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Revision History
The following table shows the revision history for this document.
Date 01/18/2012 04/24/2012 Revision Revalidated for the 13.4 release. Editorial updates only; no technical content updates. Revalidated for the 14.1 release. Editorial updates only; no technical content updates.
Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
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Chapter 1: Introduction
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Lab Exercise Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debounce Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 8 8
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
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Chapter 1
Introduction
In this lab exercise, you will explore how an Integrated Logic Analyzer (ILA) core can be inserted within the Project Navigator design environment to debug your FPGA designs. You will take advantage of ChipScope Pro Analyzer functions to debug and discover some potential root causes of your design, thereby allowing you to address issues quickly as will be shown by this tutorial. Example RTL designs will be used to illustrate overall integration flows between ChipScope and Xilinx ISE Project Navigator. In order to be successful using this tutorial, you should have some basic knowledge of ISE tool flows.
Objectives
After completing this lab exercise, you will be able to: Validate and debug your design using Project Navigator and ChipScope with ILA core and Analyzer Understand how to create an ISE project, probe an ILA core, and implement the design in Project Navigator Debug the design using ChipScope Analyzer and iterate the design using Project Navigator design environment and an SP601Platform
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Chapter 1: Introduction
Figure 1-1:
SP-601 Platform
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Design Description
Design Description
The top-level block diagram for the RTL example design is shown in the figure below. The design is comprised of a simple control state machine, multiple sine wave generators, common Push Button (GPIO_BUTTON), Dip Switch (GPIO_SWITCH), and LED displays (GPIO_LED).
Figure 1-2:
Figure 1-3:
Debounce circuit
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Chapter 1: Introduction
Debounce Circuit
When enabled, the debounce circuit provides a clean pulse or transition from a high to low on this particular example. It eliminates series of spikes or glitches when a button is pressed and released.
LED Displays
GPIO_LED_0 and GPIO_LED_0 are used to display selection status from the state machine outputs, each of which represents a different sine wave frequency - high, medium, and low.
X-Ref Target - Figure 1-4
Figure 1-4:
LED Displays
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Note: This lab also supports other two Xilinx platforms - SP605 and ML605. Use pin-out information
provided by the table below to retarget this tutorial to either SP605 or ML605.
Table 1-1:
Procedure
In this tutorial, you will complete three tasks: 1. 2. 3. Creating and Implementing a Project in Project Navigator Adding a ChipScope ILA Core to Your Design Debugging Your Design using ChipScope Pro Analyzer
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Chapter 1: Introduction
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Chapter 2
Figure 2-1:
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3.
Specify device and project properties as shown here, and click Next
Figure 2-2: Project Settings Window 4. 5. Click Finish on the Project Summary page. Right-click the pn_step1 project and select Add Source to add VHDL source files to the new project.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
6.
Locate the source files in the src directory, select all VHDL source files, and open them..
Figure 2-3: 7.
Source Files
Review the files listed in the Adding Source Files window and click OK.
Figure 2-4:
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8.
Right-click sinegen_demo and select New Source to add a new definition and connection (.cdc) file to the project.
Figure 2-5: 9.
In the Select Source Type window, select ChipScope Defination and Connection File, and then type pn_step1.cdc for the file name and click Finish. The next step is to generate all three sine wave generator cores.
10. Review the information in the Summary dialog box and then click on Finish.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Questions
11. In the Design window, select all three .xco files listed under U_SINEGEN, and then double-click the Regenerate All Cores process.
X-Ref Target - Figure 2-6
Figure 2-6: Sine Wave Generator Files in the Design Window 12. Prior to synthesizing the design, set the Keep Hierarchy option to Soft to preserve the design hierarchy and prevent the XST from performing hierarchical optimizations. To do this, right-click the Synthesize process and set the -Keep_hierarchy switch to Soft. 13. Click Apply. Now you are ready to synthesize the design. 14. Click the Synthesize process. 15. Select File > Copy Project to copy the project as pn_step2. 16. Type the project name and location, and then click OK. At this point, you have successfully created the ISE project and synthesized the design using Project Navigator.
Questions
1. 2. 3. Describe briefly of what you did in Step1: _____________________________________ What are some major circuits used in this lab?__________________________________ Which source file would you have to modify if you were to target other Xilinx boards? ______________________________________________________
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Chapter 3
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2.
ICON Options
In the Trigger Parameters tab of the ILA Options window, set the trigger parameters.
Figure 3-3:
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
For this example, set the trigger parameters as follows. Table 3-1: Trigger Parameters
Trigger Width 2 2 2 20 2 3 Match Type Basic w/ edge Basic w/ edge Basic w/ edge Basic Basic w/ edge Basic w/ edge Trigger Name TRIG0 TRIG1 TRIG2 TRIG3 TRIG4 TRIG5
5.
Select the Capture Parameters tab and examine the trigger parameters you just set
Figure 3-4: 6.
Connect each port to debugging nets. To do this: a. b. c. Select the Net Connections tab. Click Modify Connections. The Select Net dialog window appears. From the Select Net window, search for the CLK_BUFG net from the sinegen_demo hierarchy. To search for the "CLK_BUFG" net, type the "clk_bufg" string in the Pattern field and click Filter.
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d. Select the clk_BUFG net from search results and click Make Connections
X-Ref Target - Figure 3-5
Figure 3-5: 7.
Repeat Step 6 to connect the rest of trigger ports: TRIG0: search for *sel* from the U_SINEGEN hierarchy TRIG1: search for *GPIO_BUTTONS_re* from the sinegen_demo hierarchy TRIG2: search for *GPIO_BUTTONS_dly* from the sinegen_demo hierarchy TRIG3: search for *SINE* from the sinegen_demo hierarchy TRIG4: search for *GPIO_BUTTONS_db<0>* from the sinegen_demo hierarchy TRIG4: search for *GPIO_BUTTONS_db<1>* * from the sinegen_demo hierarchy TRIG5: search for *GPIO_BUTTONS_0_IBUF* from the sinegen_demo hierarchy TRIG5: search for *GPIO_BUTTONS_1_IBUF* from the sinegen_demo hierarchy TRIG5:search for *GPIO_SWITCH_IBUF* from the sinegen_demo hierarchy
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Figure 3-6: 8.
Trigger/Data Signals
Once complete, all ports turn from red to black, indicating that you have finished connecting all the clock and trigger ports to debugging nets.
Figure 3-7:
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9.
Save and close the pn_step1.cdc file Before you use the ChipScope Pro Analyzer tool to download your bitstream into your device, make sure the bitstream generation options are set properly.
10. Right-click on the Generate Programming File process and select Properties. 11. In the Startup Options category, set the -g StartUpClk switch to the JTAG Clock option.
X-Ref Target - Figure 3-8
Figure 3-8:
Now you can start generating a programming file. 12. Double-click the Analyze Design Using ChipScope process. When the process completes, the ChipScope Pro Analyzer tool opens.
Questions
4. What is the main advantage of inserting debug probes onto your post-synthesis netlist instead of adding them onto HDL design files? ________________________________ You have just finished with inserting a ChipScope ILA core and now you are ready to debug the design using ChipScope Pro Analyzer.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Chapter 4
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2.
Figure 4-1: 3. 4.
Right-click the device name in the Project list and select Configure to configure the device. In the Configuration window, select the default BIT and CDC files from Project Navigator.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
5.
Figure 4-2:
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6.
Open the Trigger Setup and Waveform windows by double-clicking on each item: Trigger Setup and Waveform.
Figure 4-3: Location of Trigger Setup and Waveform 7. 8. Select rigger Setup > Trigger Immediate. Verify that there is activity on the sine wave.
Figure 4-4: 9.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
10. On the Bus Plot window, select /sine to display the sine wave.
X-Ref Target - Figure 4-5
Figure 4-5:
Notice that this waveform does not look much like a sine wave. This is because the radix setting needs to be changed to from Hex to Sine Decimal. 11. In the Signal window, right-click /sine and select Bus Radix. Click to select the Signed Decimal check box. 12. Click the Trigger Immediately button plot.
X-Ref Target - Figure 4-6
Figure 4-6:
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13. On your board, push the Sine Wave Sequencer button (shown in Figure 1-1) until the Sine Wave Selection indicator LEDs on the board display off,on, 01.
Note: Sequencer is not working correctly. The expected behavior is a simple 2-bit counter that counts for each press (00, 01, 10, 11...). You will debug the root cause for this later in this tutorial.
14. Click the Trigger Immediately button again, and view the mid-frequency bus plot.
X-Ref Target - Figure 4-7
Figure 4-7:
15. Push the Sine Wave Sequencer button on the board until the Sine Wave Selection indicator LEDs on the board display "on, off, 10. 16. Click the Trigger Immediately button and view the low-frequency bus plot.
X-Ref Target - Figure 4-8
Figure 4-8:
17. Push the Sine Wave Sequencer button on the board until the Sine Wave Selection indicator LEDs on the board display "on, on, 11.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
18. Click the Trigger Immediately button and view the combined sine wave bus plot.
X-Ref Target - Figure 4-9
Figure 4-9:
You just verified that all sine wave selections look correct. However, the selection logic circuit is still not working correctly. Verify that all sine wave selections look correct. Verify that selection logic is working correctly: Verify that state machine is transitioning correctly and outputs are correct. Verify that state machine inputs are correct. Next, start debugging the selection logic circuit. 19. Set the following parameters: Match: set TriggerPort1 to RX -- to look for rising edge on GPIO_BUTTONS_re[1] because this is what causes FSM to transition. Trigger Conditions: M1 -- set up trigger equation to M1 Capture Settings: Windows = 10; Depth = 2
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Figure 4-10:
Note: The actual TriggerPort number for the GPIO_BUTTONS_re[1] net might not be the same as specified on this tutorial.
Information about the run progress displays at the bottom of the window. 21. Push the Sine Wave Sequencer button on the board. 22. Observe the number of windows captured.
X-Ref Target - Figure 4-11
If only one window was captured, repeat steps 21 and 22. If more than one window was captured, go to the next step.
Figure 4-11:
Notice the multiple rising edges each time you pressed the Sine Wave Seqencer button. Also, note the correct transition of sineSel, which indicates that the state machine is working properly.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
You just verified that sine wave generators are working correctly. Verify that all sine wave selections look correct. Verify that selection logic is working correctly: Verify that state machine is transitioning correctly and outputs are correct. Verify that state machine inputs are correct. 24. Set the following parameters for trigger modes and conditions: Trigger Run Mode: Repetitive Match: set TriggerPort5 to XRX -- to look for rising edge on GPIO_BUTTONS_1_IBUF, which is the input buffer for the Sine Wave Sequencer button on the board. Trigger Conditions: M5 Capture Settings: Windows = 1 Depth = 1024 Position = 512
25. Click the Run Trigger button and press the Sine Wave Sequencer button on the board until you see multiple transitions on the GPIO_BUTTONS_1_IBUF signal.
X-Ref Target - Figure 4-12
Figure 4-12:
View Waveform
Note: Your waveform might not display signal glitches at exactly the same location as shown here. This is one of the advantages of the Repetitive triggering feature.
You just verified that sine wave generators are working correctly. However, the state machine inputs are not correct. These inputs are connected directly from Push Button switches. Verify that all sine wave selections look correct. Verify that selection logic is working correctly: Verify that state machine is transitioning correctly and outputs are correct. Verify that state machine inputs are correct.
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As shown in Figure 4-12, the problem seems to point to Push Button switches, which generate glitches every time the Push Button switch is pressed and released. A debounce circuit is required for each push button switch to eliminate these glitches that result in multiple transitions. The debounce circuits have already been integrated in the provided design. To enable debounce circuits, turn on Dip switch-1, repeat steps 24 and 25, and verify there is only one transition for each button push.
Questions
5. 6. Did you have time to resolve the problem on Step 18 for extra credit? ______________ Why is a debounce circuit required for this lab?_________________________________
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications
Chapter 5
Tutorial Conclusion
Conclusion
This tutorial introduced you to the tightly integrated design flow between ChipScope Pro ILA Core Inserter and Project Navigator. It showed you how to generate IP core netlist in Project Navigator and synthesize the design. Secondly, it illustrated how to add ChipScope ILA core to the design using the ILA Core Inserter. More importantly, this tutorial guideed you through a debugging process. It showed you how to validate and debug your design using ChipScope Pro Analyzer using various triggering setups. You should now be familiar with some basic design flows and integration between Project Navigator and ChipScope Pro.
Question Answers
1. Describe briefly of what you did in Step1. You just created an RTL PlanAhead project, loaded a VHDL ChipScope design, and implemented the design. 2. What are some major circuits used in this lab? 3. debounce.vhdl - Debounce circuit fsm.vhdl - Control state machine sinegen_demo - Wrapper for Sine wave generators
Which source file would you have to modify if you were to target other Xilinx boards? UCF constraint file What is the main advantage of inserting debug probes onto your post-synthesis netlist instead of adding them onto HDL design files? You don't have to directly touch and / or modify original HDL source files, thereby eliminating the risk of making any unintentional changes
4.
5.
Did you have time to resolve the problem on Step 18 for extra credit? Hint: Judging by the waveform from Analyzer, it appeared that the output Sine wave got truncated possible due to insufficient bit vector specified in "sinegen_demo.vhd and sinegen.vhd" modules. It's currently specified as a 20-bit vector. It should be expanded to 22-bit. Feel free to modify these two modules and iterate the design.
6.
Why is a debounce circuit required for this lab? It provides a clean pulse or transition from a high to low on this particular example. It eliminates series of spikes or glitches when a button is pressed and released.
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Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications