Reliability of Commercial PEMs in Extreme Temperature Environments At Elevated Temperatures Patrick McCluskey, Kofi Mensah, and Casey O'Connor

CALCE Electronic Products and Systems Center University of Maryland, College Park, MD 20742 Voice: 1-301-405-0279; FAX: 1-301-314-9477; E-mail: mcclupa@eng.umd.edu and Anthony Gallo Dexter Electronic Materials Olean, NY
Abstract Over 97% of all integrated circuits produced today are available only in plastic encapsulated, surface mountable, commercial grade or industrial grade versions. This is especially true for the most advanced technologies, such as high-speed microprocessors. The cost, availability, and functionality advantages of these devices are causing many electronics manufacturers to consider using them in elevated temperature applications such as avionics and automotive under-hood electronic systems to ensure early affordable access to leading edge technology. However, manufacturers only guarantee the operation of commercial devices in the 0C to 70 C temperature range, and the industrial devices in the 40C to 85C temperature range. This paper describes the first study which addresses the reliability of plastic encapsulated microcircuits (PEMs) in the range from 125C to 300C, well outside the manufacturers suggested temperature limits. Previous work has indicated that PEMs sold for use in the commercial and industrial temperature ranges can often operate within the manufacturers suggested electrical parameter specifications at much higher temperatures. For example, in this study, a Motorola MC68332 microcontroller, which is widely used in avionic systems, remained fully functional to 180C. This is in accordance with previous work that indicated no fundamental constraints to the operation of silicon devices at temperatures up to 200C. However, this study also revealed that industrial grade, plastic encapsulated MC68332 devices had less than half the lifespan at 180C of similar MC68332 devices packaged in hermetic ceramic packages. In addition to the MC68332, the other nine types of plastic components studied had a shorter lifespan at 180C than their ceramic packaged counterparts. Outgassing of flame retardants with the associated catalysis of the growth of intermetallics was determined to be the principal cause of failure in the plastic components. Further studies conducted on 84-lead PQFP leadframes encapsulated in two different molding compounds revealed that the plastic encapsulant itself begins to lose its ability to insulate leads at temperatures greater than 250C and can actually combust at temperatures greater than 300C. Both insulation resistance degradation and cracking were found to be more prevalent in novalac than biphenyl. In summary, these studies have shown that while plastic encapsulated microelectronics can operate at temperatures above 125C, they have less than half the life of ceramic microcircuits at 180C and they begin to show signs of insulation resistance degradation after 300 hours at 250C.

LIFETIME-LIMITING FACTORS FOR COMMERCIAL POWER MOSFETS AT HIGH TEMPERATURES

W. Wondrak1, A. Boos 1, W. Schaper1, J. V. Manca2, B. Parmentier3, and R. Peat4 DaimlerChrysler AG, Research and Technology, Goldsteinstr. 235, D-60528 Frankfurt, Germany 2 Limburgs Universitair Centrum, Institute for Materials Research, Wetenschapspark, B-3590 Diepenbeek, Belgium; 3 Etudes et Productions Schlumberger, 26, rue de la Cave, F-92140 Clamart, France 4 AEA Technology, Products and Systems, F5 Culham, Abingdon, Oxfordshire OX14 3DB, United Kingdom
Abstract
In this paper, we report on the impact of cyclic temperature stress up to 200C on commercial power MOSFETs. We investigated 60V MOSFETs, with a maximum rating for ID of 60A. Electrical characterisations and acoustic microscope investigations after thermal shock tests and after pressure cooker tests (PCT) were conducted to give informations on the failure modes and reliability at accelerated temperatures. As a result, commercial power MOSFETs in plastic packages off-the-shelf can be operated at temperature levels of 200C, but care must be taken if the devices have to operate in humid environments.
1

Introduction
Power devices are key components for electronically controlled actuators needed in automotive and aerospace systems. In future applications like transmission control or motor control, higher operation temperatures will be required going up to 200C. For many of these applications power MOSFETs are ideal candidates. Understanding the behaviour and the degradation mechanisms of such devices in harsh environments will enable to define guidelines for their implementation in high-temperature applications. In addition to temperature-accelerated sensitivity of electronic devices to electrical stresses, thermo-mechanical stress is a major damage source [1-4]. In this paper, we focus on the impact of cyclic temperature stress on commercial power MOSFETs. We investigated 60V MOSFETs, with a maximum rating for ID of 60A in conventional TO220 packages, specified for a maximum temperature of 175C. In the package, the dies are mounted with a lead-rich solder on the leadframe, and surrounded by a molding compound with a glass transition temperature of about 185C. Data sheet values for threshold voltage and on-resistance were 2 - 4V, and 18m .

Thermal Shock Stressing

The stress conditions for thermal shock were similar to quality standards in semiconductor industry (IEC 68 or MIL SPEC 883), but with increased temperature levels (-40 to +200C). Figure 1 shows the temperature profile in the thermal shock chamber employed. One cycle from 40 to 200C and back took about 60 minutes. Dwell times were roughly 25 minutes at high and low temperature. The test devices were cycled in groups of 5 elements up to 2000 cycles.

Temperature (C)

time (h)
Fig. 1: Temperature profile in the shock chamber

The measured electrical parameters were threshold voltage vth, drain leakage current I D , gate leakage current IG, breakdown voltage UBR , and on-resistance Ron.
Fig. 2 shows the normalized threshold voltage versus the number of thermal cycles. No significant changes can be observed.

1,02 1,01 1 0,99 0,98 0,97 0,96 0 500 1000 1500 2000

# of cycles

Fig. 2: Normalized threshold voltage of power MOSFETs after thermal shocks.

100

gate current (pA)

80 60 40 20 0 0 500 1000 1500 2000

# of cycles

Fig. 3: Gate leakage current of power MOSFETs after thermal shocks.

40 35

on-resistance (m )

30 25 20 15 10 5 0 0 500 1000 1500 2000

# of cycles

Fig. 4: On-resistance of the power MOSFETs after thermal shocks.

Fig. 3 shows the measured gate leakage currents of the devices after thermal cycling. The parameter variations are rather due to noise in the measurements than to real changes in the devices. The only electrical parameter showing a systematic shift is the on-resistance. A steady increase with time was observed (see fig. 4), which amounts to 5 /cycle. This allows us to determine a lifetime when a maximum allowed on-resistance must not be exceeded. This effect is generally observed after thermal cycling of power devices, because thermomechanical stress leads to cracks in the solder joint and thus to an effective decrease of the contact area. No failures due to bonding wires or dies itself have been observed. The changes in parameters are small, we noticed only a change in color of the packages and oxidation of the leads. No visible defects could be observed. In order to find out, whether small cracks have formed, which allow water penetration, pressure cooker tests at stressed devices were performed.

Pressure Cooker Tests High temperature can lead to irreversible changes in polymers resulting in hardening, cracking and delamination. This would induce high sensitivity of the devices against water. In
order to find out, whether small cracks have formed which allow water penetration, pressure cooker tests at stressed devices were performed (121C, 2 bars pressure). Electrical characteristics were measured after 96 hours and after 168 hours, respectively. The results indicate, that the devices are very sensitive to humidity after thermal shock, so that probably delaminations had occured. After 1000 cycles, the gate leakage current at Vg = 20V of all devices exceeded 1 A, which was our criterium for gate integrity. In fig. 5, the evolution of drain leakage current of the power MOSFETs during thermal cycling from 40 to +200C is shown before and after pressure cooker test. Test voltage was 60V with gate and source grounded. It can be recognized, that moisture ingress affects strongly the device behavior even after only 200 cycles. After 500 cycles, it is still in an acceptable range, but after 1000 cycles, the drain current has grown to a magnitude which affects possible applications. Since no mechanical defects could be observed, scanning acoustic microscopy was employed to reveal potential delaminations in the packages.

1,00E-02 1,00E-03 1,00E-04 1,00E-05 1,00E-06 1,00E-07 1,00E-08 1,00E-09 1,00E-10 1,00E-11 0 500 1000 Number of cycles 1500 2000

Fig. 5

Drain leakage current of power MOSFETs after thermal cycling from 40 to +200C before and after pressure cooker test

Scanning Acoustic Microscopy Investigations

Delaminations are opening paths for water penetration in packaged devices. By scanning acoustic microscopy two types of delamination could been observed. The first type of delamination is between the metal plane and the plastic and is present on all devices tested. This is obvious from the top-side investigations (fig. 6). Even in the virgin devices (fig. 6a), a relative big fraction of the interface between lead-frame and mold material shows weak adhesion. After 500 cycles, the brighter appearance of the picture indicates that almost the whole interface between plastic and leadframe, and also between plastic and die is degraded. The second type of delamination could be observed on the pictures from the bottom-side of the packages (fig. 7).

Chip
Delamination

Bonding wires

a)
Fig.6

b)
Scanning acoustic microscope images from top side after 0 and after 500 cycles

Die

Void Leadframe

a)
Fig. 7

b)
Scanning acoustic microscope image from bottom side after 0 cycles(a) and after 500 cycles (b)

Prior to cycling, the interface between die and leadframe is dark and shows only some small voids. After 500 cycles, big voids have emerged. This more than 50% delamination can be estimated to increase the thermal resistance of the total package by 25%. In addition, bright spots have developed at the corners of the chip, where the highest thermomechanical stress is expected. This is an indication for beginning crack propagation. Therefore, the limit of the high-Pb solder joint is almost reached under these conditions. For comparison, if we admit an increase of the on-resistance of the devices by 2 m , the resulting lifetime would be 400 cycles.

Conclusions
As a result, commercial power MOSFETs in plastic packages off-the-shelf can be operated at temperature levels of 200C. They withstand a number of thermal cycles without severe electrical degradation, but care must be taken if the devices have to operate in humid environments. For such applications, new molding materials or adhesion-promoting layers are strongly requested. With the proposed combination of tests, the suitability of these new materials can be investigated easily. The conventional die attach system is almost at ist limit under the conditions descibed. In order to achieve long lifetimes, new solder materials have to be implemented.

Acknowledgements
This work was supported by the European Commission under contract no BRPR-CT-0596 (REDHOT).

References
[1] [2] [3] [4] F. P. McCluskey, R. Grzybowski, and T. Podlesak, High Tenmperature Electronics, CRC Press 1996 H. Berg and E. Wolfgang, Microelectronics Reliability 38 (1998), pp. 1319-1323 M. Ciappa and W. Fichtner, Proc. of the IRPS 2000, pp 210-216 W. Wondrak, Microelectronics Reliability 39 (1999) 1113-1120

HIGH TEMPERATURE TIME DEPENDENT DIELECTRIC BREAKDOWN OF POWER MOSFETS

1

J.V. Manca, 2W. Wondrak, 1K. Croes, 1W. De Ceuninck, 3B. Dieval and 1L. De Schepper
1

Limburgs Universitair Centrum, Institute for Materials Research, Wetenschapspark, B-3590 Diepenbeek, Belgium; Tel. : +32/11/268826 ; Fax : +32/11/268899 ; e-mail : jean.manca@luc.ac.be 2 DaimlerChrysler AG, Research and Technology, Goldsteinstr. 235, D-60528 Frankfurt/Main, Germany 3 present Address: Alcatel, Stuttgart, Germany.

Abstract - Time Dependent Dielectric Breakdown (TDDB) has been studied by means of in-situ leakage current measurements of power MOSFETs at various voltages (30V-45V) and temperatures (175C-225C). A statistical analysis of the results yields information on the underlying failure time distribution, failure mechanisms and lifetime. Introduction - MOSFETs are key components for many of the new high temperature applications. In these devices, most failures are due to gate-oxide breakdown, which depends on the applied voltage and on the temperature. For the thermal acceleration of dielectric breakdown, widely differing activation energy values, ranging from 0.2 to 1.1 eV, have been reported in various studies, depending on oxide thickness and ambient temperature. For voltage acceleration, two competing models exist for lifetime calculation, leading to ambiguous lifetime predictions. In-situ leakage current measurements have been performed in order to study the dielectric breakdown behaviour of the oxides used in two types of high temperature MOSFETs. In this paper the presented results have been obtained with one type of commercial power MOSFET (60V,70A). Failure Time Distribution - An essential step in reliability studies is the determination of the underlying failure time distribution. The choice of the failure time distribution is of great importance because all conclusions drawn from a statistical analysis will depend on it. Lifetime predictions can vary orders of magnitude depending on the distribution used. The extrapolation to low percentiles (an x%-percentile is defined as the time that x% of the total population of components have failed) is particularly sensitive to the choice of the underlying distribution of failure times. For TDDB, Weibull distributions are often used since this distribution fits with the weakest-link character of the breakdown process, but also the lognormal distribution is often encountered in the literature. Two important aids in order to make a correct choice of failure distribution are : (1) to measure a large number of samples and (2) to use a statistical technique based on Pearson's correlation coefficient. For the present study, long term (27 days) TDDB-experiments have been performed at 200C with a gate voltage of 41V on a population of 40 samples (batch1). Each sample was connected with a series resistance and the leakage current was monitored for each individual sample by measuring the voltage over the series resistance. The set of failure times has been analyzed with the statistical software package FAILURE. This software package incorporates a method which allows to make an objective distinction between lognormal and Weibull failure distributions. The result of this Lognormal/Weibull-test was that the Ho-hypothesis (Ho = lognormal) was NOT rejected in favour of HA = Weibull. The significance level of the test was 10%. Due to the large number of samples the power of the test was high : 78%. In the figure below the failure times have been plotted on a cumulative lognormal plot, confirming the good choice of the failure distribution.

Figure 1 : Lognormal-plot of TDDB-data for power MOSFETs stressed at V = 41V and T = 200C. Temperature Dependence - To evaluate the dielectric breakdown resistance of the power MOSFETs at high temperatures, TDDB-experiments have been performed at various elevated temperatures and various voltages.

The number of samples tested for each stress condition are listed in the table below. Temperature 37 V 39 V 41 V 43 V

175C 10 samples 10 samples 10 samples 200C 9 samples 10 samples 10 samples 225C 10 samples 10 samples 20 samples 9 samples Table 1 :stress conditions and number of samples for the TDDB-experiments on power MOSFETs (batch2). A statistical analysis of the reliability data has been performed using the software package Failure. An unique feature of Failure is that the estimation of model parameters is done by using the so-called maximum likelihood method. This method numerically maximizes a function depending on the data and on the model parameters. For the case of the considered TDDB-data it is has already been shown that lognormal cumulative monomodal failure plots represent the failure data properly. In this paper, the temperature dependence of the life time of the MOSFETs at high temperatures is investigated. Analysis of the life time data shows that the temperature dependence of the life time ! is well described by means of the Arrhenius relation :

! = A exp( kE aT ) B
with kB the Boltzmann constant, T the absolute temperature and Ea the activation energy as model parameter. In the figure below, the TDDB-data of the experiments performed with 41V at various temperatures is represented on a lognormal cumulative failure plot. The lines on the plot are the maximum likelihood fits of the data using the Arrhenius relation. From the plot it is clear that the Arrhenius relation forms a good description of the temperature dependence of the high temperature TDDB-data.

Figure 2 : Lognormal-plot of TDDB-data for V = 41V and T = 175C;200C;225C ; the symbols are the experimental life times, the full lines are the fits based on the Arrhenius relation. From this analysis scale parameter, shape parameter and activation energy can be obtained. In the next table the estimates together with the lower and upper bounds (confidence level = 95%) are listed for the reference temperature of 200C : Parameter Name Estimate Lower Bound (95%) Upper Bound (95%)

Scale parameter at 200C 191 164 223 (minutes) : Activation energy (eV): 1.06 0.920 1.20 Shape parameter : 0.500 0.407 0.631 Table 3 : Statistical fit parameters of TDDB-data (V = 41V and T = 175C;200C;225C). The analysis performed above has also been performed for the experiments with V = 37V and V = 39V. In the next tables the corresponding model estimates together with the lower and upper bounds are listed for the

Parameter Name

Estimate

Lower Bound (95%)

Upper Bound (95%)

Scale parameter at 200C 688 609 778 (minutes) : Activation energy (eV): 1.20 1.09 1.31 Shape parameter : 0.337 0.265 0.444 Table 4 : Statistical fit parameters of TDDB-data (V = 37V and T = 175C;200C;225C).

Parameter Name Scale parameter at 200C (minutes) : Activation energy (eV): Shape parameter :

Estimate 334 1.06 0.452

Lower Bound (95%) 284 0.907 0.357

Upper Bound (95%) 393 1.21 0.593

Table 5 : Statistical fit parameters of TDDB-data (V = 41V and T = 175C;200C;225C). Voltage dependence- The relationship between the electric field at breakdown Ebd and the time to breakdown tbd at room temperature has been formulated by the so-called reciprocal field model (ln(tbd) ~1/Ebd) and the linear field model (ln(tbd)~ -Ebd). In order to study the voltage dependence at high temperatures of gate oxide breakdown in power MOSFETs, experiments have been performed at 200C with various elevated voltage levels. In the figure below predictions of the lifetime (t50%) at realistic operation conditions (20V/200C) have been performed using both the E-model and the 1/E-model and the results from the experiments in table 1 . Predictions have been performed in two ways : (1) calculations using only the t50%-points at the various stress conditions, and (2) calculations using the maximum likelihood method (Failure). The predictions towards the 20V/200C;25V/200C;30V/200C-levels show that for both models too optimistic lifetimes are obtained by taking into account only the t50%-points. Predictions using the maximum likelihood method (Failure) show a difference of almost a factor 100 for the lifetime at the 20V/200C-condition. The results of a recent set of experiments with a broad range of voltages (30V-45V) will allow to better distinguish between the two models.
1e+6 1e+5 1e+4 1e+3
50% (days) t

E-model : t50 1/E-model : t50 1/E-model : Failure E-model : Failure

1e+2 1e+1 1e+0 18 20 22 24 26 28 30 32

Voltage (V) Figure 3 : Lifetime predictions for gate oxides at various voltage levels at 200C using the E- and the 1/Emodel and two fitting methods (only t50%-points / Maximum Likelihood = Failure).

Conclusions - From the statistical analysis of the high temperature TDDB-data the following conclusions can be drawn: (1) the TDDB-data are well represented by a monomodal lognormal cumulative failure plot ; (2) the Arrhenius relation forms a good description of the temperature dependence of the high temperature TDDB-data ; (3) Ea , the activation energy in the Arrhenius relation, is in the order of 0.9-1.3 eV ; (4) a maximum likelihood method leads to improved lifetime predictions and (5) the validity of the E- or the 1/E-model is under study with high temperature TDDB experiments in a broad voltage range (30V-45V). ACKNOWLEDGEMENTS -The authors would like to thank the European Commission for the financial support of the BRITE-EURAM project REDHOT.

Applications Targeted by Reliable High Temperature Electronics

Ben Gingerich, Phil Brusius Honeywell Solid State Electronics Center 12001 State Highway 55 Plymouth, Minnesota 55441 (612)-954-2104, (612)-954-2897 fax: (612)-954-2764 e-mail: ben.l.gingerich@honeywell.com

Introduction
This paper presents a set of reliable high temperature electronic components that have been developed to target multiple applications in hot hostile environments. We present the various applications and our understanding of the reliability and temperature requirements. In addition we present the reliability testing conducted with respect to random failures and wear out mechanisms at high temperature that support the capability of the electronics to meet these applications needs. Over the years numerous papers presented at this conference have highlighted requirements which have had various temperature and lifetime requirements. These applications have all had a similar need for reliable and predictable behavior of the electronics at elevated temperatures. This paper will present reliability data taken on a set of electronic components fabricated in Silicon On Insulator, SOI, CMOS. These parts have been designed from ground up for reliable operation at high temperature with long lifetimes. Over 2,000,000 equivalent device hours at 225C have been gather on a family of components with demonstrated failure rates of greater than 500,000 hour Mean Time Between Failure, MTBF. The applications targeted by these electronics range from down hole petroleum and geothermal instrumentation to smart sensors and actuators on aircraft gas turbine engines. This paper will discuss the range of temperatures and lifetime requirements that are represented by these diverse applications. Additional applications that have been discussed include internal combustion engine emission controls along with industrial petrochemical processing smart sensors.

High Temperature Applications

A number of applications have been presented previously that require reliable high temperature integrated circuits. The applications range from down hole drilling and monitoring activity for geothermal and petroleum applications to advanced instrumentation for aircraft turbine engines. The temperature range and lifetime requirements vary significantly. The range of temperature and lifetime requirements for various applications are shown in Table 1. The lifetime requirements and temperature cover 90% of the applications within the various market segments.

Market / Application Petroleum Measurement While Drilling Permanent Gauges Geothermal Well Montitoring Gas Turbine Engines Heavy Duty Diesel Engines Automotive Industrial Process Instrumentation

Temp. Range, C -40 to 200 -40 to 200 -40 to 300 -55 to 300 -40 to 200 -40 to 160 -40 to 300

Lifetime At Temp. Hr 100 to 500 50,000 25,000 50,000 25,000 5,000 50,000

Shock & Vibration Sever Minor Minor Sever Moderate Moderate Minor

Table 1: Applications Temperature & Lifetime

To address problems of reliable high temperature operation a new set of integrated circuit components has been introduced as HTMOS!. These integrated circuit electronics have been developed to address aircraft gas turbine engine instrumentation and meet the high reliability requirements. The electronics were target to meet 225C and 50,000 hours of operation at that temperature. To make valid reliability projections a database with more than two million device hours at the targeted maximum temperatures has been developed and failure analysis completed on failed components. With this database projections of lifetime and failure rates can be completed for applications using these integrated circuits. These same components can be used as the building blocks for a other applications requiring high reliability. Reliability Factors For Integrated Circuits For many products and integrated circuits the reliability of a given product has 3 distinct phases that are commonly referred to as the bathtub curve. In the early hours of the product lifetime, the failure rate is relatively high, but infant mortality can be screened out with effective testing or burn-in. In the useful years of the product lifetime the failure rate should be low. These failures are caused by random defects or environmental events. After the useful life of the product, various facets of the product wear out and the failure rate increases rapidly. These different failure rate phases provide a curve that resembles a bathtub. If the product is manufactured and tested properly, the early defects are observed and screened out such that products with these defects are not shipped. If the product is designed properly, the 3rd or wear out phase occurs after the useful life of the product. This then results in products that have an appropriate useful life with a low failure rate for the intended application. With respect to the high temperature integrated circuits presented here, we have performed different types of tests to assure that the manufacturing defects have been properly screened out and that the products do not have any lifetime limiting defects. A burn-in at 250C and a three temperature test after burn-in is used to eliminate infant mortality and minimize defects in shipped parts. Life tests are performed at these same temperatures after the standard product screening to develop a reliability database to verify that the failure rate is relatively low during the useful life of the product. In addition at the beginning of the integrated circuit development highly accelerated tests were performed on special test structures to assure design requirements such that the wear out mechanisms do not occur during the planned useful life of the product. These tests are described in the following sections.

Lifetime Testing To develop a set of reliable high temperature integrated circuits, a number of lifetime tests must be conducted to establish design rules. In order to obtain data in a reasonable period of time, highly accelerated tests are performed on special test structures to project the products end of life. By using special test devices, conditions too extreme for the product can be utilized so as to accelerate known failure mechanisms. In this manner tests a few months in duration may be the equivalent of years of normal life. There are a number of known wear out mechanisms that could limit the life of an integrated circuit. Many of these are packaging related. One of the greatest areas of concern is the wire bonds because often two different materials are connected. When different materials are together at high temperature, the connection may become resistive and subject to failure. Most integrated circuit chips employ aluminum metalization as the interconnect on the chip. Most ceramic hermetic packages have gold metalization as the wire bond landing material. A wire connecting the chip to the package is going to have a mismatch at one end or the other. To evaluate the bond lifetimes, an experiment was set up where the resistance of different interconnecting schemes was monitored at 300C. The experiments covered a full spectrum of all aluminum, all gold, and a mixture with interfaces at the chip and on the package wire bond pad. The results of this testing are summarized in Table 2. The only somewhat surprising information in this table is the 3rd row, where aluminum wires on gold package pads have not failed in 17,000 hours. This is especially interesting in light of the 4th row where gold wires on the aluminum chip pads failed in 30 hours. This situation in the 4th row where the aluminum interfaces with the gold on the chip is believed to be due to the relatively small amount of aluminum diffusing into the relative large gold ball bond. On the other hand the situation in the 3rd row provides plenty of aluminum to diffuse into and saturate the thin film package gold. Wire bond pull strength measurements were also conducted at 15,000 hours. These tests have confirmed that the bonds as shown in the 3rd row are robust. This life testing of the aluminum wires on the gold pads is equivalent to more than 15 years at 225C and will meet the needs of a reliable system. I Chip Metal Wire Type Package Bond Pad Metal Al Au Au Au Time @ 300C (Hours) 17,000 17,000 17,000 30 Resistance Change

Al None None Al

Al Au Al Au

No change No change No change Failed open

Table 2: Summary of Wire Bond Resistance Additional testing has shown that the type of interconnections described above can withstand 500 thermal cycles to 300C with minimal degradation. This data has been presented in more detail in reference 1. In some applications where significant vibration is present, such as down hole measurements while drilling, wire resonance may be an issue. With proper design of the

package the wires can be less than .080 inchs in length such that the lowest resonant frequency of commonly used 1.25 thousands of an inch aluminum wire would be on the order of 26,000 Hz. The resonant frequency of a similar sized gold wire could be a low as 10,000 Hz. With the low mass of the aluminum wires the shock and vibration are not a problem. In addition to packaging problems there are a number of potential life limiting failure mechanisms on the silicon integrated circuit chip. Probably the most important of these problems is electromigration. Electromigration is the phenomena in which metal ions move in the chips thin film conductors. This movement is proportional to current density and temperature and may result in open or short circuit failures. The electromigration lifetime of a semiconductor chip is dependent on its metalization system and the designed maximum current density. This relationship is established by highly accelerated testing of test structures. Tests have been performed many times on the AlCu metalization system used in these products. These tests have been performed at 250C a number times over the last 20 years. The results of this testing have shown .5mA/m2 will meet the 50,000 hours at 225C objectives. This is the lifetime for one percent of the parts to fail. The products designed with this requirement will also operate for over 20 years at 150C. Additional development efforts have been demonstrated on a tungsten metalization process that would offer the capability to operate for long periods of time at temperatures above 300C. Another common integrated circuit wearout mechanisms is time dependent dielectric breakdown (TDDB). TDDB has been shown to conform with physical and analytical models to 400C as discussed in reference 2. TDDB has a modest temperature effect and for the most part this means that a reliable gate oxide process for normal temperatures will be reliable at high temperatures. For these integrated circuits a reliable gate oxide process with more than 1,200,000 device hours at 150C and more than 800,000 device hours at 250C has been established. Another prominent life limiting failure mechanism is hot carrier effects. This effect results from high electric fields due to smaller transistor sizes. The small geometry of modern day integrated circuits cause high electric fields that can energize electrons and holes to be hot. These energized hot carriers are accelerated by the high fields powering them into the silicon / oxide interfaces. These hot carriers can change transistor characteristics. Interestingly, this phenomena becomes more severe at colder temperatures, and thus with careful design practices is not life limiting at temperatures above room temperature. Data supporting this claim has been published elsewhere and is described in detail in reference 3. It is important to note that Honeywell uses Silicon on Insulator (SOI) starting material for its high temperature products. This material has some unique advantages for high temperature operation as noted in reference 4, such as low leakage currents at high temperature. Other aspects of this process have also been characterized at temperatures greater than 250C and found to be predictable and not reliability limiting. The SOI technology and its applications are discussed in more detail in reference 5. With the various technology life limiting failure mechanisms characterized, we can then address them in the product development phase. These steps have been taken early in the development phase and applied to a set of design rules which ensure a robust design that will meet the targeted 5 year lifetime at 225C.

Product Life Testing The burn-in process is often used to assure that defects that cause early failures are screened out and the product characteristics are stabilized. The packaged integrated circuits are operated at elevated temperatures (HTMOS uses 250C) with electrical bias ranging from 2 to 14 days. Weak or marginal parts will normally fail in this time and are flagged by final testing over the full temperature range. In this fashion weak parts with infant mortality are screened out and not shipped into the field. If the lifetime limiting failure mechanisms are designed out and infant mortality is screened out, other random, defect or process related mechanisms may be evaluated in a product life test. In such a test quantities of parts that have received normal screening are biased at elevated temperature for extended periods of time. The parts are periodically tested for correct operation. Such tests can be used to develop a reliability database that can be used to gauge the failure rate to be expected in the field under normal usage. To establish a database a number of such life tests have been performed on different part types at 250C. Once a reasonable number of hours in life test has been established the Mean Time Between Failure (MTBF) can be calculated. To develop the database a selection of analog and digital parts have been chosen to provide a mix that would characterize the HTMOS family of products. The parts used were a Quad Operational Amplifier, an Eight Bit Microcontroller, a 256K Bit Static Memory, and a 16:1 Multiplexer. These products have completed over 2,220,000 equivalent hours at the design target temperature of 225C. The detail regarding the tested parts and the calculated MTBFs are shown in Table 3. This table shows that the MTBF for the product family is over 300,000 hours at 225C Part Type Actual Device Hours @ 250C 424,000 178,000 149,000 52,000 803,000 Equivalent Device Hours @ 225C 1,394,000 388,000 325,000 114,000 2,220,000 MTBF @ 225C (Hours) 334,000 423,000 105,000 56,000 302,000 Equivalent Device Hours @ 150C 25,000,000 7,000,000 5,900,000 2,000,000 40,000,000 MTBF @ 150C (Hours) 6,000,000 7,600,000 1,890,000 446,000 5,457,000

Op Amp 83C51 SRAM Mux All

Table 3- MTBFs Projected to 225C and 150C With Activation Energy Of Ea=0.7eV

The failures experienced in these life tests have not been catastrophic. They were not of the type that would be life limiting such as a dead short or an open. As an example, an SRAM failure was a single bit failure. If encoding algorithms are used which can correct and detect on fault this failure would not be a system failure. The two op amp failures were due to (1) high leakage current, 15 nA measured at 225C and (2) a slightly high input voltage offset of 7.6 mV measured at 225C. In short, the above life testing has shown that integrated circuits designed for high temperature applications can be reliable at temperatures up to 225C. These circuits can be used for long life applications and with the use of a reliability database predictable performance and lifetime expectations can be made. With the application of redundancy and fault tolerance techniques instrumentation or data acquisition systems can be designed to last for many years at elevated temperatures with a high level of reliability.

Passives, Boards, and Other Issues Instrumentation and data acquisition systems will require more than integrated circuits that operate at high temperature. A number of sensors have been demonstrated to operate at high temperatures reliably. It has typically been the electrical interface circuits that have had reliability issues. These circuits may well require resistors and capacitors. In addition to the HTMOS line of integrated circuits a thin film resistor process implemented on chip has shown less than 1.7% change in resistance after 1700 hours biased at 250C. These results are discussed in more detail in reference 5. These resistors have been integrated onto silicon integrated circuits and they have been fabricated as a resistor arrays with specific values. In addition at the board level power wirewound resistors and thick film resistors have been demonstrated to meet high temperature requirements. The details of this testing are discussed in reference 6. Wirewound resistors have survived 10,000 hours storage at 300C and 1,000 thermal cycles from -55C to 225C with less than 4% change. Thick film resistors have been shown to meet a 5% tolerance in the 175C to 250C range under the same kind of conditions. There are several kinds of capacitors that can adequately serve most high temperature needs. Ceramic NPO capacitors with a low temperature co-efficient of capacitance have been shown to be stable to 500C as reviewed in reference 7. Higher value ceramic X7R capacitors with a higher dielectric constant have been demonstrated to be stable through 5000 hours at 200C in reference 8. These same devices have undergone more than 1000 hours of life testing at rated voltage and 300C without failure or significant current or resistance degradation as reviewed in reference 9. (This testing is equivalent to about 5 years at 200C.) It is interesting to note that barium titanate X7R capacitors tend to age a few per cent per decade of time when biased below 120C and actually de-age at a temperature of 150C as described in reference 10. With respect to reference 10 higher value wet tantalum capacitors age gracefully for 2000 hours at 200C, but may lose their hermetic seal and slowly degrade after that. Solid tantalum capacitors aged as much as 4% through the first 1000 hours at 200C, but were stable for the next 4000 hours. A s can be seen from the referenced data presented here several alternatives for high temperature capacitors exist which can meet reliable long life time operation. To meet reliable high temperature operation it is an important consideration for all high temperature capacitors to be derated for voltage. Voltage is more of an accelerating factor than temperature for capacitors. A figure of merit that can be used with a capacitor is to choose one rated at least 2x above the voltage required. Resistors and capacitors, such as those noted above, as well as packaged integrated circuits can be soldered to an appropriate printed wiring board with high temperature solders. Normal FR-4 boards will not last above 150C. Polyimide boards with all the copper traces embedded have been shown to last 6000 hours at 250C during Honeywells integrated circuit life tests. Such boards can be made for through hole connections which are generally more reliable with temperature cycling than surface mount. More specialized applications may require ceramic boards. The thick film conductors on a ceramic board are generally fired at temperatures from 800C to 1000C and are not affected by the much lower application temperature. The eutectic tin-lead (37/63) solder used for commercial applications will flow at 183C and is not a good choice for high temperature applications. There are a number of high lead / low tin content solders (95/5 and 90/10) which melt near 300C and can be useful at temperatures of 250C and less. The fatigue properties of these and other solders have been studied by CALCE in reference 11 among others.

Improving Reliability With Multi-Chip Modules and ASIC Integration Experience indicates that most of the failures for a high temperature module will be related to an interconnect, such as the solder connections to a board. The failure rate models in MIL-HDBK-217 on Reliability Prediction of Electronic Equipment indicate that the board failure rate will be directly proportional to the number of solder connections. Thus, it would be advantageous to minimize the number of solder connections. One method of minimizing the number of solder connections would be to utilize a MultiChip Module (MCM) in which most of the connections are inside the hermetic package. As noted above, sealing 5 components with 40 leads each inside a single MCM package with 40 leads would reduce the interconnect failure rate by nearly 80%. In addition the use of an MCM can add to the reliability of the high temperature system because of the smaller size, lighter weight, reduced board size and connectors. High temperature MCMs have been fabricated for two aircraft turbine engine applications. An example of the improvements possible with a MCM approach are shown in Table 4. In Table 4 an additional example of a down hole data acquisition system has been added as an example to indicated the savings potential for a typical down hole gauge electronics. MCMs labeled Case 1 and Case 2 are actual high temperature MCMs fabricated for aircraft engine applications. The lower complexity MCM, Case 2, is also being presented at this conference as an application paper for a vibration sensor. This MCM has passed tests for wire resonance (vibration), cover resonance, high voltage insulation resistance, residual gas analysis, impact shock (20gs, 11mS both directions, all axis), thermal shock (-65C to 150C), moisture resistance, salt atmosphere, wire bond strength, die and capacitor bond strength. This MCM is currently being qualified at a higher assembly level for an application on a military aircraft engine program. Turbine Engine Case 1 SCP MCM
8 469 97,000 37,000 27,000 166% 1 64 97,000 273,000 71,600

Data Acquisition SCP MCM

Number of Components Number of Pins Total Chip MTBF (Hours) Connections MTBF (Hours) 2 Board/MCM Combined MTBF MCM Improvement in MTBF
1

Turbine Engine Case 2 SCP MCM

4 39 1,500,000 448,000 345,000 146% 1 9 1,500,000 1,940,000 848,000

10 264 82,000 66,000 36,600 72%

1 64 82,000 273,000 63,000

Table 3- Multi-Chip Module MTBF Improvement Over Single Chip Package and Board Approach. 1. Based on Reliability Database Projected to 150C 2. Based on MIL-Hdbk-217

The use of higher levels of integration can be completed with the use of a gate array Application Specific Integrated Circuit, or ASIC. Two mask programmable gate arrays have been developed within the HTMOS family to provide higher levels of integration as discussed in reference 12. These products can significantly increase the reliability of the system by integrating several digital functions onto a single chip.

Reliability Conclusions A basic set of 15 Integrated Circuits has been developed specifically for reliable high temperature operation. The integrated circuits have been targeted and demonstrated in aircraft turbine engine distributed control applications where lifetimes of 50,000 hours are required in harsh operating environments with temperatures reaching as high as 300C for short durations. The introduction of these high temperature products coupled with reliable high temperature passives, boards and solders offer a unique opportunity to significantly increase the reliability of instrumentation and data acquisition electronics. The various integrated circuits have undergone 250C life testing and a statistical database has been developed to predict integrated circuit failures at temperature. The database can be used as a predictor of reliability and expected failure rates in hot hostile environments such as the applications shown in Table 1. Additional levels of integration with improvements in reliability can be achieved by including digital ASICs, implemented in gate arrays and MCM packaging. These approaches can significantly reduce the number of interconnects to the board increasing the reliability at the board level by a factor of two or more. The addition of digital ASICs and MCM packaging not only increases reliability but also reduces the overall size of the data acquisition electronics. This two fold benefit can also help where small size is an attractive feature. When high temperature electronics are coupled with appropriate passives, boards, and circuit packaging techniques the reliability of the system can be increased to provide a high confidence of meeting system lifetime goals.

References 1. P. Brusius, B. Gingerich, M. Liu, B. Ohme, and G. Swenson, Reliable High Temperature SOI Process, Transactions of Second International Conference on High Temperature Electronics, Charlotte, N.C. 1994, p II-15. 2. J. Suehle, P. Chaparala, C. Messick, W. Miller and K. Boyko, Field and Temperature Acceleration of Time-Dependent Dielectric Breakdown in Intrinsic Thin SiO2, 1994 International Reliability Physics Proceedings, p 120. 3. F. P. McCluskey, R. Grzybowski, and T. Podlesak, editors, High Temperature Electronics, CRC Press, New York, NY, 1996, p 32. 4. P. Brusius, S.T. Liu, J. Kueng, B. Ohme, T. Fabian, SOI Devices for High Temperature Applications, Transactions of Third International High Temperature Electronics Conference, Albuquerque, Jun 1996, p XI-3. 5. P. Brusius, Some Reliability Aspects of High Temperature ICs, Transactions of Fourth High Temperature Electronics Conference, Albuquerque, Jun 1998, p 151. 6. J. Naefe, R.W. Johnson, and R. Grzybowski, High-Temperature Storage and Thermal Cycling Studies of Thick Film and Wirewound Resistors, Transactions of Fourth High Temperature Electronics Conference, Albuquerque, Jun 1998, p 191. 7. R. Grzybowski, Characterization and Modeling of Ceramic Multilayer Capacitors to 500C and Their Comparison to Glass Dielectric Devices, Proceedings Thirteenth Capacitor and Resistor Technology Symposium, 1993, p 157. 8. R. Grzybowski, Long Term Behavior of Passive Components for High Temperature Applications - an Update, Transactions of Fourth High Temperature Electronics Conference, Albuquerque, Jun 1998, p 207. 9. J. Day and M. Roach, Ceramic Dielectric Performance Under High Temperature Life Test, Transactions of Fourth High Temperature Electronics Conference, Albuquerque, Jun 1998, p 181.

10. C. A. Harper, editor, Handbook of Components for Electronics, McGraw-Hill, New York, NY, 1977, p 8-100. 11. P. Haswell, H. Choi, A. Dasgupta, Experimental and Analytical Durability Assessment of High-Temperature, Fatigue-Resistant Solders, Part I: Constituitive Properties, Transactions of Fourth High Temperature Electronics Conference, Albuquerque, Jun 1998, p 60. 12. C. Passow, B. Gingerich, G. Swenson, HT2000 High Temperature Gate Array, Transactions of Fourth High Temperature Electronics Conference, Albuquerque, Jun 1998, p 219.

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