Beruflich Dokumente
Kultur Dokumente
Knowledge Development
Knowledge Transfer
Knowledge Application
Major Results
The core can perform 35.000 cryptographic operations per second
50% Usage (On Xilinx XC4SX35) 1024 bit message 1024 bit modulo, 5 bit public exponent
@200 MHz 50.000 operations can be performed Compare with AMD Opteron 2.8 GHz: 26.000 Ops/s W 0 9 X A M Power consumption 1 W (Xilinx power estimator using simulated data). Theoretical MAX: 3.150.000 Ops/s (Altera Stratix IV E with 1360 16-bit multipliers).
Simulink
Fixed Point Blockset modelling (large) integers. Stateflow was used to implement the controller. hdlCoder Generating generic VHDL code Xilinx Sysgen for HIL
Development Issues
In cryptography all numbers are usually either bit fields or integers modulo n. Therefore use a toolbox like Fixed Point Toolbox to model these numbers. Model the algorithm in Matlab Model the algorithm in Simulink/Stateflow, and compare the results vs. the results from the Matlab model. Generate the code and run it.
a,b,p
n X
mod m
m h t i r a g o l s i e t m e r o l c T s u i L d D mo U C I F F DI
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For small numbers this can be done efficiently For large numbers this can become a bit difficult
*
t
*
m t
M *
m2
+
y1
/ y2
y1
y2
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Matlab Development
Matlabs built-in GCD is based upon floats (Double)
A GCD must be created which uses the FI-type.
A helper function which generates stimuli structures for simulink. The Montgomery Algorithm was developed to compare the results from this algorithm with the results from Simulink.
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HW in the LOOP
JTAG
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Perspectives
The title is Using Matlab to aid the implementation of a fast RSA Cryptocore The title should have been Using Matlab to do the implementation of a fast RSA Cryptocore
An advanced encryption algorithm can implemented using Matlab/Simulink. For commercial SSL offload engines certification is a must. The core can be implemented as an Off-the shelf service
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Conclusion
Correct use of Simulink with the hdlCoder results in a FAST and efficient core. Simulink runs faster than a comparable VHDL simulation
More tests can be performed during the same time. Using a faster model-based approach make programming more efficient.
The result is virtually generic. You do not need to spend time digging into subtile VHDL constructs. You must have knowledge of the mapping from Simulink Blocks into HDL blocks, and the result will also depend on your synthesis tool!
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Questions ?
http://www.teknologisk.dk Teknologisk Institut Denmark
Taastrup Aarhus Kolding, Herning, Odense, Hirtshals
http://www.teknologiskinstitut.se Teknologisk Institut AB, Formerly SIFU FIRMA 2000 Poland Swedcert AB carsten.siggaard@teknologisk.dk
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