VHDL Lab Manual Dated: 19/05/2011

FPGA DESIGN FLOW

Programmable Logic Design Flow
Design Specifications Design Entry Functional Simulation (Zero Delay) RTL Model TEST BE Gate level Model N C H Libraries (Simprims and Unisims) Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com Target Device Gate level Synthesis Libraries (Vender Specific) Simulation Design Constraints Area / Speed Target Device Libraries (Vender Specific) Design Constraints Area / Speed Gate level description using target library cells Timing Mapping + Simulation Translation (Gate + Gate level model to Interconnect device architecture Delays) Place and Route Placing the design in device while optimizing it for speed and area Programming file generation Bit Stream Download onto FPGA/ CPLD

FPGA Design Flow for Xilinx

The Design flow followed by Xilinx devices is as shown as under:

VHDL Lab Manual Dated: 19/05/2011 Xilinx FPGAs are reprogrammable and when combined with an HDL design flow can greatly reduce the design and verification cycle. Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011 Broadly the stages can be categorized as:

1. Design Entry may have two alternatives: a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor). b) Using Cores(Xilinx Core Generator). 2. Functional Simulation of synthesizable HDL code (MTI ModelSim). 3. Design Synthesis ( Xilinx project navigator). 4. Design Implementation (Xilinx Design Manager). The stages are linked as follows: VERILOG HDL/Verilog Code Design Entry Functional Simulation Synthesis Post Synthesis Simulation Implementation Timing Simulation Program onto FPGA

Design Entry
The first stage of Xilinx design flow is a design entry process. A design must be specified by using either a schematic editor or HDL text-based tool.

Functional Simulation
Upon the finish of the design entry stage, the functional simulation of the design is being performed, which is used to verify functionality of the design assuming no delays, whatsoever. This assumes no target technology selection at this stage and hence assumes zero delay in simulation. Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011

Complex designs must be intensively simulated, at different simulation points, during the design flow. Simulation verifies the operation of the design before it is actually implemented as hardware. One of the most prevalent methods for simulation is testbenching. Testbenches (VERILOG HDL) or text fixtures (Verilog) are used to specify circuit stimuli and responses. Roughly, simulation can be divided as functional and timing simulation. Primarily, the functional simulation verifies that the designs specifications are correctly understood and coded. Timing information, produced during the device implementation stage, is not available during the functional simulation. Functional simulation can be used after synthesis, too. Comparison between the pre- and post-synthesis simulations results checks the results of the HDL compilers work and the HDL codes correctness. Timing simulation operates with the real delays (results of device implementation) and is used for verification of implemented design. Timing data are given in an .sdf file (Standard Delay Format). Xilinx supports functional and timing simulations at different points of the design flow: Register Transfer Level (RTL) simulation. Post-synthesis functional simulation (PreNGDBuild). Post-implementation back-annotated timing simulation.

Design Synthesis
After this process, the synthesis is performed. Here for the first time in the design flow the target technology (choice of a particular FPGA device family) is being performed. This target technology selection will remain the same, henceforth in the design flow, upto the final implementation stage, where finally generated Bit stream file gets downloaded onto that FPGA. The output of the synthesis process is creation of gate level netlist. This refers to the EDIF implementation netlist of the FPGA design. Besides the EDIF implementation netlist, the XNF (Xilinx netlist format) netlist can be used as well. Although the XNF is now becoming rather obsolete. The EDIF netlist is used as an input file to the Xilinx Implementation tool and specifies how the core will be implemented. The Electronic Design Interchange Format (EDIF) is a format used to exchange design data between different CAD systems. In the world of FPGA design, it is used for interchange of data between different EDA (Electronic Design Automation) software tools. EDIF files are used for FPGA implementation only. They are the result of design synthesis and can be generated from different design entry EDA tools: schematic or HDL design tools. EDIF files are inputs to the Xilinx implementation tools during the translation step (NGDBuild).

Design Implementation
Design Implementation includes the following steps: i) Translate ii) Map iii) Place and Route Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011

In the Translate step, which is the first step in the implementation process, EDIF netlist must be further converted into Native Generic Database file (NGD), by means of a program called NGDBuild. The NGD file resulting from an NGDBuild run contains the logical description of the design that can be mapped into a targeted Xilinx FPGA device family. It is important to stress that NGDBuild merges all available EDIF netlists from the working directory. This is actually the step where the black-box netlist becomes merged with the rest of FPGA design. In the next stage, the Map stage, the NGD file is an input into a MAP program that maps logical design to a Xilinx FPGA. The output of the MAP program is an NCD (Native Circuit Description) file. The NCD is a physical representation of the design mapped to the components of internal FPGA architecture. The mapped design is ready to be placed and routed. The PAR program does this job. The input to PAR is a mapped (not routed) NCD file, while the output is a fully routed NCD file. Review reports are generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design: Process properties Constraints Source files Synthesis and again implementation of the design is being made until design requirements are met. Timing verification of the design can be made at different points in the design flow as follows: i) Run static timing analysis at the following points in the design flow: After Map. After Place and Route. ii) Running Timing Simulations at the following points in the design flow: After Map (for a partial timing analysis of CLB and IOB delays). After Place and Route (for full timing analysis of block and net delays).

Program onto FPGA

Programming on the Xilinx device can be made as follows: Creation of a programming file (BIT) to program FPGA. Generate a PROM, ACE, JTAG file for debugging or to download to the device. Use iMPACT to program the device through programming cable. Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with the configuration bitstream. The configuration bitstream is generated from the fully routed NCD file, by means of a BitGen program. The output of BitGen is a binary file with the .BIT extension that can be formatted for different PROM devices.

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011

EXPERIEMENT NO. 1

Simulation using all the modeling styles and Synthesis of all the logic gates using VHDL
AIM: Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then, Synthesize each one of them on two different EDA tools. Electronics Design Automation Tools used: i) FPGA Advantage 3.1 (includes Model Sim simulation tool and Leonardo Spectrum Synthesis Tool) ii) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to Implementation to download onto FPGA).

Block Diagram:
A

And, Nand, Or, Nor, Xor, Xnor B

Truth table:
And Gate: Or Gate: ABY000011101111 Nand Gate: Nor Gate: ABY001010100 Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com C ABY000010100111 ABY001011101110

VHDL Lab Manual Dated: 19/05/2011 110

Xor Gate: Xnor Gate: A B Y ABY000 001011 010101 100110 111

Boolean Equation:
And Gate: Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B) Nor Gate: Y = (A+B) Xor Gate: Y = A.B + A.B Xnor Gate: Y = A.B + A.B

VHDL Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling): library ieee; use ieee.std_logic_1164.all; entity andg is port (a,b : in std_logic; c : out std_logic ); end andg; architecture andg_df of andg is -- simple dataflow modeling begin c <= a and b; end andg_df; architecture andg_beh of andg is -- behavioral modeling using simple process begin process(a,b) begin c <= a and b; end process; end andg_beh;

Or gate(Dataflow, behavioral modeling):

library ieee; use ieee.std_logic_1164.all; entity org is port (a,b : in std_logic;

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011

c : out std_logic ); end org;

architecture org_df of org is -- dataflow modeling using when .... else begin c <= '0' when a = '0' and b = '0' else '1' when a = '0' and b = '1' else '1' when a = '1' and b = '0' else '1' when a = '1' and b = '1' else 'Z'; end org_df; architecture org_beh of org is -- behavioral modeling using if .... else begin process(a,b) begin if (a = '0' and b = '0') then c <= '0'; elsif (a = '0' and b = '1') then c <= '1'; elsif (a = '1' and b = '0') then c <= '1'; elsif (a = '1' and b = '1') then c <= '1'; end if; end process; end org_beh; Nand Gate (In Dataflow, behavioral Modeling): library ieee; use ieee.std_logic_1164.all; entity nandg is port (a,b : in std_logic; c : out std_logic ); end nandg; architecture nandg_df of Nandg is -- dataflow modeling using with ...... select signal sel : std_logic_vector(1 downto 0); begin sel <= a & b; with sel select c <= '1' when "00", '1' when "01", '1' when "10", '0' when "11", 'Z' when others; end nandg_df;

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011

architecture nandg_beh of nandg is -- behavioral modeling using case ... end case

begin process(a,b) variable v : std_logic_vector(1 downto 0); begin v := a & b; case v is when "00" => c <= '1'; when "01" => c <= '1'; when "10" => c <= '1'; when "11" => c <= '0'; when others => c <= 'Z'; end case; end process; end nandg_beh; Nor Gate (In Dataflow, behavioral Modeling): library ieee; use ieee.std_logic_1164.all; entity norg is port (a,b : in std_logic; c : out std_logic ); end norg; architecture norg_df of norg is -- dataflow modeling using with ...... select signal sel : std_logic_vector(1 downto 0); begin sel <= a & b; with sel select c <= '1' when "00", '0' when "01", '0' when "10", '0' when "11", 'Z' when others; end norg_df; architecture norg_beh of norg is -- behavioral modeling using case ... end case begin process(a,b) variable v : std_logic_vector(1 downto 0); begin v := a & b; case v is when "00" => c <= '1'; when "01" => c <= '0'; when "10" => c <= '0'; when "11" => c <= '0';

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

VHDL Lab Manual Dated: 19/05/2011

when others => c <= 'Z'; end case; end process; end norg_beh; Xor gate(Dataflow, behavioral modeling): library ieee; use ieee.std_logic_1164.all; entity xorg is port (a,b : in std_logic; c : out std_logic ); end xorg; architecture xorg_df of xorg is -- simple dataflow modeling begin c <= (a and (not b)) or ((not a) and b); end xorg_df; architecture xorg_df1 of xorg is -- dataflow modeling using when .... else begin c <= '0' when a = '0' and b = '0' else '1' when a = '0' and b = '1' else '1' when a = '1' and b = '0' else '1' when a = '1' and b = '1' else 'Z'; end xorg_df1; architecture xorg_beh of xorg is -- behavioral modeling using if .... else begin process (a,b) begin if (a = '0' and b = '0') then c <= '0'; elsif (a = '0' and b = '1') then c <= '1'; elsif (a = '1' and b = '0') then c <= '1'; elsif (a = '1' and b = '1') then c <= '0'; end if; end process; end xorg_beh; Xnor Gate (In Dataflow, behavioral Modeling): library ieee; use ieee.std_logic_1164.all; entity Xnorg is

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com