Internal Data Bus of a Small Student Satellite

Marius Lind Volstad

Master of Science in Electronics

Submission date: June 2011 Supervisor: Bjrn B. Larsen, IET

Norwegian University of Science and Technology Department of Electronics and Telecommunications

Problem description
In modern satellites, containing many separate digital systems, it is essential for the functionality of the satellite to allow for reliable and power ecient communication between all systems. The most eective way of ensuring system-to-system communication is through a common data bus. The internal data bus will be the backbone of the satellite and has to remain operable through the lifespan of the satellite. It is also benecial for the integrity of the satellite to have an On-Board Controller (OBC) to log useful data and monitor the digital systems. The student shall design a reliable data bus and OBC for use in the NTNU Test Satellite (NUTS) project.

Assignment Given: 24.01.2011 Supervisor: Bjrn B. Larsen Co-supervisor: Roger Birkeland

ii

Abstract
This thesis presents a platform for a small student satellite. A backplane solution with slots for 8 individual modules is proposed. The backplane provides the modules with power and a common data bus, as well as mechanisms for isolating modules from the rest of the system and a possibility of restoring misbehaving modules. It has a power consumption of about 100mW. An on-board controller has been designed and tested. It consists of a 32-bit MCU, a NAND ash memory for housekeeping logs, an SRAM memory for processing variables, an OTP memory for safe storage of module rmwares, USB interface and a wireless intra-satellite communication module. The on-board controller has the main responsibility for monitoring and preserving the satellites health. The power consumption will be dependent of the nal rmware, but a rough estimate is about 100mW. Also, an experimental wireless intra-satellite communication system is proposed. The system consists of a small wireless module, that will be integrated onto any module that is a part of the wireless network.

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Preface
My rst thought when joining the NUTS project, was that it would be extremely satisfying building something that is destined to be launched into space. But I felt a bit confused after the rst introductory speeches of what building a satellite was all about. There were a lot of new concepts and methodologies to become familiar with. After some time immersing myself in space and satellite related material, I again began to feel the excitement of being a part of a team of satellite builders. The work with the backplane has been a joint eort by Dewald de Bruyn and myself. Dewald has had main responsibility for the power solution and done most of the hardware layout drawings, while I have made the digital systems. We have had many discussions about the system, and feel that we have ended up with a solid design. It has been incredibly educational to work with the NUTS project. I have met many challenges and felt a lot of joy in overcoming the obstacles. Also, I have had the pleasure of being a part of a very competent team. And now, Im looking forward to coming back to NTNU for the launch of NTNUs rst successful satellite mission!

Marius Lind Volstad

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Acknowledgement
I would like to thank my supervisors Bjrn B. Larsen and Roger Birkeland for guidance on this thesis, and thanks to Dewald de Bruyn for cooperation during the backplane development. Thanks to Torbjrn Finny, Daniel Aasb, Kjetil Kval and Carolina Fiorella Inche Velezmoro for overall help with this thesis and great company at the oce. A double thanks to Daniel Aasb for corrective reading of the thesis.

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Contents
Abstract Preface Acknowledgement Contents Acronyms List of Figures List of Tables 1 Introduction 1.1 Internal Communication . . . . . . . . . . . . . . . . . . . . . 1.2 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 On-Board Controller . . . . . . . . . . . . . . . . . . . . . . . 2 Background Information and Theory 2.1 The Space Environment . . . . . . . . . . 2.1.1 Space Radiation . . . . . . . . . . . 2.1.2 Vacuum Conciderations . . . . . . 2.1.3 Space Debris . . . . . . . . . . . . 2.2 Memory . . . . . . . . . . . . . . . . . . . 2.2.1 NAND Flash . . . . . . . . . . . . 2.2.2 Static Random Access Memory . . 2.2.3 One-Time-Programmable Memory . iii v vii ix xiii xv xvii 1 2 2 2 3 3 3 8 8 9 9 10 10 ix

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Contents 2.3 2.4 2.5 Digital Logic Series . . . . . . . . . . . . . . . . . . . . . . . . 11 AT32UC3A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 nRF24LE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 16 16 19 20 24 25 25 25 29 31 31 32 32 33 34 34 34 35 35 36 36 36 37 37 38 41 42 43 43 46 47

3 Backplane 3.1 Design . . . . . . . . . . . . . . . 3.1.1 Data Bus . . . . . . . . . 3.1.2 Power System . . . . . . . 3.1.3 Digital Control . . . . . . 3.1.4 Mechanical Considerations 3.1.5 System Overview . . . . . 3.2 Prototyping . . . . . . . . . . . . 3.2.1 Testing . . . . . . . . . . . 3.2.2 Results . . . . . . . . . . . 4 On-Board Controller 4.1 Hardware Design . . . . . . 4.1.1 Microcontroller . . . 4.1.2 Memory Hierarchy . 4.1.3 Backplane Connector 4.1.4 USB Interface . . . . 4.1.5 Manual Override . . 4.1.6 Hardware Overview . 4.2 Software Design . . . . . . . 4.2.1 Drivers . . . . . . . . 4.2.2 Housekeeping . . . . 4.2.3 Operating System . . 4.2.4 Support Software . . 4.3 Prototyping . . . . . . . . . 4.3.1 Testing . . . . . . . . 4.3.2 Results . . . . . . . .

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5 Internal Wireless Communication 5.1 Hardware Design . . . . . . . . . 5.2 Firmware Design . . . . . . . . . 5.2.1 Protocol . . . . . . . . . . 5.3 Prototyping . . . . . . . . . . . . 5.3.1 Testing . . . . . . . . . . . x

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Contents 5.3.2 6 Discussion 7 Concluding Remarks 8 Future Work 8.1 Wireless link . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 OBC Completion . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Radiation Detector . . . . . . . . . . . . . . . . . . . . . . . . Bibliography A Backplane B On-Board Controller C Wireless Internal Communication Module Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 49 53 55 55 55 55 57 59 71 75

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Acronyms
ADC CAN CD CMOS Analog-to-Digital Converter. Controller Area Network. Compact Disc. Complementary Metal-Oxide-Semiconductor.

DMIPS Dhrystone Million Instructions Per Second (MIPS). DSP ECC GPIO GUI I2C IC LEO MCU MeV Digital Signal Processing. Error Correcting Code. General Purpose Input/Output. Graphical User Interface. Inter-Integrated Circuit. Integrated Circuit. Low Earth Orbit. Microcontroller Unit. Megaelectronvolt.

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Acronyms

MIPS MOS NUTS OBC OTP PCB RAM SCL SDA SEE SEU SOI SPI SRAM TID UART

Million Instructions Per Second. Metal Oxide Semiconductor. NTNU Test Satellite. On-Board Controller. One-Time Programmable. Printed Circuit Board. Random Access Memory. Serial Clock Line. Serial Data Line. Single Event Eect. Single Event Upset. Silicon-On-Insulator. Serial Peripheral Interface. Static RAM. Total Ionizing Dose. Universal Asynchronous Receiver/Transmitter.

USB

Universal Serial Bus.

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List of Figures
2.1 2.2 2.3 2.4 2.5 2.6 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 4.1 Illustration of the Van Allen belts. Courtesy of NASA. . . . A standard CMOS inverter with parasitic transistors. Courtesy of Aerospace Corporation. . . . . . . . . . . . . . . . . . A majority voting system, processor 2 is defective. . . . . . . A majority voting system with time delay. . . . . . . . . . . The oating gate transistor. . . . . . . . . . . . . . . . . . . An SRAM memory cell. . . . . . . . . . . . . . . . . . . . . The centralized system solution. . . . . . . . . . . . . . . . . The distributed system solution. . . . . . . . . . . . . . . . . An illustration of a backplane solution, from the NUTS-1 Mission Statement. . . . . . . . . . . . . . . . . . . . . . . . . . The proposed bus topology. . . . . . . . . . . . . . . . . . . The satellite power system. . . . . . . . . . . . . . . . . . . . The address matching circuit for the module controls. . . . . Power and data bus access control. . . . . . . . . . . . . . . Control waveform for power and data bus access ip-ops. . The backplane reset circuitry. . . . . . . . . . . . . . . . . . The backplane reprogramming circuitry. . . . . . . . . . . . The module to backplane connector. . . . . . . . . . . . . . An overview of the backplane, excluding control logic. . . . . Pinouts for master slots (left), payload slots (middle) and power slot (right). . . . . . . . . . . . . . . . . . . . . . . . . The circuit board for the backplane. . . . . . . . . . . . . . . The nished backplane with On-Board Controller (OBC) module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

. 5 . 7 . 7 . 9 . 10 . 14 . 14 . . . . . . . . . . 15 18 19 20 21 22 22 23 24 26

. 27 . 27 . 28

A system overview of the OBC. . . . . . . . . . . . . . . . . . 34 xv

List of Figures 4.2 4.3 5.1 5.2 5.3 The circuit board for the OBC. . . . . . . . . . . . . . . . . . 37 The nished OBC. . . . . . . . . . . . . . . . . . . . . . . . . 38 An overview of the wireless transceiver module. . . The wireless module circuit board. Top view on the bottom view on the right. . . . . . . . . . . . . . . The wireless module. . . . . . . . . . . . . . . . . . schematic, schematic, schematic, schematic, schematic, schematic, schematic, schematic, schematic, schematic, schematic, page page page page page page page page page page page 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 left, and . . . . . . 46 . . . . . . 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 61 62 63 64 65 66 67 68 69 70

A.1 Backplane A.2 Backplane A.3 Backplane A.4 Backplane A.5 Backplane A.6 Backplane A.7 Backplane A.8 Backplane A.9 Backplane A.10 Backplane A.11 Backplane

B.1 On-Board Controller schematic, page 1. . . . . . . . . . . . . . 72 B.2 On-Board Controller schematic, page 2. . . . . . . . . . . . . . 73 C.1 Intra-satellite Communication Module schematic. . . . . . . . 76

xvi

List of Tables
2.1 3.1 3.2 5.1 5.2 5.3 Estimated amount of space debris. Source: American Institute of Physics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Selected data bus characteristics based on common specications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Testing specication of the backplane. . . . . . . . . . . . . . 28 Example address table for wireless transmission. . . . . . . . . 44 A transmission from Module A to Module B. . . . . . . . . . . 45 Dividing the channel controls in time for each link. . . . . . . 45

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Chapter 1 Introduction
This thesis is one of many concerning the student satellite program at NTNU, called NTNU Test Satellite (NUTS). A document outlining the mission objectives for NUTS is attached on the accompanying Compact Disc (CD). A short summary of the mission objectives is given below: The NUTS (NTNU Test Satellite) project was started in September 2010. The project is part of the Norwegian student satellite program run by NAROM (Norwegian Centre for Space-related Education). The projects goal is to design, manufacture and launch a double CubeSat by 2014. The national student satellite program involves three educational establishments, namely the University of Oslo (UiO), Narvik University College (HiN) and NTNU. As main payload, the NUTS project will y an IR-camera for atmospheric observations. In addition, a concept for a wireless short range data bus connecting dierent subsystems will be added. For communication, the satellite will use the common amateur radio bands and y one transceiver for each frequency. During the rst half of 2011, ten students from dierent departments and curriculums were involved in the project. It has previously been done research on building a student satellite at NTNU. This research stems from both previous projects, and a precursory 1

Chapter 1. Introduction study for the NUTS project. Some previous experiences have been incorporated into the research. The NUTS will be orbiting Earth way out of reach for us to do any physical maintenance after launch. It is also too far out to be protected from solar radiation by our planets atmosphere. Because of this, it is extremely important that the satellite is designed to be self-reliant and robust. There are many aspects to consider to design such a system. This thesis focuses on three main points; the internal communication, providing a systems platform for maximum lifespan and an OBC.

1.1

Internal Communication

The internal communication of the satellite will consist of a regular wired bus for main internal communication, and an experimental wireless bus. Wireless intra-satellite communication has not yet been widely tested, and one of the mission objectives is therefore to test if this is a viable replacement.

1.2

Backplane

The basic platform of the satellite is refered to as the backplane. It will consist of all the necessary circuitry for providing power and communications to the payloads, and also for isolating and restoring misbehaving sub-systems. In short terms; it is the connection hub for all sub-systems.

1.3

On-Board Controller

An OBC is responsible for much of the housekeeping of the satellite. It has the main responsibility for monitoring the health of the system, and to take any necessary actions. It should keep a log of all events and vital mission data, and be able to oer processing capabilities for other systems. The accompanying CD contains developed code, as well as source les for schematics and layout. 2

Chapter 2 Background Information and Theory

This chapter will present various theory and concepts useful for understanding the rest of this thesis. Some electronic devices used are also presented.

2.1

The Space Environment

The environment in space is very dierent from the normal operating conditions of electronic devices. This section will outline these dierences, and reect on the diculties they pose.

2.1.1

Space Radiation

Space radiation is one of the biggest concerns when dealing with satellites in orbit. It consists of high energy particles radiated from several sources in space. [1] These particles comes from cosmic rays, as well as our own sun. Cosmic rays mainly consists of the nuclei of a variety of atoms, but also includes subatomic particles such as positrons and electrons.[2] Other stars, novas, supernovas and other objects are responsible for the cosmic rays. The radiation from the sun mostly stems from the fusion processes in the core, which results in a solar wind of electrons and protons. The strength of the 3

Chapter 2. Background Information and Theory

Figure 2.1: Illustration of the Van Allen belts. Courtesy of NASA. solar radiation will vary with the sunspot activity, and will peak during solar ares. When the radiation reaches Earth, it will be aected by Earths electromagnetic eld. This will cause some of the radiation to accumulate in the upper atmosphere in what is called the Van Allen Radiations belts. There are two belts, the inner and the outer belt. The inner belt mostly consist of protons with energy above 3 Megaelectronvolt (MeV). The outer belt contains less energetic protons, but has electrons that can have energies of several hundred MeV. [3] The inner Van Allen belt has its centre at approximately 2,000 km above the surface of the Earth. However, measurements have shown that the belt is descending closer to the poles, and that the radiation can have considerable concentrations at lower altitudes. An illustration of the Van Allen belts are shown in gure 2.1. Eects of Radiation on Electronic Components The bombardment of highly energetic space radiation can cause some troubling eects on electronic components. The total radiation dose will lead to a constant degradation of the components, and will eventually cause the device to fail. In addition, the radiation can cause spontaneous Single Event Eects (SEEs). Radiation in the form of protons or heavy ions will release energy by ionization when it penetrates the components. The ionization will give a charge at the node, and lead to a short current pulse. 4

2.1. The Space Environment

Figure 2.2: A standard CMOS inverter with parasitic transistors. Courtesy of Aerospace Corporation. Latch-up is a state found in Complementary Metal-Oxide-Semiconductor (CMOS) devices where a high current moves from the components source voltage to ground. In this state, the component will not respond properly to input stimuli. [4] Normal operation can be restored by removing and reapplying power, but heat dissiapation from the current ow might have destroyed the component. The problem can be understood by considering the standard CMOS logic inverter seen in gure 2.2. The die has a PNPN-structure which results in the equivalent circuit of two connected transistors. When high energy radiation penetrates into this structure and releases some of its energy as a current spike, it can activate one of the transistors. The current consumption will increase due to positive feedback in the circuit, and ultimately become a short-circuit. [5] A Single Event Upset (SEU) is a less devastating eect, but can still cause mayhem on the circuits operation. Consider a storage element such as a ip-op, NAND ash or SRAM cell. A heavy ion can penetrate into the structure and leave a charge that ips one or more bits. The consequence 5

Chapter 2. Background Information and Theory of this SEE will depend on the applications interpretation of the specic bits, but could possibly be mission-threatening if it aects e.g. navigation or power controls. Total Ionizing Dose (TID) refers to the amount of ionizing radiation a component has accummulated over time. The ionizing radiation leads to a change in the physical parameters of the devices. More specically it will result in a shift of the threshold voltage of Metal Oxide Semiconductor (MOS) transistors. [6] This could lead to a higher leakage current, and eventual failure of the electronic components. Improving Radiation Tolerance Physically shielding by encapsulating the sensitive components in a radiation absorbing or reecting material is possible. Depending on the material characteristics and thickness it will reduce the amount of radiation reaching the components. However, the shielding will not be able to stop all the radiation, and especially not the most energetic particles that causes SEEs. Fabrication processes exists that can be used to counteract latch-up. Latch-up is dependent on the existence of the PNPN-structure. For the most common CMOS fabrication process this structure will be present on numerous places. Luckily, there are design methods and alternate fabrication processes to counter the PNPN-structure. [7] One design method is to disrupt the current ow path by placing an n-well contact to the power supply for each pFET connected to the power supply. [4] An example for latch-up tolerant processes is the Silicon-On-Insulator (SOI) process. SOI builds its transistors on an insulator instead of a silicon substrate. This wont lead to the formation of the PNPN-structure. Redundancy is a way of increasing the reliability of a system by duplicating sub-systems or information. This is especially important in space applications, where the equipment is constantly subject to a bombardment of radiation, which results in SEUs and degradation. However, redundancy will add some extra space and complexity to both hardware and software. Error Correcting Codes (ECCs) will assure data integrity by adding redundant bits to a bulk of data. [8] These bits are calculated using special algorithms to allow for detection and even correction of bit errors. There are 6

2.1. The Space Environment

Processor 1 0xAA Output: 0xAA Majority Voter 0xA9 0xAA Processor 3 Processor 2 Input: 0x55

Figure 2.3: A majority voting system, processor 2 is defective.

2us 0xA4 Output: 0xAA Majority Voter 0xAA 0xAA 1us

Processor 1

Processor 2

1us

Input: 0x55

Processor 3

2us

Figure 2.4: A majority voting system with time delay. a number of dierent algorithms such as Hamming codes and Reed Solomon codes, which vary in calculation complexity and storage eciency (i.e. how many bits are redundant). Some Microcontroller Units (MCUs) have integrated generators for some codes, which will heavily increase the throughput. Majority voting is useful when adding redundant duplicated pieces of hardware for processing. It is used to decide which result is the correct one, and which sub-systems have been damaged and produces the faulty response. This can be done by majority voting where the result from all the redundant systems are compared, and the most common answer will be assumed to be correct. Figure 2.3 shows a system using majority voting. The majority voting system can be improved by recognizing that some faults can stem from SEUs from space radiation. Then it is likely that many of the redundant systems are aected at the same time by a burst of radiation, e.g. from a solar storm. By adding dierent time delays for each system the calculations would take place at a dierent point in time, and decrease the possibility of a radiation burst changing the majority vote result. Figure 2.4 7

Chapter 2. Background Information and Theory shows the majority voting system with time delay implemented.

2.1.2

Vacuum Conciderations

The concentration of particles of the atmosphere in Low Earth Orbit (LEO) is signicantly smaller than on the surface of Earth. Since the atmosphere excert a pressure depending on the concentration of particles, the pressure is much higher on the surface. [9] Certain conciderations must be taken in order for the pressure dierence of the design environment, the surface of Earth, and the ight environment, LEO, to not have a damaging eect. If bubbles of gas and liquid have been trapped in any component package or a Printed Circuit Board (PCB), it could lead to the pressure damaging the material and possibly the whole component or PCB. Such bubbles can occur on a PCB during manufacturing if a via hole is buried between copper layers or solder mask. And even during soldering pockets of gas or liquids can be trapped in the solder. The components can also contain pockets from the packaging process. A danger also arises if any of these gases or liquids are acidic, which could result in damage to the whole satellite or even other satellites in the same rocket.

2.1.3

Space Debris

Space debris is an ever increasing concern for satellites and space vehicles. A vast number of old satellites, fragments of satellites, old rockets and similar is oating around Earth at dierent altitudes. [10] The debris count for various sizes are shown in table 2.1. In LEO, objects orbit at speeds above 7 km/s, which means that even small fragments can hold as much energy as a moving Table 2.1: Estimated amount of space debris. Source: American Institute of Physics. 0.1-1 cm Total debris at all altitudes Debris in low-Earth orbit 8 150 million 16 million 1-10 cm > 10 cm 650 000 270 000 22 000 14 000

2.2. Memory

Control gate Floating gate n+ Source Drain n+

Figure 2.5: The oating gate transistor. car on the freeway. All fragments between 1 mm and 1 cm are considered to pose a threat to satellites, while any fragment above 1 cm would denitely destroy it. The only way to improve space debris resilience would be to shield the satellite with durable materials. This would make the satellite too heavy to t into the CubeSat standards. Luckily, there is a vast amount of space and the chance of a collision is small, even though the possibility of a collision is real.

2.2

Memory

Memory devices are an indispensable part of all advanced systems, and are present in some form. This section will give a brief introduction to some types used in this thesis.

2.2.1

NAND Flash

NAND Flash storage devices are based on a oating gate MOS transistor. [11] A oating gate transistor can be thought of as a regular MOS transistor with an extra control gate on top of the normal gate, as illustrated in gure 2.5. A charge can be built up on the oating gate, which will hold the transistor in its on or o state. The state of the transistor decides if a one or a zero is stored in the cell. The process of depositing charge on the oating gate varies among technologies and manufacturers. But one way of programming is to ground the P-substrate and N-well, and then applying voltage to the 9

Chapter 2. Background Information and Theory

WL nBit Bit

Figure 2.6: An SRAM memory cell. control gate. This will create an electric eld that pulls electrons onto the oating gate, making it negatively charged. The oating gate is charged positively by applying ground to the control gate and voltage to the source of the transistor.

2.2.2

Static Random Access Memory

A Static RAM (SRAM) memory cell is based on two connected transistor inverters, as shown in gure 2.6. [12] The inverters will keep the gate voltage of each other to retain the bit information. Reading is performed by activating the control transistors, which connects the inverters to the bit lines. Write is performed in the same way, but by applying the new bit on the bit line and thereby charging or discharging the gate.

2.2.3

One-Time-Programmable Memory

The One-Time Programmable (OTP) memory is a non-volatile memory that can only be programmed once. It is built up by an array of fuses that is permanently broken during programming. [13] There are many dierent congurations of OTP memory, but the basic principles are the same. Programming is performed by imposing a large enough current or voltage to damage the dielectric material. [14] Address lines are available to address 10

2.3. Digital Logic Series specic parts of the memory. Information is then stored by addressing the correct part and programming the fuses that should be programmed. Since information is stored by structurally altering the component, it is considered to be more reliable than other memories in harsh radiation environments. In fact, certain technologies of OTP memories has proven to be specically radiation tolerant. The resistance of a programmed OTP antifuse memory cell based on amorphous silicon is not aected by radiation, and the resistance of an unprogrammed cell will increase under radiation, i.e. improve. [15]

2.3

Digital Logic Series

Using digital logic is not as simple as just selecting the logic expression you want to realize and putting it together using the available Integrated Circuits (ICs). There are several key parameters to take into concideration, such as voltage levels, power consumption, speed and other internal aspects of the logic circuitry. For example a logic device that supports partial power down will not be partially powered through an I/O pin when its power supply has been shut o. There are dozens of dierent families and technologies of digital logic to explore. [16]

2.4

AT32UC3A3

The AT32UC3A3 is a range of MCU devices built around the AVR32 core from Atmel. [17] It oers 32 bit processing at up to 92 Dhrystone MIPS (DMIPS), and a Digital Signal Processing (DSP) instruction set. It can handle many memory interfaces automatically, and supports multiple dierent memory devices connected to a common bus at the same time. The memory interface can be used together with an ECC generator to add redundancy. A Universal Serial Bus (USB) interface is available for connectivity to a computer. 11

Chapter 2. Background Information and Theory

2.5

nRF24LE1

The nRF24LE1 is a combination of a 2.4GHz radio transceiver and an 8051 MCU from Nordic. [18] It can transfer data at a maximum rate of 2Mbps, but can be lowered to acheive a better transmission reliability. The MCU oers several modules such as communication, encryption and Analog-toDigital Converter (ADC). An external crystal can be connected to provide a low-power synchronization clock. Both the radio and the MCU has been optimized to be power ecient. An OTP edition of nRF24LE1 is available. This version provides an OTP memory instead of the normal ash for rmware storage. In addition, some OTP memory is also available for storing data.

12

Chapter 3 Backplane
A system as complicated as a satellite will always be divided into several sub-systems. The designers working on those sub-systems will focus on completing their specic task. But eventually all the sepearate sub-systems has to be sown together into the completed satellite. So the question is; how will everything be tied together? There are ultimately two main topologies for connecting the sub-systems together. A centralized approach, as shown in gure 3.1, will consist of a main computer functioning as the connection point between all sub-systems. The distributed system, shown in gure 3.2, consists of a common connection link shared by all sub-systems. Previous research on the subject has favored the distributed system because of reusability and scalability. [19] Scalability is important because the designer of the data bus-system does not necessarily know in what way the data bus will be used. The use of a distributed system makes it much easier to dene a common connector and pin-out for all sub-systems in the satellite. This introduces the thought of a backplane. A backplane is a board with several connectors that interfaces the sub-systems together. An illustration of the general thought of the backplane is shown in gure 3.3. The dierent sub-systems are then built as separate modules that ts directly onto the backplane connector. This solution makes it easy for designers to insert and remove single cards without having to dismantle the whole satellite every time a change must be made. 13

Chapter 3. Backplane

Payload

Payload

Payload

Payload

Main MCU

Payload

Payload

Payload

Payload

Figure 3.1: The centralized system solution.

Main MCU
Payload Payload Payload Payload

Payload

Payload

Payload

Payload

Figure 3.2: The distributed system solution.

14

Figure 3.3: An illustration of a backplane solution, from the NUTS-1 Mission Statement.

15

Chapter 3. Backplane The backplane will have slots for 8 modules. Two of them will be reserved as extended functionality master module slots, one for a special purpose power module and the remaining ve as regular payload slots. The two masters will be responsible for controlling most of the digital systems on the backplane, and do general housekeeping in the satellite. Both masters will have equal access to do everything, as a redundancy. But there are still many considerations to be made. What if a module starts misbehaving and oods the data bus? Due to space radiation this is likely to occur eventually during the satellites lifespan. There should be some mechanisms for detecting the misbehaving module, isolating it and hopefully correcting the error. This makes it necessary to add control logic to the backplane. The following section (3.1) presents a viable design solution.

3.1
3.1.1

Design
Data Bus

The data bus will be the main communication channel between all modules. It needs to be scalable and robust, provide a relatively high throughput rate and preferably have a low power consumption. In addition, it should be easy to use for the modules, and the best way to assure this is to select a commonly available standard for the data bus. There are many dierent standards available, both for serial and parallell communication. Parallell busses will require a much larger connector than the serial busses, therefore a serial interface is to prefer. Many MCUs have integrated logic to automatically handle a range of communication protocols. Among the serial interfaces, the most found includes Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART) and Controller Area Network (CAN). The most important characteristics of each bus is summarized in table 3.1. 16

3.1. Design Table 3.1: Selected data bus characteristics based on common specications. Data Bus SPI I2C CAN UART Speed 20Mbps 400kbps 1Mbps 1Mbps Lines 4 2 2 2 Notes One chip select for each device. Limited address and bus capacity. Needs external circuitry. Noise resilient. Dicult to use between multiple nodes.

The most important aspects for the backplane is that the data bus should be equally available for all and be as simple as possible. This excludes SPI because it requires a master device to control the chip select signal, or some sort of complex logic to control the arbitration process. UART will also require som complex logic for arbitration since it is made for communication between just two modules. The CAN bus would have been a good choice because of its noise resilience, but most MCUs do not have integrated support. It would therefore be necessary to add some extra circuitry, and increase the overall design complexity.

I2C The I2C bus was selected as a common data bus. It is a very common data bus with integrated support in most MCUs, and many sensor chips uses this interface. The bus only requires two lines for communication; Serial Data Line (SDA) and Serial Clock Line (SCL). [20] The lines are controlled by open-collector logic, and pulled up to logic 1 by resistors in the idle state. This makes it possible to have multiple masters on the same bus, and implement collision detection and arbitration in software if there isnt already supported in hardware. All devices are connected to these common lines, and addressed by a unique address for each device. The address space is limited to 7 bits giving 128 possible addresses, but a 10 bit addressing mode can be used if necessary. Some of the addresses are reserved for specic purposes, so the true number of available addresses is smaller depending on what devices are used. There will anyways be enough addresses for many modules and sensors connected to the bus. If more devices are needed there exists an abundance of I2C 17

Chapter 3. Backplane

I2C Bus Module 1 I2C Rep. I2C Rep. Module 5

Module 2

I2C Rep.

I2C Rep.

Module 6

Module 3

I2C Rep.

I2C Rep.

Module 7

Module 4

I2C Rep.

I2C Rep.

Module 8

Figure 3.4: The proposed bus topology. switches, multiplexers and hubs that can be used to create sub-domains of the I2C address space. The total bus capacitance of the I2C bus will limit both the number of devices that can be connected to the bus and the total length of the bus. This can be solved by using I2C repeaters that replicates the bus conditions on both sides, acting like a buer. These repeaters also have an enable/disable pin for connecting or disconnecting the two sides of the repeater, making them ideal for isolating malfunctioning devices from the bus.

Bus Topology The bus has to be distributed in a reasonable way between all of the modules. The selected topology is presented in gure 3.4. The backplane contains a common I2C bus connected to an array of bus repeaters. Each of those bus repeaters are connected to a separate module slot, and one for a separate I2C bus on the backplane. The bus repeaters (PCA9517) has an active-high enable pin that can be used to isolate the module side of the bus from the backplane side. This bus topology makes it easy to isolate a separate module through the control logic. 18

3.1. Design

SUN Solar panel Solar panel Power Module Solar panel Solar panel 3v3 Current lim. Current lim. Current lim. a b a b 5v Batt. Batt. Batt. Batt.

3v3 to module

Meas.

Same circuitry for 5v, as for 3v3.

3v3 to module

Meas.

3v3 to module Meas. I2C

Figure 3.5: The satellite power system.

3.1.2

Power System

The power system, as illustrated in gure 3.5, consists of a set of solar panels, a power module, battery packs and a power distribution system. The power module has its own special slot on the backplane because it is suppose provide the backplane with power, and not draw power as the other modules. It provides two regulated power levels of 3.3V and 5V, and two separately regulated lines of each for redundancy. On the backplane the redundant power lines are merged into one source for each of the modules. The merging is done through a special circuit that acts as an ideal diode, only leading one way. Following the ideal diodes is a current limiting circuit. It will cut the power whenever the module tries to draw too much current from either of the sources. There is also a circuit for reading the current consumption through the I2C bus. It will also be possible to shut the power o for the separate modules. This is handled by the current limiting circuit which has an enable pin for the power. The current state can even be monitored by the master modules as a power ag, and proper steps taken to correct the behavior. All of this functionality will be handled by the digital logic on the backplane. 19

Chapter 3. Backplane

Board ID0

Addr0

Board ID1 nSelect Addr1

Board ID2

Addr2

Figure 3.6: The address matching circuit for the module controls.

3.1.3

Digital Control

The digital control will handle shutting on and o power and data bus access for each module. In addition it will handle the reset signals and reprogrammability option for each of the modules. But if all the necessary signals were dedicated for each module, the master connectors would need way too many pins. It is therefore necessary to use a common control bus for all the modules, and add some kind of addressing to select the module. A more detailed explanation of the parts of the digital control system follows below.

Address Matching Each of the modules will have their own address. When addressed, the modules select signal will go active. The simplest solution for doing this would be to have 8 select lines from the masters. This is still too many lines. A better solution is to use a 3-to-8 decoder circuit. The master modules can then use 3 lines to address each of the 8 modules. But the 3-to-8 decoder would have been a single point of failure, that could potentionally crippled the whole system. The solution was to break the 3-to-8 decoder into individual address 20

3.1. Design

nBus nSet BP Reset

D nClr Clk

Q nQ I2C enable

nSelect

nPwr

D nClr Clk

Q nQ Power On

Figure 3.7: Power and data bus access control. matching circuits, as shown in gure 3.6. The XOR-ports compares the value of each address bit and gives a low signal when it is a match. The OR-port will then check for a mismatch by propagating any high signals. This makes the select signal active-low. The address for each module is hardwired onto the module itself. This makes it possible to address the specic module and not just the slot on the backplane. The modules can then be swapped without reprogramming the masters.

Data Bus and Power Control The data bus access and power switch is simply controlled by enable pins. These two pins could have been controlled directly from the master modules, but because of the pin count a better solution had to be found. A D-type ip-op is used for each signal to store the state, as shown in gure 3.7. The control bus for these ip-ops consists of a bus enable, power enable and clock signal. These signals are used together with the select signal to control the state of the ip-op outputs. Figure 3.8 shows the correct waveforms for setting the states. 21

Chapter 3. Backplane

Select module Release module nSelect

nSet

Toggle nSet to set

nBus Release nPwr nPwr Turn power on, and bus off

Figure 3.8: Control waveform for power and data bus access ip-ops.

nSelect Module Reset

System Reset 1 System Reset 2

nReset

Figure 3.9: The backplane reset circuitry. Reset System When a module starts misbehaving it would be benecial to be able to do a reset of the aected systems. This could be done by powering the module on and o, or by pulling on the reset line of all the digital circuits on the module. The reset circuitry is shown in gure 3.9. There are three separate reset lines on the backplane. The module reset is used to reset the individual module being addressed at the moment. The two system reset signals are used to reset all of the modules and the backplane as well. There is one system reset per master, so that the master does not reset itself when it pulls on the system reset line. In the case of a lockup of both masters the backplane includes a watchdog timer. A lockup could occur if power for both masters have been shut down. 22

3.1. Design

Prog1 From masters Prog2 Prog3 nSelect Pwr-state Prog4 En

Module prog1 Module prog2 Module prog3 Module prog 4

Figure 3.10: The backplane reprogramming circuitry. Then there wont be any controlling modules on the backplane, and the power cant be turned back on. The watchdog timer will then trigger and reset the power and bus ip-ops and reset the entire system. To prevent the watchdog timer from triggering one of the masters must toggle the rst addressing pin.

Reprogramming Modules In a harsh radiation such as space, memory cells will suer from degradation and bit ips. If a rmware ash on an MCU is aected it could possibly render the device useless. The only way to recover the device would then be to reprogram the device. Most devices uses an interface, e.g. JTAG, ISP, TPI etc., with 4 lines or less to program the device. Therefore four signals are routed from the masters to each module slot as a programming port. The programming port is as default disconnected, and is connected whenever a module is selected. The circuitry for handling this is shown in gure 3.10. There doesnt have to be made any decisions regarding the actual programming protocols to be used. It will just be a matter of implementing the various necessary protocols on the master modules later. Then the master will know which protocol to use depending on which address is going to be reprogrammed. 23

Chapter 3. Backplane

Figure 3.11: The module to backplane connector.

3.1.4

Mechanical Considerations

The satellite needs to be a mechanically reliable system. During launch the satellite must endure immense accelerations and vibrations. This means that there are special concerns to be handled regarding the connectors used for each of the modules, and also for how the backplane itself is secured in the satellite. It is even important to concider component packaging and placement to build a mechanical stable system. The connector for the modules should be capable of providing the module with mechanical support in the satellite. It will act as an anchor point, and support the module together with the satellites frame. The selected connector is a regular 2.54mm pitch two row connector, as shown in gure 3.11. It should provide sucient support and be mechanical robust. The circuit board of the backplane itself is shaped to be able to secure to the frame of the satellite. It is meant to t into slots in the frame, and be secured by screws in the corner. The shape of the circuit board can be seen in gure 3.14. 24

3.2. Prototyping

3.1.5

System Overview

An overall overview of the backplane system is shown in gure 3.12. It consists of six 12x2 pin 2.54mm connectors, for regular payload and power, and two 18x2 pin 2.54mm connectors for the master modules. It is proposed that the master modules are the radio module and the OBC. The masters have the ability to control access to the common I2C bus, toggle power for each module, reprogram modules and reset specic modules. The connector pinouts for both the master modules, power module and payload modules are shown in gure 3.13.

3.2

Prototyping

The proposed solution has been realized and tested. The schematics are presented in appendix A. Figure 3.14 shows the PCB, both unassembled and assembled.

3.2.1

Testing

The basic functionality of the backplane has been tested by the steps shown in table 3.2. The rst step was to do a visual inspection of the circuit board to check that all ICs were mounted correctly, and that there were no short circuits before powering the board. Power was applied to the power slot of the backplane, and the power levels throughout the board were veried using a multimeter. The redundancy of the power system was tested by removing power to one of the power contacts from the power slot, and then measuring that the power was still present. The current limiting circuits were also tested by short-circuiting the power terminals. The digital systems were thoroughly tested in incremental steps. Proper I2C signalling, communication and full speed has been tested by checking that the I2C current monitor circuits could be read. Then, by hard-wiring addresses for each slot, an acknowledge signal was veried when the correct address was applied. The remaining tests were performed by attaching an MCU to the control ports. Bus access, power and reset signals have been 25

Chapter 3. Backplane

Power 5v Ideal 3v3 Diodes Curr. Limit Curr. Limit Power BP I2C Curr. Meas. Curr. Meas. 3v3 5v Power 3v3 5v 3v3 I2C Bus SCL SDA

5v

Module 1 Payload Module 2 Payload Module 3 Payload Module 4 Power

I2C Repeater I2C Repeater I2C Repeater I2C Repeater I2C Repeater I2C Repeater I2C Repeater I2C Repeater

Power

3v3 5v

Module 5 Master1 Module 6 Payload Module 7 Payload Module 8 Master2

Control Bus: ADDR, Module Reset, System Reset, nSet, nPwr, nBus, nAck, Pwr Flag, BP I2C EN

Power

3v3 5v

Power

3v3 5v

Power a b ab

3v3 5v

Figure 3.12: An overview of the backplane, excluding control logic.

26

3.2. Prototyping

I2C SCL 1 I2C SDA 3 Gnd 5

2 3V3 4 Gnd 6 5V

I2C SCL 1 I2C SDA 3 Gnd 5

2 3V3 4 Gnd 6 5V

I2C SCL 1 I2C SDA 3 Gnd 5

3V3_A

4 Gnd 6 5V_A

nReset 7 8 ID0 Module PROG1 9 10 ID1 Module PROG2 11 12 ID2 Module PROG3 13 14 nSet Module PROG4 15 16 nAck

nReset 7 8 ID0 Module PROG1 9 10 ID1 Module PROG2 11 12 ID2 Module PROG3 13 14 RESV0 Module PROG4 15 16 RESV1 nReset 17 18 RESV2 Gnd 19 20 3V3 I2C SCL 21 22 Gnd I2C SDA 23 24 5V

nReset 7 8 ID0 Module PROG1 9 10 ID1 Module PROG2 11 12 ID2 Module PROG3 13 14 RESV0 Module PROG4 15 16 RESV1 nReset 17 18 RESV2 Gnd 19 20 3V3_B I2C SCL 21 22 Gnd I2C SDA 23 24 5V_B

Gnd 17 18 PWR FLAG I2C SCL 19 20 3V3 I2C SDA 21 22 BP I2C EN Module Reset 23 24 5V PROG1 25 26 nBus PROG2 27 28 nPwr PROG3 29 30 ADDR0 PROG4 31 32 ADDR1 System Reset 33 34 ADDR2 Gnd 35 36 Gnd

Figure 3.13: Pinouts for master slots (left), payload slots (middle) and power slot (right).

Figure 3.14: The circuit board for the backplane. 27

Chapter 3. Backplane

Figure 3.15: The nished backplane with OBC module.

toggled using the control bus. The programming interface have been tested using a JTAG interface connected to another MCU.

Table 3.2: Testing specication of the backplane. Step 1 2 3 4 5 6 7 8 9 10 11 12 13 28 Functionality Specication

Visual inspection Check components and soldering Basic power Apply power to both Redundant power Remove power from one Over-Current protection Short-circuit power signals I2C signalling Pull and release I2C lines I2C communication Read current measurement ICs I2C speed Read at 400kHz Module addressing Addressed a slot Power and bus control Turn on/o controls Ack and power ag Address module and check ags Reset system System and module reset Programming bus Signal propagation to module Programming bus JTAG programming

3.2. Prototyping

3.2.2

Results

Overall, the backplane is functioning as expected. However, there have been a few problems regarding the pull-up resistors for the I2C bus and the rst address bit. The bus repeaters needed a lower resistance than the default value of 10k ohms on the common backplane side, to be able to release the bus after a zero was transmitted. This is probably due to the load all the repeaters puts on the common bus, and the resistor is not sucient to pull the line high again. The rst address line also had troubles being pulled high. The watchdog timer required a larger current to pull the line high. The maximum speed of the I2C bus exceeds the specied 400kHz, but communication speeds should still be limited to 400kHz for reliable communication. The programming bus was tested at speeds up to 500kHz, but it can probably work with higher speeds. Power Consumption The backplanes power consumption was measured to be 20mA. The backplane logics runs at 3.3V, and the total power consumption is thus 66mW. The power consumption will of course increase with control and I2C bus activity because of the pull-up resistors.

29

30

Chapter 4 On-Board Controller

The main tasks of the On-Board Controller are to keep track of the satellites health, help to increase its life span and provide support with storage and/or processing capabilities. It will serve as one of the two backplane masters, and will use its heightened responsibility to monitor and act on all communication and behavior of the satellite. Since the OBC will have a supervising responsibility, it is natural that it retains a log of events and house-keeping data. It could be interesting to be able to download this log, or at least a summary, and analyze the behavior of the satellite. Especially getting detailed logs of error condition would be helpful. It is also desirable that the OBC can be used as a helpful tool before ight as well. The OBC can perform debug tasks as monitoring the messages on the data bus and power consumption, reprogram modules on request etc. It would therefore be advantageous to provide an option to interface the OBC to a computer.

4.1

Hardware Design

The hardware will mainly consist of the connector for the backplane, an MCU for processing and memory for dierent purposes. Because of space and power restrictions, hardware redundancy will not be prioritized. Although, 31

Chapter 4. On-Board Controller methods for increasing reliability are discussed and planned for. Methods for using the OBC for manual backplane control are also implemented.

4.1.1

Microcontroller

There were several issues to think about before selecting an MCU. It had to provide low-power modes or sleep modes for saving power, and also be able to process a sucient amount of data. Since the board were to contain a lot of memory, it was also desirable to have integrated support for various memory busses. Another aspect was that the MCU should preferably be of a familiar architecture for both the author and the succeeding developers. The nal choice was the AT32UC3A3256 MCU from Atmel. It runs on the AVR32 core which is designed with power-saving in mind, and oers processing capabilities with up to 92 DMIPS. There is some DSP instructions available, which could be useful for image processing or other sensory equipment. There is also internal support for many dierent memory types, and an ECC generator with support for both Hamming codes and Reed Solomon codes.

4.1.2

Memory Hierarchy

The memory setup will be used for logging events in the satellite, temporary processing storage, module rmwares and possible more. It must therefore contain some dierent type of memory to accommodate all uses. It should also be taken into consideration that some memory types are volatile against radiation, and can suer bit-ips. Also, all memories that are not radiation hardened are vulnerable against latch-up in the on-chip digital circuits, but those will hopefully be handled by the power system of the backplane. First of all an SRAM chip is needed to expand on the limited amount of on-chip Random Access Memory (RAM) on the MCU. This type of memory has a low access time and will help speed up the calculations. Unfortunately, they are sensitive to radiation and bit-ips are a potential danger. [21] A radiation hardened SRAM would have solved this, but as the availability of those are limited a regular variant is still used. The specic chip used 32

4.1. Hardware Design is IS61WV102416BLL-10TLI, and expands the MCU RAM with 16Mbit of storage. For a more long-term logging of data a non-volatile memory was needed. There is also a possibility of SEU for non-volatile memories, so the idea was to store redundant information to be able to detect any anomalies. By using a sophisticated ECC it is possible to use a relatively small amount of bits to detect a fair amount of bit errors, and even correct them. A NAND ash has been used because it comes in relatively large sizes, and there wont be any concerns for having too little space for adding redundancy. A 16Gbit ash, MT29F16G08DAAWP, gives the possibility of storing a lot of housekeeping data and even images. The rmware for the dierent modules in the satellite are most commonly stored in a on-chip ash on the separate MCUs. This ash is also volatile to radiation, and can be struck by a SEU that ips a bit. It will then be necessary to have something to compare the rmware with to detect the error in the ash. When an error is detected the known correct rmware can be uploaded. A correct rmware version must then be available for the OBC. This is done by using an OTP memory which is known to be specially tolerant against radiation. The OTP memory will contain the rmware and perhaps other default settings for all of the modules, and can be used to compare and correct errors.

4.1.3

Backplane Connector

Since the OBC is a master, it will have a master connector following the pinout from gure 3.13. The I2C bus signals are connected to the General Purpose Input/Output (GPIO) pins with integrated I2C support. This means that the MCU can communicate over the I2C bus with much less processing power. The control signals are connected to normal GPIO, and will be congured to use open-drain signalling. This is done to assure that if the two masters ght over control of the backplane (i.e. one master want to transmit 0, and the other master tries to transmit 1) they wont harm the output stage of the GPIO pin. 33

Chapter 4. On-Board Controller

Backplane Connector

Override

USB

AT32UC3A3256

RF Link

SRAM 16Mbit NAND 16Gbit OTP 4Mbit

Figure 4.1: A system overview of the OBC.

Data bus

4.1.4

USB Interface

An USB interface would be a simple way to communicate with the satellite. It could be used to debug and congure the satellite, both in the development process and just before launch. Since the selected MCU has direct support for USB it was not necessary to add any new chips to the design. The MCU is programmed to enumerate on the computer as a standard COM-port and the user can then decide to use a simple terminal or a specialized program to communicate with the satellite.

4.1.5

Manual Override

There are also possible to override the backplane control signals manually. By using some jumpers placed at the edge of the OBC most of the backplane control signals can be operated to e.g. turn o power for a module, select a module for programming and check the power state.

4.1.6

Hardware Overview

An overview of the hardware design for the OBC is shown in gure 4.1. The AT32UC3A3 MCU is connected to the memory hierarchy with a common 34

4.2. Software Design parallell bus. The backplane control signals are connected directly to general purpose input/output pins of the MCU, and some are also connected to the manual override headers. The USB connector is connected to the MCU as well. The wireless module shown in the gure will be discussed in chapter 5.

4.2

Software Design

The OBC will need a complex piece of software to function as a master for the satellite. It has been given many tasks, and all of them needs to be handled in an ecient and secure manner. Because of its heightened status as a master on the backplane, it has a lot of responsibility to not abuse its power and perform potentially devastating mistakes. This has to be kept in mind when developing the software. A lot of the development work for the OBC software still remains, but an overall idea for the various tasks and abilities of the software is outlined. Some aspects have been tested, and hardware specic drivers have been developed and can be used in the future.

4.2.1

Drivers

The OBC contains 3 dierent types of memory devices which have been interfaced to the same bus interface, but in a slightly dierent way. This requires some conguration and setup in software in order to work as expected. The SRAM and OTP memory uses a standard random access addressed interface, but the NAND ash uses a command interface to read and store pages of data. This requires a little framework in order to function. The USB interface also needs some drivers to work. Actually it would take several days, or even weeks, of work to get a usable USB stack up and running. Fortunately, Atmel provides a framework of drivers for most modules and the USB interface is one of them. This framework has been used for both the USB interface and for the memories, with the exception of the NAND ash command interface. Also, some drivers for the backplane has to be developed in order to control all the functions properly. This includes turning the power and bus ac35

Chapter 4. On-Board Controller cess on/o, resetting modules, interpreting bus activity and reprogramming modules. Even the reprogramming must be taken care of by implementing a driver for each of the supported protocols.

4.2.2

Housekeeping

Tasks as supervising the power consumption, bus activity, module health etc. falls under housekeeping. This needs to be handled by the OBC by periodically reading the current measurement circuits on the I2C bus, checking that communication is valid and sending a ping to each of the modules. Housekeeping data should also be stored to the NAND ash and could be used to create a summary for download to the ground station. Then the ground station can request more detailed data of a duration in time that seem interesting.

4.2.3

Operating System

Since the OBC will perform many separate tasks, it would be easier, more ecient and more secure to use some sort of small operating system. There are many operating systems available to select from, and a suitable one should be implemented at a later time.

4.2.4

Support Software

The support software will consist of a python script with a Graphical User Interface (GUI). It will have the ability to connect to the OBC and monitor and control all of the OBC actions. E.g. power consumption, bus activity, module rmware etc. can be read and congured from the interface. All data can be sent and received using the USB interface with the COM-port emulation. 36

4.3. Prototyping

Figure 4.2: The circuit board for the OBC.

4.3

Prototyping

A prototype of the OBC has been developed and tested. The circuit diagram can be found in appendix B. The circuit board is shown in gure 4.2, and an assembled version is shown in gure 4.3. Note that the OTP memory is not mounted since it has to be programmed using a special programmer before mounting. The extra PCB on the top of the gure is the wireless internal communication module discussed in chapter 5.

4.3.1

Testing

The OBC module was tested by attaching it to the backplane through a master slot before applying power to the backplane. Then using the manual override connectors in front on the OBC module, the address was set to the OBC module itself. A JTAG programmer was attached to the JTAG connector, and the chip ID of the MCU was read. To be able to fully debug the rest of the system a rmware emulating a COM port through the USB interface was programmed onto the MCU A simple command interface using single letters, controlled which test the MCU was going to run, and the result of the test was printed back on 37

Chapter 4. On-Board Controller

Figure 4.3: The nished OBC.

the terminal. A full write/read-test of the SRAM was performed, as well as a simple read test on the NAND ash. The OTP memory has unfortunately not been fully tested since the programming socket was not available. The backplane was also controlled by the OBC to check that all the connector pins were correctly placed. The I2C bus was used to read current measurements from the backplane, and a simple JTAG programming driver was written to read the ID from modules.

4.3.2

Results

All functionality of the OBC has proven to work. The memory ICs are able to share a common bus, and operate at the timing specications given in the datasheet. This means that the PCB routing is not a limiting factor for the throughput. 38

4.3. Prototyping Power Consumption The power consumption of the OBC module will rely heavily on the rmware for the MCU. In the worst case scenario with USB connected using no sleep modes, not shutting of clock domains in the MCU or other power optimizations the power consumption was 45mA, or 150mW. When putting the OBC into static sleep mode, which means all clocks are stopped, the power consumption fell to 4.5mA, or 15mW. The datasheet for the SRAM chip reports a nominal consumption of 4mA in retention mode, so below 0.5mA is used for the NAND ash. It is much potential for saving power by carefully using sleep modes as much as possible. Even when the MCU cant sleep it can save a lot of power by using a low operating frequency when little processing power is required. A high frequency should be used when processor intensive tasks should be done, so that the MCU can go back to sleep as soon as possible.

39

40

Chapter 5 Internal Wireless Communication

There are certain disadvantages by using a standard electrically wired data bus for communication between the modules. A short circuit is the rst problem, which would cripple the whole bus. The only way to protect against this would be to have an extra data bus for redundancy. Another problem would be if a module starts ooding the bus with garbage data. One solution for all of this is to use a wireless data bus instead. There are many dierent wireless communication ICs available, and many are optimized for low-power and low-size applications. They also give the option to change the communication frequency, which would x the problem of a module ooding the data bus. A wireless bus is also more exible since it doesnt require any concern for how to connect the dierent modules together. Some of the modules in the student satellite will be equipped with a wireless internal communication module, as described in this chapter. The goal is to test if a wireless internal data bus is a viable solution, and if it could replace the wired bus in the future. It should be as invisible as possible for the module MCUs, i.e. provide a seamless wireless link between the modules. Therefore the wireless module has to be smart and be able to transmit and receive data without help from the module MCU. 41

Chapter 5. Internal Wireless Communication

SPI

nRF24LE1

Filter

Prog

Figure 5.1: An overview of the wireless transceiver module.

5.1

Hardware Design

Since the wireless module should be able to process the wireless transmissions itself, it should contain some sort of a processing unit. There are a number of single-chip solutions with a wireless transceiver and a MCU on the same chip. One of these are the nRF24LE1 from Nordic Semiconductor. This chip has been selected because it can transmit at a rate of up to 2Mbps, and comes in a variety where the rmware for the MCU is stored in an on-chip OTP memory. This will help improve the radiation tolerance of the wireless modules. Figure 5.1 shows an overview of the wireless module hardware. The wireless module contains two crystal oscillators connected to the nRF24LE1 chip. A 16MHz crystal is needed for the wireless transceiver and as a MCU clock, and a 32.768kHz crystal will be used by the chip to synchronize timings of the wireless protocols. By having a reliable synchronization it is possible to sleep between transceiving in order to save a substantial amount of power. A chip antenna has been used instead of a trace antenna to eliminate the need to experiment on the optimal length and geometry of the trace. In addition, the chip antenna takes up a much smaller area than the trace antenna would have. A matching network of inductive coils and capacitors are still needed in order to match the output stage of the wireless transceiver to the chip antenna. A SPI interface will be used between the module MCU and the wireless module. The SPI interface will provide a larger throughput than the I2C 42

5.2. Firmware Design bus, and is necessary in order to take full advantage of the 2Mbps transfer rate of the transceiver. Some extra connectors for reset and programming lines are added as well. These will be helpful during the development stage.

5.2

Firmware Design

Some rmware work is needed on the wireless module too. First of all a decent protocol must be found that will accommodate the various demands on throughput, latency and power consumption. A complicating piece of the puzzle is that the wireless network should be self-reliant and not depending on any form of master node. Some suggestive ideas for the protocol is given in section 5.2.1. The rmware must also keep track of incoming and outgoing data, and where they come from and where they should be sent. Because of the limited amount of memory in the rf transceiver IC, the buer will be too small to hold a signcant amount of packages. Therefore it will be easiest to limit the buer to only be able to hold one incoming and one outgoing package at any given time. The actual wireless packages from nRF24LE1 are limited to only 32 bytes per wireless transmission. If any more data is needed it must be split into several transmissions. The protocol will be able to handle the transmission of the entire buer automatically, but if even larger amount of data needs to be transmitted, such as an image, it must be handled by the transmitting and receiving module MCUs.

5.2.1

Protocol

Addressed Transmission The nRF24LE1 has the possibility to lter and buer wireless packages based on a separate address. If wireless module A is the receiver, it can congure six individual addresses used for six independent links. Then wireless module B has been given one of those six addresses to use when transmitting to wireless module A. When wireless module B transmits a package with this 43

Chapter 5. Internal Wireless Communication address, only wireless module A will receive this package, and will know that the message came from wireless module B because of the address that was used. Table 5.1 shows an example address table for transmission between 3 wireless modules.

Table 5.1: Example address table for wireless transmission. Transmitter Module Module Module Module Module Module A A B B C C Receiver Module Module Module Module Module Module B C A C A B Address 0 1 2 3 4 5

The disadvantage with this approach is that all modules must constantly be in receive mode to check for messages. This will lead to a high power consumption. In addition, if two wireless modules start transmitting at the same time both messages will be corrupted.

Separate Channels

A slightly dierent approach is to use a separate channel for each, instead of the addresses. This will eliminate the danger of collisions, but will still lead to a high power consumption since the modules have to listen all the time. Therefore it could be benecial to combine the use of addresses and channels. By assigning a separate channel for all communications going to module A, B, C etc. and making the transmitter listen for an invitation before transmitting it is possible to put the devices into sleep mode occasionally. Table 5.2 shows a step by step instruction of how a transmission would occur. 44

5.2. Firmware Design Table 5.2: A transmission from Module A to Module B. Step 1 2 3 4 5 6 Module A action Module B action

Change to B channel Sleeping Waiting for invitation Invite C to start transmission Waiting for invitation Receiving Waiting for invitation Invite A to start transmission Transmit data Receiving Receive ack Send ack

Time-Split Channel Further optimization of the power consumption can be done by synchronizing the transmissions. If all modules are synchronized and knows at what point in time it is their turn to transmit it will be easier to plan ahead, and decide when a sleep mode can be entered. If a time-consuming transmission needs to take place it is still possible for the two modules to negotiate a channel change to be able to complete their transmission without interruption from other nodes. An example time division table is shown in table 5.3, and shows how the modules can alternate the control of the wireless channel. Note that only the receiving nodes need to be awake at each point in time. Table 5.3: Dividing the channel controls in time for each link. Time 0 ms 1 ms 2 ms 3 ms 4 ms 5 ms 6 ms Direction A to B A to C B to A B to C C to A C to B A to B

This method will not suer from collisions and will provide the modules 45

Chapter 5. Internal Wireless Communication

Figure 5.2: The wireless module circuit board. Top view on the left, and bottom view on the right.

Figure 5.3: The wireless module. a chance to sleep. However, the latency of a transmission will increase if the modules are allowed to sleep for too long. A good way to synchronize is also needed in order to make this work smoothly.

5.3

Prototyping

The hardware for the wireless module has been prototyped and tested, in addition to some protocol experimentation. The circuit board is shown in gure 5.2, and the completed wireless modules is shown in gure 5.3. Appendix C 46

5.3. Prototyping shows the hardware schematics.

5.3.1

Testing

The wireless module was tested by programming it to constantly increment a variable, and transmit it to a receiving development board with a display. The counter was displayed on the display. Some testing has also been done on various ways to implement a communication protocol for the satellite.

5.3.2

Results

The wireless module is working as expected. Messages can be transmitted and received from the chip antenna. However, there is still some work left to do to nd a suitable protocol for communicating eciently between all of the modules. It could be easier to nd a suitable protocol when the complete usage of the wireless link has been decided. Power Consumption The power consumption of the wireless module is 20mA during constant receive mode, and similar results for constant transmit mode. This is too much since there has to be one wireless module per backplane slot for a complete communication system. However, experimentation with dierent protocols has shown that the power consumption can probably reach as low as 2mA for each wireless module.

47

48

Chapter 6 Discussion
The satellite is suppose to be a self-reliant system. This means that it should be able to automatically handle any error conditions that might occur during its lifespan. It is unfortunately impossible to predict every single problem that might occur. And not all of the ones that can be predicted will be possible to account for completely. A solution using redundant components will consume a lot of space and extra power, and the complexity of connecting these systems could lead to a more fragile system. Since NUTS will follow the CubeSat specication it has a heavily limited amount of space and weight. Because of this, the solutions presented in this thesis has emphasized simplicity over a fully redundant system. The amount of space available for each module is quite limited. By doing a simple design for the backplane it was possible to put all the necessary control logic on it. This will ease the process for module designers, and make the backplane more reliable since all control logic is the same. One simple mistake that could have been done is to use a dierent logic family for the control logic. The logic families have been specially selected to account for voltage range, speed, partial power down and other aspects. The backplane solution takes care of the most important design aspects, which has been to not allow a single fault to take down the whole satellite. This has been done by being able to isolate modules from the rest of the system, and power down modules drawing too much current. There is even a redundant set of regulated power lines in case one regulator fails. 49

Chapter 6. Discussion Space radiation will eventually incapacitate the satellite due to increasing TID, and it is dicult to slow down the process. The satellite has mostly been protected from SEU to stop a sudden radiation burst from causing too much damage. The over-current protection will hopefully act quick enough to be able to stop a latch-up condition from damaging the die. And if the latch-up does not draw enough power to trigger the over-current protection, the OBC will notice the anomaly and do a power toggling. Latch-up can be eliminated by building the logic gates using separate transistors, but it would consume way too much area. SEU aecting memory cells will be detected by the ECC. This will protect against a lot of possible hazards. The OBC will have the main responsibility as a master module on the backplane. It will keep polling the rest of the modules to make sure the systems health is good. In addition, a log of events and statuses will be kept in a NAND ash. The NAND ash is not concidered to be a very reliable memory, not even on the ground. Therefore much redundancy has been planned for the ash memory. By using ECC and storing data twice, data should be kept intact even if some bits are ipped by SEU. There is still the possibility of the NAND ash logic failing totally, but that risk is always present, no matter what memory type is used. The backplane master responsibility is shared with the radio module, which can take control when the ground station sends a specic command. If the OBC suddenly starts misbehaving, the radio module can take over and try to restore the OBC. The radio can even hold a copy of the OBC rmware in order to be able to reprogram it. If the OBC cant be recovered, the radio module can shut o power to the OBC and continue acting as a master. Power consumption for the backplane seems to be well below 100mW. From rough power calculations of the solar panel eciency, the total power budget is about 4W. A consumption of 100mW is therefore a small piece of the total budget. For the OBC the power consumption will be dependent on the programming of the MCU, but it is probable that its power consumption can end at 100mW also. The total power consumption would then be about 5% of the total power budget, which should not be too demanding. Intra-satellite wireless communication will be an interesting addition to the regular wired bus. Since the total speed of the I2C bus has been limited to 400kb/s, the 2Mbit/s wireless link can be used to speed up transmissions of larger data sets. It could even prove to be more power ecient to 50

use this high speed wireless link over the wired I2C bus. Since the I2C bus signals will have to propagate to several separate sub-domains with separate pull-ups. And transmissions will require longer time to complete on the I2C bus, so power consumption could add up to be higher when using the wired bus. In addition, the point to point transmission using the wireless bus will not stop any other modules from communicating.

51

52

Chapter 7 Concluding Remarks

The overall system solution presented in this thesis seems to be a viable design for a reliable satellite. Although, radiation testing has not been done because of lack of equipment, the functionality of isolating separate modules and others have been veried. The design has emphasized simplicity over a complex redundant system, as this has several benets such as lower area and power consumption, and since simple systems generally are more reliable. Low power consumption has been a constant criteria for the backplane OBC and wireless communication module. With the OBC and backplane consuming 5% of the total power budget, there will be plenty of power left for other modules to perform their tasks. The wireless communication could even prove to improve on the overall power budget since transmissions can be done quicker, and devices can go into sleep modes faster. The abrasions from radiation can only be countered by shielding or using dierent manufacturing processes for the ICs. These ICs are hard to nd, and it is almost impossible to shield from the most energetic particles. Therefore eventual failure will occur. However, the most drastic eects of space radiation, such as latch-up and bit-ips, have been taken into account and compensated for in the design. The total lifespan of the satellite will be increased by the proposed solutions.

53

54

Chapter 8 Future Work

8.1 Wireless link

The exact usage of the wireless link must be assessed, and a suitable protocol must be implemented. For now the wireless link is considered an experiment to look at the viability of an internal wireless bus for communications.

8.2

OBC Completion

There are still a lot of work remaining on the OBC module. The behavior of the rmware has only been outlined, and some drivers developed. Still the implementation needs to be done and thoroughly tested. A le system should be implemented on the NAND ash device for logging, and other usage. The OTP memory also need some sort of structure.

8.3

Radiation Detector

There should also be done some research on adding a radiation detector circuit to the system. A photodiode can be used to detect charge injections due to ionizing radiation. This actually works much the same way as the 55

Chapter 8. Future Work reason for latch-up and bit-ips. A charge is injected on the die, and ows as a current through the sensor. This minute current can be amplied and measured to attain an approximation of the amount of radiation. The measurements can be logged and downloaded to the ground station. It could be interesting to see the changes in radiation at various locations in the Van Allen belt, and also compared to the solar cycle. In addition, the measurements could be used by the OBC to determine if certain fragile systems should be shut down during intense radiation showers.

56

Bibliography
[1] Space radiation eects on electronic components in low-earth orbit, tech. rep., NASA, April 1996. Practice No. PD-ED-1258. [2] R. A. Mewaldt, Cosmic rays, 1996. [3] Van allen radiation belt. http://www.britannica.com/EBchecked/ topic/622563/Van-Allen-radiation-belt. [4] J. P. Uyemura, Introduction to VLSI Circuits and Systems. John Wiley & Sons, Inc., 2002. [5] Single event latchup. http://www.aero.org/capabilities/seet/ SElatchup.html. [6] S. Kayali, Space radiation eects on microelectronics. http://parts. jpl.nasa.gov/docs/Radcrs_Final.pdf. [7] Understanding latch-up in advanced cmos logic. http://www. fairchildsemi.com/an/AN/AN-600.pdf, April 1999. AN-600. [8] S. Chen, What types of ecc should be used on ash memory?, tech. rep., Spansion, November 2007. [9] N. Marquardt, Introduction to the principles of vacuum physics. http://www.cientificosaficionados.com/libros/CERN/ vacio1-CERN.pdf. [10] D. Wright, Space debris. http://www.ucsusa.org/assets/ documents/nwgs/wright-space-debris-physics-today.pdf, October 2007. 57

Bibliography [11] T. Miyahira and G. Swift, Evaluation of radiation eects in ash memories. http://klabs.org/richcontent/MAPLDCon98/ Papers/c4_miyahira.doc. [12] A. S. Sedra and K. C. Smith, Microelectronic Circuits. Oxford University Press, 2004. [13] Evaluating embedded non-volatile memory for 65nm and beyond. http://www.sidense.com/images/stories/designcon_8_a_eval_ embedded_nvm_65nm_and_beyond.pdf, 2008. [14] H. S. R. S. V. L. G. L. Hans Reisinger, Martin Franosch and H. Wendt, Patent no. us 6,215,140 b1 - electrically programmable non-volatile memory cell conguration, tech. rep., Siemens Aktiengesellschaft, April 2001. [15] J. Benedetto and C. Hafer, Ionizing radiation response of an amorphous silicon based antifuse, in Radiation Eects Data Workshop, 1997 IEEE, pp. 101 104, jul 1997. [16] Logic guide. http://focus.ti.com/lit/sg/sdyu001z/sdyu001z. pdf, 2009. [17] At32uc3a3 datasheet, March 2010. [18] nrf24le1 - ultra-low power wireless system on-chip solution, August 2010. [19] I. Helland, Systems platform for nano and pico satellites, January 2009. [20] Um10204 - i2c-bus specication and user manual - rev.03, tech. rep., NXP, June 2007. [21] G. S. L.Z. Scheick and S. Guertin, Seu evaluation of sram memories for space applications, 2001.

58

Appendix A Backplane
The source drawings for the hardware of the design is located in this section.

59

60
5 4 3 2 1

NUTS Backplane
Page
1 2 3 PA01 4 5 6 7 8 9 10 11 A00 PA00

Revision History
Revision Comment
Initial Pre-Release Version Fixed errors from initial review

Board Function

Front Page

Appendix A. Backplane

Module Connectors

Power Module 1 & 2

Power Module 3 & 4

Power Module 5 & 6

First Release Version

Power Module 7 & 8

Bus Logic Module 1 & 2

Bus Logic Module 3 & 4

Bus Logic Module 5 & 6

Bus Logic Module 7 & 8

Backplane Logic & Pull-ups

Figure A.1: Backplane schematic, page 1.

/ TOP
Schematic Title Page Title
Designed: Approved:

NUTS Backplane
Front Page
<OrgAddr1>
Size BOM Doc No:

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

Document number

Revision

<Doc>
Sheet Created Date Friday, February 18, 2011
4 3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 1 of

11

Module Connector 1 Module Connector 3

Module Connector 2

Module Connector 4 On Board Data Handling

3V3_MODULE4

3V3_MODULE1 5V_MODULE4 5V_MODULE1 P1 ID4[2..0] ID40 ID41 ID42 SET# ACK# PWR_FLAG BP_I2C_EN BUS_EN# PWR_EN#
D

3V3_MODULE2 5V_MODULE2 P2 ID1[2..0] I2C_SCL2 I2C_SDA2 ID2[2..0] ID20 ID21 ID22 RESV0 RESV1 RESV2 RESET#3 DBG_TMS3 DBG_TDO3 DBG_TCK3 DBG_TDI3 RESV[2..0] ADDR0 ADDR1 ADDR2 RESV[2..0] MODULE_RESET# DBG_TMS DBG_TDO DBG_TCK DBG_TDI SYSTEM_RESET#1 ID30 ID31 ID32 RESV0 RESV1 RESV2 ID3[2..0] RESET#2 DBG_TMS2 DBG_TDO2 DBG_TCK2 DBG_TDI2 RESET#4 DBG_TMS4 DBG_TDO4 DBG_TCK4 DBG_TDI4 I2C_SCL3 I2C_SDA3 P3 I2C_SCL4 I2C_SDA4 5V_MODULE3 P4

3V3_MODULE3

I2C_SCL1 I2C_SDA1 ID10 ID11 ID12 RESV0 RESV1 RESV2 RESV[2..0]

RESET#1 DBG_TMS1 DBG_TDO1 DBG_TCK1 DBG_TDI1

1 3 5 7 9 11 13 15 17 19 21 23

2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23

2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23

2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
ADDR[2..0] GND GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36

GND

GND

GND

GND

GND

GND

3V3_MODULE1 3V3_MODULE3 C1 C4 100N 100N 100N 100N 100N 100N 100N 100N 100N 100N 100N 100N 100N C5 C6 C7 C8 C2 C3 C11 C12 C13 C14 C15 C9 5V_MODULE3 3V3_MODULE4

5V_MODULE1

3V3_MODULE2

5V_MODULE2 5V_MODULE4

C10 100N 100N

C16 100N
C

GND GND GND

GND

GND

GND GND GND

Module Connector 5

Module Connector 6

Module Connector 7

Module Connector 8 RADIO

P5 3V3_MODULE7 3V3_MODULE8 5V_MODULE8

Electrical Power System

3V3_A 5V_MODULE7 5V_MODULE6 P6 P7 ID5[2..0] ID6[2..0] RESET#7 DBG_TMS7 DBG_TDO7 DBG_TCK7 DBG_TDI7 ID70 ID71 ID72 RESV0 RESV1 RESV2 I2C_SCL6 I2C_SDA6 I2C_SCL7 I2C_SDA7 P8

5V_A

3V3_MODULE6

I2C_SCL8 I2C_SDA8

ID8[2..0] ID80 ID81 ID82

I2C_SCL5 I2C_SDA5

ID7[2..0]

RESET#8 DBG_TMS8 DBG_TDO8 DBG_TCK8 DBG_TDI8

SET# ACK# PWR_FLAG BP_I2C_EN BUS_EN# PWR_EN# RESV[2..0] ADDR0 ADDR1 ADDR2

RESET#5 DBG_TMS5 DBG_TDO5 DBG_TCK5 DBG_TDI5 RESET#6 DBG_TMS6 DBG_TDO6 DBG_TCK6 DBG_TDI6 RESV[2..0] 3V3_B 5V_B RESV[2..0] ID60 ID61 ID62 RESV0 RESV1 RESV2

1 3 5 7 9 11 13 15 17 19 21 23
ID50 ID51 ID52 RESV0 RESV1 RESV2

2 4 6 8 10 12 14 16 18 20 22 24 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23

2 4 6 8 10 12 14 16 18 20 22 24

MODULE_RESET# DBG_TMS DBG_TDO DBG_TCK DBG_TDI SYSTEM_RESET#2

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36

ADDR[2..0] GND GND 3V3_MODULE7 3V3_MODULE6 C20 3V3_B C25 C30 100N GND GND GND GND GND 100N 100N C31 C32 100N 100N 100N 100N GND GND GND GND C26 C27 C28 5V_A 5V_B 100N 100N 100N 100N 100N 100N 100N 100N 5V_MODULE6 C21 C22 C23 C17 C18 C19 C24 GND 5V_MODULE7 3V3_MODULE8 5V_MODULE8 GND GND GND GND GND

3V3_A

Figure A.2: Backplane schematic, page 2.

/ TOP
Schematic Title

C29

100N

GND

NUTS Backplane
Page Title
Designed: Approved:

The EPS supplies the 3V3_A, 3V3_B, 5V_A and 5V_B rails. The module 5 power distribution circuit is used to provide protection to the backplane. Module 5 power cannot be turned off.

Module Connectors
<OrgAddr1>
Size BOM Doc No:

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

Document number

Revision

<Doc>
Sheet Created Date Friday, February 18, 2011
3 2

A00
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Sheet 2 of

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61

GND 3V3_COMB1 R7

GND

GND

GND

GND

3 GND

A1 A0

8 7
C45

LED1 GREEN INA219 100N

470R LED3 RED GND R8 100K

ADDR = 0x41
GND

GND

GND

PWR_FLAG1 PWR_ON1

Not Mounted on Flight Version

5V_A

L6

Module 2 Power Distribution

5V_COMB2 U7 R9 U8 5V_SENSE2 5V_MODULE2

Module 2 Power Monitoring

5V_SENSE2 5V_MODULE2 U9 L8 3V3_BP

BLM21PG221S

5V_B

L7

5 IN ON SETI
C48

1 7 FLAG 3
10U 0R04 1% C46

2 2
C49 C50

1 5 OUT INA INB ENA ENB STAT NC1 NC2

1U GND R10 220K MAX14523 GND GND GND GND

OUTA OUTB 9
C51 22U

10 6

2 1

VINVIN+

VS SDA SCL 3 GND

INA219

4 6 5 A1 A0 8 7
C52 100N GND I2C_SDA_BP I2C_SCL_BP C47 10U

2
BLM21BD102S

BLM21PG221S 10U 10U

2 4 3 11 GND GND
LTC4413

8 7 GND GND NC1 NC2

8 9

1 6

INA INB 7 ON SETI 8 9 GND GND

MAX14523 GND GND GND GND

OUTA OUTB FLAG 3

C58

0R04 1%

C53 10U 1U

SDA SCL 3 GND

GND INA219

I2C_SDA_BP I2C_SCL_BP

BLM21PG221S C54 C55

2 4 ENA ENB STAT NC1 NC2 8 7

22U

9
C56

A1 A0

8 7
C57

LED4 GREEN

Figure A.3: Backplane schematic, page 3.

3V3_COMB1 GND 3V3_MODULE1 R3 GND U4 U5 3V3_SENSE1

GND GND
LTC4413

NC1 NC2

R14 220K

100N

ADDR = 0x43
GND GND GND GND GND 3V3_COMB2 R15

/ TOP

Not Mounted on Flight Version

Schematic Title
470R R16 100K LED6 RED
A

NUTS Backplane
Page Title
Designed: Approved:

PWR_FLAG2 PWR_ON2

Power Module 1 & 2

<OrgAddr1>
Size BOM Doc No:

<OrgAddr2>

62
5 4 3 2 1

5V_A

L1

Module 1 Power Distribution

2
5V_COMB1 U1 R1 U2 5V_SENSE1 5V_MODULE1

Module 1 Power Monitoring

5V_B

BLM21PG221S L2

5 IN ON SETI
C37

1 7 FLAG 3
10U U3 0R04 1% C33 5V_SENSE1 5V_MODULE1

2 2 4 6 5
I2C_SDA_BP I2C_SCL_BP C39 100N C38 10U C34 C35

1 5 INA INB ENA ENB STAT NC1 NC2

R2 220K GND 1U

OUTA OUTB 9
C36 22U

10 6 OUT
L3

4
3V3_BP

BLM21PG221S 10U 10U

2 4 3 11 GND GND SDA SCL 3

GND INA219 GND LTC4413 MAX14523 GND GND

8 7 GND GND 8 7 NC1 NC2

8 9

1 6

2 1 VINVIN+ VS

2
BLM21BD102S
D

3V3_A

L4

GND

GND

A1 A0

GND

ADDR = 0x40

BLM21PG221S

3V3_B

L5

5 IN ON SETI
C43

1 7 FLAG 3
10U U6 GND 1U 3V3_SENSE1 3V3_MODULE1 0R04 1% C40

2 2
C41 C42

1 5 INA INB ENA ENB STAT NC1 NC2

R4 220K

OUTA OUTB 9
C44 22U

10 6 OUT

BLM21PG221S 10U 10U

2 4 3 11 GND GND 2 1 VINVIN+ SDA SCL VS 6 5 4

LTC4413 MAX14523

5V_MODULE1

3V3_MODULE1

Appendix A. Backplane

8 7 GND GND NC1 NC2

8 9

1 6

I2C_SDA_BP I2C_SCL_BP

R5 1K

R6 470R

LED2 GREEN
C

ADDR = 0x42
GND GND 5V_MODULE2 3V3_SENSE2 3V3_MODULE2 3V3_MODULE2 R13 U11 3V3_MODULE2

3V3_A

L9

GND

1
3V3_COMB2 U10 U12 3V3_SENSE2

BLM21PG221S

3V3_B

L10

2 1

5 IN OUT

VINVIN+

VS

4 6 5

R11 1K

R12 470R

1 5

10 6

LED5 GREEN

10U

10U

3 11

1 6

Document number

Revision

Module 2 Power Supply

5 4 3

A3

<Cage Code>
Design Created Date: Friday, February 18, 2011
2

<Doc>
Sheet Created Date Tuesday, February 22, 2011 Sheet Modified Date Sunday, March 20, 2011
1

A00
Sheet 3 of 11

5V_A

L11

Module 3 Power Distribution

2
5V_COMB3 U13 R17 U14 5V_SENSE3 5V_MODULE3

Module 3 Power Monitoring

5V_B

BLM21PG221S L12

5 IN ON SETI
C63

1 7 FLAG 3
10U U15 0R04 1% L13 C59 5V_SENSE3 5V_MODULE3 3V3_BP

2 2 4 6 5
I2C_SDA_BP I2C_SCL_BP C64 10U C65 100N GND BLM21BD102S C60 C61

1 5 INA INB ENA ENB STAT NC1 NC2

R18 220K GND 1U

OUTA OUTB 9
C62 22U

10 6 OUT

BLM21PG221S 10U 10U

2 4 3 11 GND GND SDA SCL 3

GND INA219 GND LTC4413 MAX14523 GND GND

8 7 GND GND 8 7 NC1 NC2

8 9

1 6

2 1 VINVIN+ VS

2
D

3V3_A

L14

GND

GND

A1 A0

ADDR = 0x44
3V3_COMB3 GND GND R19 U16 U17 3V3_SENSE3 3V3_MODULE3

BLM21PG221S

3V3_B

L15

5 IN ON SETI
C70

1 7 FLAG 3
10U U18 GND 1U 3V3_SENSE3 3V3_MODULE3 0R04 1% C66

2 2
C67 C68

1 5 INA INB ENA ENB STAT NC1 NC2

R20 220K

OUTA OUTB 9
C69 22U

10 6 OUT

BLM21PG221S 10U 10U

2 4 3 11 GND GND 2 1 VINVIN+ SDA SCL

GND GND

5V_MODULE3

3V3_MODULE3

8 7 GND GND VS 6 5 8 7
C71

8 9 NC1 NC2 4
I2C_SDA_BP I2C_SCL_BP

1 6

R21 1K

R22 470R

LTC4413 GND 3V3_COMB3 R23 GND GND

MAX14523

3 GND
INA219 LED9 RED

A1 A0

LED7 GREEN 100N

2
LED8 GREEN
C

470R

ADDR = 0x45
GND GND

R24 100K

GND

GND

PWR_FLAG3 PWR_ON3

Not Mounted on Flight Version

5V_A 5V_SENSE4 5V_COMB4 U19 R25 U20 5V_SENSE4 5V_MODULE4 5V_MODULE4

L16

Module 4 Power Distribution

Module 4 Power Monitoring

L17 U21 3V3_BP

BLM21PG221S

5V_B

L18

5 IN ON SETI
C77

1 7 FLAG 3
10U 0R04 1% C72

2 2
C74 C75

1 5 OUT INA INB ENA ENB STAT NC1 NC2

1U GND R26 220K MAX14523 GND GND GND GND 3V3_SENSE4 3V3_COMB4 U23 R29 U24 3V3_SENSE4 3V3_MODULE4

OUTA OUTB 9
C76 22U

10 6

2 1

VINVIN+

VS SDA SCL 3 GND

INA219

4 6 5 A1 A0 8 7
C78 100N GND I2C_SDA_BP I2C_SCL_BP C73 10U

2
BLM21BD102S

BLM21PG221S 10U 10U

2 4 3 11 GND GND
LTC4413

8 7 GND GND NC1 NC2

8 9

1 6

ADDR = 0x46
GND 3V3_MODULE4 U22 GND 5V_MODULE4 3V3_MODULE4

3V3_A

L19

GND

2 2 1

BLM21PG221S

VS SDA SCL

4 VINVIN+ 6 5 3 8 7
I2C_SDA_BP I2C_SCL_BP R27 1K R28 470R

3V3_B

L20

5 IN ON SETI
C83

INA INB 7 FLAG 3 1 6

1U R30 220K 0R04 1%

OUTA OUTB 2 STAT NC1 NC2

MAX14523 GND GND GND GND

C79 10U

BLM21PG221S C80 10U 10U C81

2 4 ENA ENB 9
C82 22U

GND
INA219 GND

A1 A0

C84

LED10 GREEN 100N

2
LED11 GREEN

1 5 OUT

10 6

Figure A.4: Backplane schematic, page 4.

3 11 GND GND
LTC4413 GND 3V3_COMB4 R31

GND GND

NC1 NC2

ADDR = 0x47
GND GND

GND

GND

/ TOP

Not Mounted on Flight Version

Schematic Title
470R R32 100K LED12 RED
A

NUTS Backplane
Page Title
Designed: Approved:

PWR_FLAG4 PWR_ON4

Power Module 3 & 4

<OrgAddr1>
Size BOM Doc No:

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

8 7

8 9

Document number

Revision

<Doc>
Sheet Created Date Monday, March 07, 2011
3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 4 of

11

63

1
C96 10U 10U

2 3 11
22U

ENA ENB STAT NC1 NC2

1U GND R39 220K MAX14523 GND GND GND GND GND

SETI 8 9 GND GND NC1 NC2 1 6 3 GND

BLM21PG221S

GND GND
LTC4413

8 7

A1 A0
INA219

8 7
C97

LED14 GREEN 100N

ADDR = 0x49
GND

GND

GND

GND

Not Mounted on Flight Version

Module 6 Power Distribution

2
5V_SENSE6 5V_COMB6 U32 R40 U33 5V_MODULE6

Module 6 Power Monitoring

5V_SENSE6 5V_MODULE6 U31 L27 3V3_BP

5V_A

L26

BLM21PG221S

5V_B

L28

2 1 OUT FLAG SETI

C104

VINVIN+

VS SDA SCL

4 6 5 3 8 7
I2C_SDA_BP I2C_SCL_BP C98 10U

2
BLM21BD102S

5 IN ON 3 1 6
1U R41 220K

4 2
0R04 1% C99 10U

1 7 9
C102 22U C100 C101

2 2 4 ENA ENB STAT NC1 NC2

MAX14523 GND GND GND GND

1 5 INA INB OUTA OUTB

10 6

BLM21PG221S 10U 10U

GND
INA219

A1 A0

C103 100N GND GND GND

B

3 11 GND GND
LTC4413

8 7 GND GND NC1 NC2

8 9

ADDR = 0x4a
GND 3V3_SENSE6 3V3_MODULE6 U34 5V_MODULE6 3V3_MODULE6

3V3_A

L29

GND

1
3V3_COMB6 U35 U36

2
3V3_SENSE6 R44 3V3_MODULE6

2 1

BLM21PG221S

VINVIN+

VS SDA SCL 3 GND

0R04 1% C105 10U INA219

4 6 5 A1 A0 8 7
C109 R42 1K I2C_SDA_BP I2C_SCL_BP R43 470R

5 IN ON SETI 8 9 GND GND

MAX14523 GND GND GND

1 7 FLAG 3 9
C108 22U

2 2
C106 C107

1 5 INA INB ENA ENB STAT NC1 NC2 8 7 NC1 NC2 1 6 GND GND
LTC4413 GND 3V3_COMB6 R46

OUTA OUTB

10 6 OUT

BLM21PG221S 10U 10U

2 4 3 11

LED16 GREEN C110 1U GND GND GND GND <Schematic Path> TOP GND GND R45 220K 100N

3V3_B

L30

Figure A.5: Backplane schematic, page 5.

LTC4413 GND GND GND GND GND GND MAX14523 GND 3V3_COMB_BP 3V3_SENSE5 U29 R36 U30 3V3_BP 3V3_SENSE5 3V3_BP

ADDR = 0x4b

Not Mounted on Flight Version

Schematic Title
A

470R R47 100K LED18 RED

NUTS Backplane
Page Title
Designed: Approved:

Power Module 3 & 4

<OrgAddr1>
Size BOM Doc No:

PWR_FLAG6 PWR_ON6

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

64
5 4 3 2 1

Backplane Power Distribution

3V3_COMB_BP LED13 R33

Backplane Power Monitoring

1
RED 5V_SENSE5 5V_BP U27 5V_BP 5V_COMB_BP 5V_SENSE5 U26 R34 470R

Since this module supplies the backplane power, it cannot be turned off. (Turning off the backplane power will cause it to automatically be turned on again anyway) Latch-up protection is still present.
2
L22

5V_A

L21

3V3_BP

1
U25

2 2 1 VINVIN+ SDA SCL 3 GND

C91 100N GND INA219

VS 6 5
I2C_SDA_BP I2C_SCL_BP

4
C85 10U

2
BLM21BD102S
D

BLM21PG221S

1 5 INA INB 7 ON SETI

C90

OUTA OUTB FLAG 3

10U 1U GND

10 6 IN 2
0R04 1% C86

5 OUT

5V_B

L23 C87 C88

2 4 ENA ENB STAT NC1 NC2

R35 220K

9
C89 22U

A1 A0

8 7

1
10U 10U

2 3 11 GND GND GND GND NC1 NC2 8 7 8 9 1 6

BLM21PG221S

ADDR = 0x48

3V3_A

L24 5V_BP 3V3_BP

1
U28

2 1 5 INA INB 7 ON 3
10U

Appendix A. Backplane

BLM21PG221S

OUTA OUTB FLAG 2

0R04 1% C92

10 6 IN SDA SCL OUT VINVIN+ VS 9

C95

2 1

4 6 5
I2C_SDA_BP I2C_SCL_BP R37 1K R38 470R

3V3_B C93 C94

L25

2 4

LED15 GREEN
C

LED17 GREEN

Document number

Revision

<Doc>
Sheet Created Date Monday, March 07, 2011
4 3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 5 of

11

5V_A

L31

Module 7 Power Distribution

2
5V_COMB7 U37 R48 U38 5V_SENSE7 5V_MODULE7

Module 7 Power Monitoring

5V_B

BLM21PG221S L32

5 IN ON SETI
C115

1 7 FLAG 3
10U U39 0R04 1% L33 C111 5V_SENSE7 5V_MODULE7 3V3_BP

2 2 4 6 5
I2C_SDA_BP I2C_SCL_BP C116 10U C117 100N GND BLM21BD102S C112 C113

1 5 INA INB ENA ENB STAT NC1 NC2

R49 220K GND 1U

OUTA OUTB 9
C114 22U

10 6 OUT

BLM21PG221S 10U 10U

2 4 3 11 GND GND SDA SCL 3

GND INA219 GND LTC4413 MAX14523 GND GND

8 7 GND GND 8 7 NC1 NC2

8 9

1 6

2 1 VINVIN+ VS

2
D

3V3_A

L34

GND

GND

A1 A0

ADDR = 0x4c
3V3_COMB7 GND GND R50 U40 U41 3V3_SENSE7 3V3_MODULE7

BLM21PG221S

3V3_B

L35

5 IN ON SETI
C122

1 7 FLAG 3
10U U42 GND 1U 3V3_SENSE7 3V3_MODULE7 0R04 1% C118

2 2
C119 C120

1 5 INA INB ENA ENB STAT NC1 NC2

R51 220K

OUTA OUTB 9
C121 22U

10 6 OUT

BLM21PG221S 10U 10U

2 4 3 11 GND GND 2 1 VINVIN+ SDA SCL

GND GND

5V_MODULE7

3V3_MODULE7

8 7 GND GND VS 6 5 8 7
C123

8 9 NC1 NC2 4

1 6

R52 1K

R53 470R

LTC4413 GND 3V3_COMB7 R54 GND GND

MAX14523

I2C_SDA_BP I2C_SCL_BP

3 GND
INA219 LED21 RED

A1 A0

LED19 GREEN 100N

2
LED20 GREEN
C

470R

ADDR = 0x4d
GND GND

R55 100K

GND

GND

PWR_FLAG7 PWR_ON7

Not Mounted on Flight Version

5V_A

L36

Module 8 Power Distribution

5V_SENSE8 5V_COMB8 U44 R56 U45 5V_MODULE8 5V_SENSE8 5V_MODULE8

Module 8 Power Monitoring

L38 U43 3V3_BP

BLM21PG221S

5V_B

L37

5 IN ON SETI
C130

1 7 FLAG 3
10U 0R04 1% C124

2 2
C126 C127

1 5 OUT INA INB ENA ENB STAT NC1 NC2

1U GND R57 220K MAX14523 GND GND GND GND

OUTA OUTB 9
C128 22U

10 6

2 1

VINVIN+

VS SDA SCL 3 GND

INA219

4 6 5 A1 A0 8 7
C129 100N GND I2C_SDA_BP I2C_SCL_BP C125 10U

2
BLM21BD102S

BLM21PG221S 10U 10U

2 4 3 11 GND GND
LTC4413

8 7 GND GND NC1 NC2

8 9

1 6

ADDR = 0x4e
GND GND 5V_MODULE8 3V3_SENSE8 3V3_SENSE8 3V3_MODULE8 R60 3V3_MODULE8 U48 3V3_MODULE8

3V3_A

L39

GND

1
3V3_COMB8 U46 U47

BLM21PG221S

3V3_B

L40

2 1
C131 10U

5 IN ON SETI
C135

INA INB 7 FLAG 3 1 6

1U R61 220K 0R04 1%

OUTA OUTB 2 STAT NC1 NC2

MAX14523 GND GND GND GND

SDA SCL 3 GND A1 A0

I2C_SDA_BP I2C_SCL_BP

BLM21PG221S C132 10U 10U C133

2 4 ENA ENB 9
C134 22U

8 7
C136

LED22 GREEN GND

2
LED23 GREEN

1 5 OUT

10 6

VINVIN+

VS

4 6 5

R58 1K

R59 470R

Figure A.6: Backplane schematic, page 6.

3 11 GND GND
LTC4413 GND 3V3_COMB8 R62

GND GND

NC1 NC2

INA219

100N

ADDR = 0x4f
GND GND

<Schematic Path> GND TOP

Schematic Title

GND

Not Mounted on Flight Version

8 7

8 9

470R R63 100K LED24 RED

NUTS Backplane
Page Title
Designed: Approved:

PWR_FLAG8 PWR_ON8

Power Module 3 & 4

<OrgAddr1>
Size BOM Doc No:

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

Document number

Revision

<Doc>
Sheet Created Date Monday, March 07, 2011
3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 6 of

11

65

ADDR0 GND C137 C138 SELECT#1 74LVC74A 74LVC1G332 74LVC2G02

10 1Q
100N 100N I2C_SCL I2C_SDA

1Q 1 8
R64 10K R65 10K

U49A U51A ID11

1PRE 1CLK 1D 1CLR EN SCLA SDAA Gnd SCLB SDAB 7 6

I2C_SCL1 I2C_SDA1

Vcca Vccb

U49B ID12

2Q 2Q
U55C GND

PCA9517

4 6
PWR_ON1 U54B

10 11 12 13 2PRE 2CLK 2D 2CLR 8 VCC

C140 74LVC74A

1
U58A GND U55B

1Q
GND

U63

1 8

1PRE 1CLK 1D 1CLR 1Q

I2C_SCL I2C_SDA

EN SCLA SDAA

ID21

1 3 4
SET# U60A 74LVC74A

2 3

Vcca Vccb

2
U61B

U62B

Gnd

2Q 2Q 8

PCA9517

66
5 4 3 2 1

Module 1 Address match, flip-flops & I2C repeater

3V3_BP U49C ID10 C212 U51B U52C U49E

3V_I2C

3V3_MODULE1

Decoupling

3V3_BP

ADDR[2..0]

ID1[2..0]

9 8 5
U53 100N

U50A

VCC 2 GND GND 4 7 GND

5 VCC

VCC

14
C139 100N

BUS_EN#

4 3 2 1 6 5 2 3

74LVC86A
D

1 3 4
SET# U52A

ADDR1

2 7 2 9
PWR_STATE#1 GND U50B

1 3 6 1

3V3_BP

U50C

ADDR2 BP_RESET#

5 5 2
100N

PWR_EN#

VCC GND
74LVC2G07

5
C141

VCC 7
100N

14
C142

3 GND
74LVC1G32 74LV4066

GND
74LVC74A

100N

Module 1 Reset & Debug Signals

U56A

Module 1 Acknowledge & Power flag

2 3 9 10
3V3_BP GND U49D DBG_TCK1 DBG_TDI1 DBG_TDO1 DBG_TMS1

U52B

DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y 1Z 2Z 3Z 4Z

3V3_BP

PWR_STATE#1

5 3 6
U57A R66 100K

Appendix A. Backplane

SELECT#1

12 11
PWR_FLAG1

U57B

U58B

U56B

13 5 6 12 1E 2E 3E 4E
PWR_FLAG

13 3 GND

VCC

5
C143

VCC 2
100N 74LVC1G125

5
C144

VCC GND
74LVC1G11

14
C145

U54A

7
100N

GND
74LV4066

100N
C

4 2
RESET#1 ACK# U55A

1 3 6 4 6
SELECT#1

3 1

MODULE_RESET# 74LVC1G11

GND 3V3_BP

SYSTEM_RESET#1

SYSTEM_RESET#2

Decoupling
U59B U60C 3V3_MODULE2 U61E

Module 2 Address match, flip-flops & I2C repeater

3V_I2C 3V3_BP C213 U61C ID20

VCC 2 GND
74LVC1G332

5
C146

VCC 4
100N R67 10K R68 10K

8
C147

VCC GND
74LVC2G02

14
C148

ADDR[2..0]

ID2[2..0]

7
100N

GND
74LVC86A

100N

9 8
U62A

ADDR0 SELECT#2 BUS_EN#

10 5 6 5

100N

U61A U59A

4 3 2 1

3V3_BP GND

ADDR1

2 7 9
PWR_STATE#2

1 3 6 1

SCLB SDAB

7 6

I2C_SCL2 I2C_SDA2

U64B

U65C

U62C

VCC 3 GND

5
C149

VCC 2
100N

5
C150

VCC GND 7
100N

14
C151

ID22

4 6 5
74LVC74A PWR_EN# BP_RESET#

10 11 12 13 2PRE 2CLK 2D 2CLR

GND
PWR_ON2 GND 74LVC1G32 74LVC2G07 74LVC74A

100N

ADDR2

3V3_BP GND

Module 2 Reset & Debug Signals

U66A 74LV4066

Module 2 Acknowledge & Power flag

12 13

U61D

U67B

U68B

U66B

11 3
3V3_BP GND U67A PWR_FLAG R69 100K

VCC GND

5
C152

VCC 2
100N 74LVC1G125

5
C153

VCC GND
74LVC1G11

14
C154

7
100N

GND
74LV4066

Figure A.7: Backplane schematic, page 7.

U60B DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y 1Z 2Z 3Z 4Z
DBG_TCK2 DBG_TDI2 DBG_TDO2 DBG_TMS2

2 3 9 10

100N

PWR_STATE#2

5 3 6 13 5 6 12 1E 2E 3E 4E 4
74LVC1G125 U68A U65B U65A

SELECT#2

PWR_FLAG2

/ TOP

GND

Schematic Title
A

U64A

1 4 2
74LVC1G11

NUTS Backplane
ACK#

1 3 6 4 3 4

RESET#2

SELECT#2 Designed: Approved:

Page Title

MODULE_RESET#

Bus Logic Module 1 & 2

<OrgAddr1>
Size BOM Doc No:

SYSTEM_RESET#1

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

Document number

Revision

SYSTEM_RESET#2

<Doc>
Sheet Created Date Monday, March 07, 2011
4 3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 7 of

11

Module 3 Address match, flip-flops & I2C repeater

3V3_BP U69C ID30 ADDR0 GND C155 C156 C157 SELECT#3 74LVC74A 74LVC1G332 74LVC2G02 74LVC86A
D

3V_I2C

3V3_MODULE3

Decoupling
U71B U72C U69E

3V3_BP

ADDR[2..0]

C214

ID3[2..0]

9 10 1Q
100N 100N 100N I2C_SCL I2C_SDA

U70A

1Q 1 8 EN SCLA SDAA Gnd

3V3_BP GND

8 5
U73 R70 10K R71 10K

100N

VCC 2 GND GND GND 4 7

5 VCC VCC

14

U69A U71A ID31

1PRE 1CLK 1D 1CLR 2 3 SCLB SDAB

I2C_SCL3 I2C_SDA3

1 3 4
SET# U72A

Vcca Vccb

BUS_EN#

4 3 2 1 6 5 7 6

ADDR1

2 7 2Q 2Q
U75C GND PCA9517 U70B

1 3 6 1 4 2 9
PWR_STATE#3

U69B ID32

4 6
PWR_ON3 U74B U70C

10 11 12 13 2PRE 2CLK 2D 2CLR 8 VCC

C158 C159 74LVC74A PWR_EN#

ADDR2

5 5 VCC 2
100N 74LVC2G07

5 7
100N

VCC GND
74LVC74A

14
C160 100N

BP_RESET#

3 GND
74LVC1G32

GND

Module 3 Reset & Debug Signals

U76A 74LV4066

Module 3 Acknowledge & Power flag

2 3 9 10
3V3_BP GND DBG_TCK3 DBG_TDI3 DBG_TDO3 DBG_TMS3 U69D U77B U78B

U72B

DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y 1Z 2Z 3Z 4Z

3V3_BP

PWR_STATE#3

5 3 6
U77A R72 100K U76B

SELECT#3

12
PWR_FLAG3

13 5 6 12 1E 2E 3E 4E
PWR_FLAG

4 13
C161

2 3 GND
100N 74LVC1G125 GND U75A

11 2

VCC

VCC GND
74LVC1G11

5
C162

VCC 7
100N

14
C163

U74A

GND
74LV4066

1
U78A U75B

100N
C

4 2
RESET#3 ACK# GND

1 3 6 4 6
SELECT#3

3 1

MODULE_RESET# 74LVC1G11

SYSTEM_RESET#1

SYSTEM_RESET#2

Decoupling
U79B U80C U81E

3V3_BP

Module 4 Address match, flip-flops & I2C repeater

3V_I2C 3V3_BP C215 3V3_MODULE4 U81C ID40

VCC 2 GND
74LVC1G332

5
C164

VCC 4
100N

8
C165

VCC GND
74LVC2G02

14
C166

ADDR[2..0]

ID4[2..0]

7
100N

GND
74LVC86A

100N

9 8 1Q 1 8
GND U82A

ADDR0 U83 SELECT#4 BUS_EN#

10 5
R74 10K R73 10K

100N

1PRE 1CLK 1D 1CLR 1Q

I2C_SCL I2C_SDA

EN SCLA SDAA Gnd SCLB SDAB 7 6

ID41

1 3 4
SET# U80A 74LVC74A

2 3

Vcca Vccb

U81A U79A

4 3 2 1 6 5

3V3_BP GND

ADDR1

2 7 2
U81B U82B

1 3 6 1 9
PCA9517 PWR_STATE#4

I2C_SCL4 I2C_SDA4

U84B

U85C

U82C

VCC 3 GND
74LVC1G32

5
C167

VCC 2
100N

5
C168

VCC GND
74LVC2G07

14
C169

2Q 2Q 8
PWR_ON4 GND

7
100N

ID42

4 6 5
74LVC74A PWR_EN# BP_RESET#

10 11 12 13 2PRE 2CLK 2D 2CLR

GND
74LVC74A

100N

ADDR2

3V3_BP GND

Module 4 Reset & Debug Signals

U88A 74LV4066 3V3_BP

Module 4 Acknowledge & Power flag

12 13

U81D

U86B

U87B

U88B

11 3 GND

VCC

5
C170

VCC 3
100N 74LVC1G125 GND

5
C171

VCC GND
74LVC1G08

14
C172

7
100N

GND
74LV4066

Figure A.8: Backplane schematic, page 8.

U80B DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y
U86A PWR_FLAG

1Z 2Z 3Z 4Z

2 3 9 10
DBG_TCK4 DBG_TDI4 DBG_TDO4 DBG_TMS4

100N

PWR_STATE#4

5 3 6 4
74LVC1G125 U87A U85B U85A

SELECT#4

R75 100K

13 5 6 12 1E 2E 3E 4E

PWR_FLAG4

/ TOP

GND

Schematic Title
A

U84A

1 4 2 2
RESET#4 ACK#

1 4 3 4 6

NUTS Backplane
1
SELECT#4 Designed: Approved:

Page Title

MODULE_RESET#

Bus Logic Module 1 & 2

<OrgAddr1>
Size BOM Doc No:

SYSTEM_RESET#2

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011
3 2

Document number

Revision

(Module 4 is only connected to SYSTEM_RESET#2, as it supplies the SYSTEM_RESET#1 signal, and connot be allowed to reset itself in this way).
5 4

<Doc>
Sheet Created Date Monday, March 14, 2011 Sheet Modified Date Sunday, March 20, 2011
1

A00
Sheet 8 of 11

67

ADDR0 GND C173 C174 SELECT#5 74LVC1G332 74LVC2G02 3V3_BP U91A U93A I2C_SCL I2C_SDA

10 EN
100N 100N

U92

1 8

Vcca Vccb

7 Q
U94B U95C GND

Q 3
PCA9517

Gnd

U89B ID52

7 1 2 6 5 4
GND

1Q
GND

U103

1 8

1PRE 1CLK 1D 1CLR 1Q

I2C_SCL I2C_SDA

EN SCLA SDAA

ID61

1 3 4
SET# U100A 74LVC74A

2 3

Vcca Vccb

2
U101B

U102B

Gnd

2Q 2Q 8

PCA9517

68
5 4 3 2 1

Module 5 Address match, flip-flops & I2C repeater

C216 U89C ID50 U90B U91C U89E

3V_I2C

3V3_MODULE5

Decoupling

3V3_BP

ADDR[2..0]

ID5[2..0]

9 8
R76 10K R77 10K 100N

VCC 2 GND GND 4 7 GND

5 VCC

VCC

14
C175 100N

5
U89A U90A ID51

74LVC86A
D

1 3 4
SET#

2 3 SCLA SDAA SCLB SDAB

I2C_SCL5 I2C_SDA5

7 6

ADDR1

2 2 4 6
74LVC1G74 BUS_EN#

1 3 6 1 SD CP D RD

3V3_BP

U93B

ADDR2

5 VCC
C176

5 2
100N

VCC GND
74LVC2G07

5
C177

VCC 4
100N

8
C178

BP_RESET#

3 GND
74LVC1G32 U96A 74LV4066

GND
74LVC1G74

100N

Module 5 Reset & Debug Signals Module 5 Acknowledge

DBG_TCK5 DBG_TDI5 DBG_TDO5 DBG_TMS5 GND DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y 1Z 2Z 3Z 4Z

2 3 9 10

3V3_BP

Appendix A. Backplane

SELECT#5

U98B U95A ACK# U89D

U96B

13 5 6 12 1E 2E 3E 4E 6
SELECT#5

VCC 12 11 13 2 GND
74LVC1G11

5
C180

VCC 7
100N

14
C181

U94A

GND
74LV4066

100N
C

1
U98A U95B

4 2
RESET#5 74LVC1G11

1 3 6 4 3 4

GND GND 3V3_BP

MODULE_RESET#

SYSTEM_RESET#1

SYSTEM_RESET#2

Decoupling
U99B U100C 3V3_MODULE6 U101E

Module 6 Address match, flip-flops & I2C repeater

3V_I2C 3V3_BP C217 U101C ID60

VCC 2 GND
74LVC1G332

5
C182

VCC 4
100N R78 10K R79 10K

8
C183

VCC GND
74LVC2G02

14
C184

ADDR[2..0]

ID6[2..0]

7
100N

GND
74LVC86A

100N

9 8
U102A

ADDR0 SELECT#6 BUS_EN#

10 5 6 5

100N

U101A U99A

4 3 2 1

3V3_BP GND

ADDR1

2 7 9
PWR_STATE#6

1 3 6 1

SCLB SDAB

7 6

I2C_SCL6 I2C_SDA6

U104B

U105C

U102C

VCC 3 GND

5
C185

VCC 2
100N

5
C186

VCC GND 7
100N

14
C187

ID62

4 6 5
74LVC74A PWR_EN# BP_RESET#

10 11 12 13 2PRE 2CLK 2D 2CLR

GND
PWR_ON6 GND 74LVC1G32 74LVC2G07 74LVC74A

100N

ADDR2

3V3_BP GND

Module 6 Reset & Debug Signals

U108A 74LV4066

Module 6 Acknowledge & Power flag

12 13

U101D

U106B

U107B

U108B

11 3
3V3_BP GND U106A PWR_FLAG R80 100K

VCC GND

5
C188

VCC 2
100N 74LVC1G125

5
C189

VCC GND
74LVC1G11

14
C190

7
100N

GND
74LV4066

Figure A.9: Backplane schematic, page 9.

U100B DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y 1Z 2Z 3Z 4Z
DBG_TCK6 DBG_TDI6 DBG_TDO6 DBG_TMS6

2 3 9 10

100N

PWR_STATE#6

5 3 6 13 5 6 12 1E 2E 3E 4E 4
74LVC1G125 U107A U105B U105A

SELECT#6

PWR_FLAG6

/ TOP

GND

Schematic Title
A

U104A

1 4 2
74LVC1G11

NUTS Backplane
ACK#

1 3 6 4 3 4

RESET#6

SELECT#6 Designed: Approved:

Page Title

MODULE_RESET#

Bus Logic Module 1 & 2

<OrgAddr1>
Size BOM Doc No:

SYSTEM_RESET#1

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

Document number

Revision

SYSTEM_RESET#2

<Doc>
Sheet Created Date Tuesday, March 15, 2011
4 3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 9 of

11

Module 7 Address match, flip-flops & I2C repeater

3V3_BP U109C ID70 ADDR0 GND C191 C192 C193 SELECT#7 74LVC74A 74LVC1G332 74LVC2G02 74LVC86A
D

3V_I2C

3V3_MODULE7

Decoupling
U111B U112C U109E

3V3_BP

ADDR[2..0]

C218

ID7[2..0]

9 10 1Q
100N 100N 100N I2C_SCL I2C_SDA

U110A

1Q 1 8 EN SCLA SDAA Gnd

3V3_BP GND

8 5
U113 R81 10K R82 10K

100N

VCC 2 GND GND GND 4 7

5 VCC VCC

14

U109A U111A ID71

1PRE 1CLK 1D 1CLR 2 3 SCLB SDAB

I2C_SCL7 I2C_SDA7

1 3 4
SET# U112A

Vcca Vccb

BUS_EN#

4 3 2 1 6 5 7 6

ADDR1

2 7 2Q 2Q
U115C GND PCA9517 U110B

1 3 6 1 4 2 9
PWR_STATE#7

U109B ID72

4 6
PWR_ON7 U114B U110C

10 11 12 13 2PRE 2CLK 2D 2CLR 8 VCC

C194 C195 74LVC74A PWR_EN#

ADDR2

5 5 VCC 2
100N 74LVC2G07

5 7
100N

VCC GND
74LVC74A

14
C196 100N

BP_RESET#

3 GND
74LVC1G32

GND

Module 7 Reset & Debug Signals

U116A 74LV4066 U109D

Module 7 Acknowledge & Power flag

12 11
3V3_BP GND GND U117B U118B

U112B

DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y 13 1Z 2Z 3Z 4Z
DBG_TCK7 DBG_TDI7 DBG_TDO7 DBG_TMS7

2 3 9 10

3V3_BP

PWR_STATE#7

5 3 6
U117A PWR_FLAG C197 R83 100K U116B

SELECT#7

13 5 6 12 1E 2E 3E 4E 4
PWR_FLAG7

2 3 GND
100N 74LVC1G125 U115A

VCC 2

VCC GND
74LVC1G11

5
C198

VCC 7
100N

14
C199

U114A

GND
74LV4066

1
U118A U115B

100N
C

4 2
RESET#7 ACK# GND

1 3 6 4 6
SELECT#7

3 1

MODULE_RESET# 74LVC1G11

SYSTEM_RESET#1

SYSTEM_RESET#2

Decoupling
U119B U120C U121E

3V3_BP

Module 8 Address match, flip-flops & I2C repeater

3V_I2C 3V3_BP C219 3V3_MODULE8 U121C ID80

VCC 2 GND
74LVC1G332

5
C200

VCC 4
100N

8
C201

VCC GND
74LVC2G02

14
C202

ADDR[2..0]

ID8[2..0]

7
100N

GND
74LVC86A

100N

9 8 1Q 1 8
GND U122A

ADDR0 U123 SELECT#8 BUS_EN#

10 5
R84 10K R85 10K

100N

1PRE 1CLK 1D 1CLR 1Q

I2C_SCL I2C_SDA

EN SCLA SDAA Gnd SCLB SDAB 7 6

ID81

1 3 4
SET# U120A 74LVC74A

2 3

Vcca Vccb

U121A U119A

4 3 2 1 6 5

3V3_BP GND

ADDR1

2 7 2
U121B U122B

1 3 6 1 9
PCA9517 PWR_STATE#8

I2C_SCL8 I2C_SDA8

U124B

U125C

U122C

VCC 3 GND
74LVC1G32

5
C203

VCC 2
100N

5
C204

VCC GND
74LVC2G07

14
C205

2Q 2Q 8
PWR_ON8 GND

7
100N

ID82

4 6 5
PWR_EN# 74LVC74A BP_RESET#

10 11 12 13 2PRE 2CLK 2D 2CLR

GND
74LVC74A

100N

ADDR2

3V3_BP GND

Module 8 Reset & Debug Signals

U126A 74LV4066 3V3_BP

Module 8 Acknowledge & Power flag

12 13

U121D

U127B

U128B

U126B

11 3 GND

VCC

5
C206

VCC 3
100N 74LVC1G125 GND

5
C207

VCC GND
74LVC1G08

14
C208

7
100N

GND
74LV4066

Figure A.10: Backplane schematic, page 10.

U120B DBG_TCK DBG_TDI DBG_TDO DBG_TMS

1 4 8 11 1Y 2Y 3Y 4Y
U127A PWR_FLAG

1Z 2Z 3Z 4Z

2 3 9 10
DBG_TCK8 DBG_TDI8 DBG_TDO8 DBG_TMS8

100N

PWR_STATE#8

5 3 6 4
74LVC1G125 U128A U125B U125A

SELECT#8

R86 100K

13 5 6 12 1E 2E 3E 4E

PWR_FLAG8

/ TOP

GND

Schematic Title
A

U124A

1 4 2 2
RESET#8 ACK#

1 4 3 4 6

NUTS Backplane
1
SELECT#8 Designed: Approved:

Page Title

MODULE_RESET#

Bus Logic Module 1 & 2

<OrgAddr1>
Size BOM Doc No:

SYSTEM_RESET#1

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011
3 2

Document number

Revision

(Module 8 is only connected to SYSTEM_RESET#1, as it supplies the SYSTEM_RESET#2 signal, and connot be allowed to reset itself in this way).
5 4

<Doc>
Sheet Created Date Tuesday, March 15, 2011 Sheet Modified Date Sunday, March 20, 2011
1

A00
Sheet 10 of 11

69

D1 MBR5020L ADDR[2..0] 3V3_BP ADDR0 R91 100K ADDR1 ADDR2 R95 100K R98 100K MODULE_RESET# GND SYSTEM_RESET#1 GND SYSTEM_RESET#2 I2C_SDA I2C_SCL DBG_TMS R99 100K R100 100K R96 100K R97 100K C220 100N R87 10K DBG_TDO R88 10K DBG_TDI DBG_TCK R92 100K R93 100K R94 100K 3V_I2C

MR WDI
GND U131

1 8

C209 TPS3823 100N I2C_SCL I2C_SDA

EN SCLA SDAA Gnd

C210 100N

Vcca Vccb

PCA9517

70
5 4 3 2 1

I2C Bus Pull-up

3V3_A 3V3_BP D2 MBR5020L 3V3_B

DEBUG Pull-up

ADDR Pull-down

RESET Pull-up

Backplane Reset Monitor

3V_I2C U129A 3V3_BP

Backplane I2C Isolation

Control signals Pull-up

3V3_BP

Appendix A. Backplane

SYSTEM_RESET#1

1
3V3_BP

C221

4 2 3 4 VDD
R101 10K R102 10K U130

SYSTEM_RESET#2

5
100N BP_RESET# BP_I2C_EN

R103 100K

R104 100K

R105 100K

R106 100K

R107 100K

ADDR0

2 GND 5 2 3 SCLB SDAB 7 6 RESET

SET# I2C_SCL_BP I2C_SDA_BP ACK# BUS_EN# PWR_EN# PWR_FLAG

GND 3V3_BP U129B

VCC
GND C211 100N 3V3_BP 3V3_BP

3
74LVC1G08

GND

3V3_BP

3V3_BP

GND R108 100K ID10 ID11 ID12 ID1[2..0] 3V3_BP ID3[2..0] 3V3_BP ID30 ID31 ID32 ID5[2..0] 3V3_BP 3V3_BP R109 100K R110 100K R111 100K R112 100K R113 100K ID50 ID51 ID52 ID7[2..0] R114 100K R115 100K R116 100K ID70 ID71 ID72 R117 100K R118 100K R119 100K
B

R120 100K ID20 ID21 ID22 ID2[2..0]

R121 100K

R122 100K ID40 ID41 ID42 ID4[2..0]

R123 100K

R124 100K

R125 100K ID60 ID61 ID62 ID6[2..0]

R126 100K

R127 100K

R128 100K ID80 ID81 ID82 ID8[2..0]

Figure A.11: Backplane schematic, page 11.

/ TOP
Schematic Title Page Title
Designed: Approved:

R129 100K

R130 100K

R131 100K

NUTS Backplane
Backplane Logic & Pull-ups
<OrgAddr1>
Size BOM Doc No:

Pull-ups on all ID lines

<OrgAddr2>
A3 <Cage Code>
Design Created Date: Friday, February 18, 2011

Document number

Revision

<Doc>
Sheet Created Date Friday, March 11, 2011
4 3 2

A00
Sheet Modified Date Sunday, March 20, 2011
1

Sheet 11 of

11

Appendix B On-Board Controller

The source drawings for the hardware of the design is located in this section.

71

I2C_SCL I2C_SDA 1 4 Vcc Vcc

U5
1 3 2 10 21 48 64 81 103 130 141

RESET TMS TDO TCK TDI

RF_CS RF_SCK RF_MISO RF_MOSI

9 6 8 7 CS SCK MISO MOSI

U1 C16
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO 100nF 100nF DBG_TMS DBG_TDO

C17
USB_VBUS USB_VBIAS

118

142 143

RF-MODULE

VBUS VBIAS

Gnd Gnd

BP_I2C_EN BUS_EN PWR_EN MODULE_ADDR0 MODULE_ADDR1 MODULE_ADDR2 2 3

I2C_SCL I2C_SDA MODULE_RESET DBG_TMS DBG_TDO DBG_TCK DBG_TDI SYSTEM_RESET RF_RESET CONN-DIL36 DBG_TDI SYSTEM_RESET DBG_TCK MODULE_ADDR2 BUS_EN SET INHIBIT USB_EN ACK PWR_EN MODULE_ADDR0 VCC VCC VDDANA RF_SCK MODULE_ADDR1

VDDCORE

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 5 10 PROG RESET VDDANA VDDIN VDDIN ID0 ID0 ID1 ID1 ID2 ID2 SET ACK PWR_FLAG

R13
BC857 82k C LED-SMD 10pF 470pF NP0 2.2uF X7R 1nF NP0 4.7uF X7R 6810 +/- 1% A VBIAS

DMFS DPFS

DMHS DPHS

GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO

GNDCORE

GNDANA

GNDPLL

8 9

5 6

4 7 20 47 65 82 102 131

140

117

SET BUS_EN PWR_EN MODULE_ADDR0 MODULE_ADDR1 MODULE_ADDR2 INHIBIT USB_EN CONN-DIL16

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

FSDM FSDP

8
CONN-USB-MINI VCC VBUS 2 2

J1 J3
SHIELD MODULE_RESET 4 1 ID

HSDM HSDP

144

VBUS DD+ GND 1 2 3 5

R4 D2
PESD0603-240 1 39

12.5pF FSDP

6/7/8/9

72
A
VCC VCC

0
VCC VCC

J2

VDDCORE VDDANA VCC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36

I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

L1
BLM21AG102SN1D RF_RESET

R5
ACK 82k VCC I2C_SDA I2C_SCL BC857 100nF

Appendix B. On-Board Controller

Q1

C26

R7
VDDCORE VCC 120

122 123 15 125 126 124 127 133 137 139 138 136 132 129 100 101 128 116 115 114 113 109 110 111 112 119 120 26 28 23 14 29 PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31

Q2 D3 C15 C3 C4 C5 C6 R11

PWR_FLAG

5
120

R6

MODULE_RESET BP_I2C_EN PWR_FLAG RF_MISO RF_CS RF_MOSI

NWR NRD NCS1 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 I/O15 I/O14 I/O13 I/O12 I/O11 NAND_WP NOR_RP 30 27 25 24 22 121 134 135 11 17 16 31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 NOR_WP

VCC

D4
LED-SMD

XIN32 XOUT32 XIN0 XOUT0

NANDOE ADDR23

C7
100nF 100nF 100nF 100nF 100nF

C8

C9

C10

C11

C12
100nF

C13
100nF

C14
100nF RESET TMS TDO TCK TDI

98 99 18 19 13 12 106 104 105 107 108

PC00 PC01 PC02 PC03 PC04 PC05 RESET_N TMS TDO TCK TDI

J4

PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 PX25 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 AT32UC3A3

55 59 62 63 60 58 53 54 50 49 37 67 34 33 68 40 32 83 84 35 73 80 72 85 86 92 90 89 91 94 96 97 93 95 61 38 44 45 51 52 36 71 69 88 66 70 74 39 41 43 75 77 87 42 46 79 78 76 57 56

NCS3 NCS2 NWAIT ADDR22 ADDR21 ADDR20 NCS0 NANDWE

R3
FSDM 39 HSDM HSDP

C24
XIN32

C22
XIN0 18pF

Figure B.1: On-Board Controller schematic, page 1.

D1
PESD0603-240

DBG_TCK DBG_TDO DBG_TMS

X2 C25
12.5pF CRYSTAL XOUT32 18pF

X1 C23
ABM8G-16 XOUT0

FILE NAME: DESIGN TITLE:

obc.DSN OBC
BY: <NONE> REV: <NONE>

DATE:

9
CONN-HEAD-05X2

DBG_TDI

1 3 5 7 9

2 4 6 8 10

19.06.2011

9
PAGE: and Controller PATH: Connectors C:\Users\Tablet\Dropbox\Skole\Master\Rapport\CD\On-Board Contro 1 of 2 TIME: 13:06:00

VCC VCC

12 36

1
VDD VDD

U2 C1
1nF

C21
1nF

2
VCC

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

8 9 10 11 14 15 16 17 32 33 34 35 38 39 40 41

R2
10k

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

3
NCS1 NRD NWR

ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 GND GND VCC CE OE WE UB LB 7 44 18 43 42 IS61WV102416BLL 13 37

5 4 3 2 1 48 47 46 45 30 29 28 27 26 25 24 23 22 21 20 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

R10
10k

VPP VCC

9 8

U4

VCC

O0 O1 O2 O3 O4 O5 O6 O7

21 22 23 25 26 27 28 29 I/O0 I/O1VCC I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

R9
VCC VCC VCC 10k 100nF

C20
NCS0

CE OE 12 37 10k 9 10 CE CE2 ALE CLE RE WE 7 6 19 R/B R/B2 GND GND WP ADDR22 ADDR21 NANDOE NANDWE NWAIT 8 18 17 16 10k GND 32 NRD

30

R8

R12 U3
VCC

6
NCS2 NCS3 AT27LV040A VCC VCC

ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 24

20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 6 7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18

C18
100nF

C19
100nF

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

29 30 31 32 41 42 43 44

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

NAND_WP

13 36

C2
100nF

R1
10k

MT29F16G08DAAWP

Figure B.2: On-Board Controller schematic, page 2.

FILE NAME: DESIGN TITLE: PATH: BY:

obc.DSN OBC
<NONE> REV: <NONE>

DATE:

19.06.2011

9
PAGE: Memories C:\Users\Tablet\Dropbox\Skole\Master\Rapport\CD\On-Board Contro 2 of 2 TIME: 13:06:00

73

74

Appendix C Wireless Internal Communication Module

The source drawings for the hardware of the design is located in this section.

75

3.9nH 1.5pF

L1
2 7 18 21

VDD VDD VDD VDD

J3
NRF24LE1D 25 6 17 20 22k

VSS VSS VSS VSS

P0.0

P0.1

76
A1
ANCV12G44SAA127 VCC

L2

C1

C2
1.0pF

VCC

U1

8.2nH

L3
2.7nH

R3
10k XC1 XC2 DEC2 DEC1 IREF 19 4 3 23 22

ANT2 ANT1 VDD_PA

16 15 14

C4
ABM8H-16.000MHZ-B4Y-T 2.2nF

C3
4.7pF

RESET PROG

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 RESET PROG 13 5 RESET PROG

24 1 8 9 10 11 12 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6

X2 C6
100nF

R2
10k

R1

C5
33nF

C8
18pF ABM8G-16

C7
18pF

1 2 3 4 5 6 PROG P0.2 P0.3 P0.4 P0.5 RESET CONN-SIL6

VCC VCC

Appendix C. Wireless Internal Communication Module

J2
2 1 CONN-SIL2 VCC VCC

X1
CRYSTAL 1 2

C11
1nF FC-13F, 32.768kHz, 12.5pF

C9
10pF

C10
10pF

J1
1 2 CONN-SIL2

C12
100nF

Figure C.1: Intra-satellite Communication Module schematic.