Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

EXPERIMENT NO. 1 LINEAR WAVE SHAPING AIM: To observe the response of RC Low pass circuit and RC High pass circuit for a square wave input for different time constants. i) RC>>T ii) RC = T iii) RC<<T and to determine rise time for RC<<T. iv)To determine the ti!t for RC>>T in High pass fi!ter. APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. Component E!"#pment Resistors Capacitor +read +oard. CR(unction 3enerator Connecting 5ires. R$n%e Qt&. "## $% " #."'()#.#"uf)#.##"uf " " ."H/0 &#1H/) " ."H/0"1H/) "

CIRCUIT DIAGRAM:
100n 10Vp-p,1KHz square input + V0

100k

Vi

(igure6 ". RC High 7ass Circuit.

V0 10Vp-p,1KHz square input Vi 100k C1 100n +

(igure &6 RC Low 7ass Circuit.

1

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

THEOR': LINEAR WAVE SHAPING: 8 non0sinusoida! signa! is a!tered b9 transmission the signa! through a !inear networ$ is ca!!ed :"I$E%& '%VE ()% I$*+, $( RC H#%) P$** C#+,"#t: The Capacitor in series arm and resistor in the shunt arm) the resu!ting circuit is ca!!ed High pass circuit. The circuit passes high frequencies readi!9 but attenuates !ow frequencies because the reactance of the capacitor decreases with increasing frequenc9. This circuit wor$s as a differentia! circuit. 8 circuit in which the output vo!tage is proportiona! to the derivative of the input vo!tage is $nown as differentia! circuit. The condition for differentia! circuit is RC va!ue must be much sma!!er than the time period of the input wave -&!..T/. -( RC Lo. P$** C#+,"#t : The resistor in series arm and capacitor in the shunt arm) the resu!ting circuit is ca!!ed Low pass circuit. The circuit passes !ow frequencies readi!9 but attenuates high frequencies because the reactance of the capacitor decreases with increasing frequenc9. This circuit a!so wor$s as integrating circuit. 8 circuit in which the output vo!tage is proportiona! to the integra! of the input vo!tage is $nown as integrating circuit. The condition for integrating circuit is RC va!ue must be much greater than the time period of the input wave .RC>>T). De*#%n R, H#%) p$** C#+,"#t: .i) Long time constant6RC>>T) where RC is the time constant) T is the time period of the input signa!. Let RC="#T)choose R="##;%)f=";H/. C="#<"#*="##="#*=#."'f .ii) 1edium time constant6 RC=T C=T<R="<"#*="##="#*=#.#"'f .iii) >hort time constant6 RC<<T
2

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RC=T<"# C=T<"#R="<"#="#*="##="#*=#.##"'f RC lo. p$** ,#+,"#t:/ De*#%n p+o,e0"+e #* *$me $* RC )#%) p$** ,#+,"#t( .i) .ii) .iii) Long time constant6RC>>T) C=#."'f 1edium time constant6 RC=T)C=#.#" 'f >hort time constant6 RC<<T)C=#.##" 'f V44 1V4.e2T4 RC V12V411V
7 ti!t 0 1 - V1 2 V1/ 3 - V 3 2 / 4 100

V111V1.e2T1 RC3 V112V41V3

PROCEDURE: ". Connect the circuit as shown in the figure" ?&. &. Connect the function generator at the input termina!s and CR- at the output termina!s of the circuit. *. 8pp!9 a square wave signa! of frequenc9 ";H/ at the input. .T = " msec.) and amp!itude "#@p0p. ,. -bserve the output waveform of the circuit for different time constants. 2. Ca!cu!ate the rise time for !ow pass fi!ter and ti!t for high pass fi!ter and compare with the theoretica! va!ues.
4. (or !ow pass fi!ter se!ect rise time .t r) = &.& RC .theoretica!). The rise time is defined as the time ta$en b9 the output vo!tage to rise from #." to #.A of its fina! va!ue. B. ti!t = - T32&! / 100 . theoretica!))7 ti!t 0 1 - V1 2 V1/ 3 - V 3 2 / 4 100 . practica!)

EXPECTED GRAPH /#(H#%) P$** RC C#+,"#t /#(RC1T

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

/##(RC55T

RC16.1T

/###(RC77T

RC116T

/##( Lo. P$** RC C#+,"#t /#( RC1T

/##(

RC55T
4

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RC77T

RECORD O8 O9SERVATIONS: HPRC C#+,"#t

Practical Tilt V1-V11 V/2

case

V1

V1

Theoretic al Tilt

RC<<T RC= T RC>>T

100K 100K 100k

0.001F 0.01 F 0.1 F

LPRC C#+,"#t:

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory Risetime R C T Theoretical 2.2RC !

2013-14
Risetime Practical "rom 0.1V to 0.# V!

Case

RC<< T RC=T RC>>T

100K 100K 100k

0.001F 0.01 F 0.1 F

PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. RESULT: The response of RC High pass and Low pass fi!ter circuits for square wave input is observed) rise time and ti!t has been ca!cu!ated. VIVA QUESTIONS:
". 5hen H70RC circuit is used as CifferentiatorD &. Craw the responses of L7( to step) pu!se) ramp inputsD *. Cefine ti!t and rise timeD

,. 5hen L70RC circuit is used as integratorD 2. 5h9 noise immunit9 is more in integrator than differentiatorD 4. 5h9 H7( b!oc$s the CC signa!D B. 5hat is meant b9 !inear wave shapingD E. Cefine time constantD A. Craw the responses of H7( to step) pu!se) ramp inputsD "#. Cifferences between High pass and Low pass RC circuits

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

EXPERIMENT NO. 4 NON LINEAR WAVE SHAPING : CLIPPERS AIM: To stud9 the c!ipping circuits for different reference vo!tages and to verif9 the responses.

APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. B. Component E!"#pment Resistors Ciode +read board CR(unction 3enerator 7ower supp!9 Connecting wires. R$n%e &.&;% "F,##B ."H/0 &#1H/) ."H/0"1H/) .#0*#@) Qt&. " & " " " "

CIRCUIT DIAGRAM: /#(Se+#e* Cl#ppe+

a) 7ositive C!ipper with /ero reference

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

b) Fegative c!ipper with /ero reference

c)positive c!ipper with positive reference

d)Fegative c!ipper with positive reference

/##(S)"nt Cl#ppe+
8

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

a)positive clipper with zero reference

b) negative clipper with zero reference

c)positive c!ipper with positive reference

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

d)Fegative c!ipper with positive reference

2.2k 1N4007 V2 V2 V0

10Vp-p,1KHz sine w ave

e)c!ipping of two independent !eve!s

f)c!ipping at two independent !eve!s THEOR': C!ipping means removing the se!ected portion of input signa!. Gt is a!so referred as vo!tage !imiters) current !imiters) amp!itude se!ectors or s!icers.
10

Vi

1N4007

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

There are three different t9pes of c!ipping circuits. ") 7ositive C!ipping circuit. &) Fegative C!ipping. *) +iased C!ipping .s!icer). Gn positive c!ipping circuit positive c9c!e of input signa! is c!ipped and negative portion of input signa! is obtained in the output based on the reference vo!tage. Gn negative c!ipping circuit instead of positive portion of input signa!) negative portion is c!ipped. Gn s!icer or biased both positive and negative portions of the input signa! are c!ipped. 5e can ta$e sinusoida!) square and triangu!ar as input signa!s. Gn our e=periment we use sinusoida! as input signa!. Appl#,$t#on*: ". C!ippers especia!!9 used in T.@. Receivers. &. 8!! communication s9stems where ever transmission and reception is present.

PROCEDURE: ". Connect the circuit as shown in fig. &. Gn each case app!9 "# @707) " ;H/ >ine wave G<7 using a signa! generator. *. -bserve the -<7 waveform on the CR- and compare with G<7 waveform. ,. Fote the changes in the -<7 due to variations in the reference vo!tage @r=&@. 2. >$etch the G<7 and -<7 waveforms. 4. Repeat the above steps for a!! the circuits. PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 are to be set at /ero position. RESULT: The different t9pes of c!ippers circuits are studied and observed the response for various combinations of @r and c!ipping diodes.
11

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

VIVA QUESTIONS: ". Cefine non !inear wave shappingD &. Cefine c!ipping circuitsD *. 5hat is piece wise !inear mode of a diodeD ,. what are the different t9pes of c!ippersD 2. 5hich $ind of a c!ipper is ca!!ed a s!icer circuitD 4. 5hat are the disadvantages of the shunt c!ipperD B. 5hat are the disadvantages of the series c!ipperD E. 5hat considerations are ta$en into account whi!e designing c!ipping circuitsD

EXPERIMENT NO. ; NON LINEAR WAVE SHAPING : CLAMPERS

12

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

AIM: To stud9 the c!amping circuits for different reference vo!tages and to verif9 the responses, APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. B. Component E!"#pment Resistor Capacitor Ciode +read board (unction 3enerator CR7ower supp!9 R$n%e "##$% #."'( "F,##B " H/0"1H/ #0&#1H/ #0*#@ Qt&. " " " " " " "

CIRCUIT DIAGRAM:

a)7ositive c!amping with /ero reference vo!tage

13

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

b)Fegative c!amping with /ero reference vo!tage

c)positive c!amping with positive reference vo!tage

d)positive c!amping with negative reference vo!tage

14

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

e)negative c!amping with negative reference vo!tage

f)negative c!amping with positive reference vo!tage THEOR': 8 c!amping circuit .a!so $nown as a c!amper) wi!! bind the upper or !ower e=treme of a waveform to a fi=ed CC vo!tage !eve!. These circuits are a!so $nown as d.c. vo!tage restorers or d.c. inserters. C!ampers can be constructed in both positive and negative po!arities. There are various t9pes of C!amping circuits) which are mentioned be!ow6 ". 7ositive C!amping Circuit. &. Fegative C!amping Circuit. *. 7ositive C!amping with positive reference vo!tage. ,. Fegative C!amping with positive reference vo!tage. 2. 7ositive C!amping with negative reference vo!tage. 4. Fegative C!amping with negative reference vo!tage. Ne%$t#<e Cl$mp#n% C#+,"#t:
15

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

Gt is a!so termed as positive pea$ c!amper) since the circuit c!amps the positive pea$ of a signa! to /ero !eve!. >o) this t9pe of c!amper introduces a negative d.c. va!ue. Thus) we ca!!ed it as negative c!amp. Po*#t#<e Cl$mp#n% C#+,"#t: Gt is a!so ca!!ed as negative pea$ c!amper) because this circuit c!amps at the negative 7ea$s of a signa!. >ince the circuit c!amps the negative pea$ of a signa! to /ero !eve!. >o) this t9pe of c!amper introduces a positive d.c. va!ue. Thus) we ca!!ed it as positive c!amp. Fegative C!amping with 7ositive Reference @o!tage6 >ince V& is in series with the output of negative c!amping circuit) now the average va!ue of the output becomes --Vm 5 V& /. >imi!ar!9) i) Fegative c!amping with negative reference vo!tage is --Vm 5 V& /. ii) 7ositive c!amping is HVm. iii) 7ositive c!amping with positive reference vo!tage is Vm 5 V&. iv) 7ositive c!amping with negative reference vo!tage is Vm - V&. PROCEDURE: ". Connect the circuit as shown in the figure. &. Connect the function generator at the input termina!s and CR- at the output termina!s of the circuit. *. 8pp!9 a sine wave greater than the reference vo!tage) and signa! of frequenc9 " $H/ and "#@p0p amp!itude at the input and observe the output waveforms of the circuits in CR-. ,. Repeat the above procedure for the different c!amping circuits . PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 are to be set at /ero position.

RESULT:

16

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

Fon Linear wave shaping .C!ampers) characteristics are >tudied and observed the response. VIVA QUESTIONS: ".what are the app!ications of c!amping circuitsD &. 5hat is the s9nchroni/ed c!ampingD
*. 5h9 is a c!amper ca!!ed a dc inserterD ,. 5hat is c!amping circuit theorem. How does the modified c!amping circuit theorem differs from this 2.Cifferentiate Ive c!amping circuit from Hve c!amping circuits in the above circuits

4. . Cescribe the charging and discharging of a capacitor in each circuitD

B. 5hat is the function of capacitorD E. 5hat are the effects of diode characteristics on the output of the C!amperD

EXPERIMENT NO.= TRANSISTOR ACTS AS A SWITCH

17

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

AIM: To design and observe the performance of a transistor as a switch. APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. B. E. Component E!"#pment Resistors Transistor +read board (unction generator CR7ower supp!9 CR- 7robes Connecting 5ires R$n%e "E#$%)"&$% +C "#B "H/0 "1H/ "H/ 0&#1H/ #0*#@ Qt&. " " " " " "

CIRCUIT DIAGRAM:

V 12

12k

V0

180k BC107 V, KHz square w ave + Vi

THEOR':
18

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

(ig.". Transistor as a switch. (ig.& 7in configuration of transistor &F&*4A. (ig.* -utput characteristics with !oad !ine .d.c) The transistor 6 can be used as a switch to connect and disconnect the !oad &" from the source V!!. 5hen a transistor is saturated) it is !i$e a c!osed switch from the co!!ector to the emitter. 5hen a transistor is cut0off) it is !i$e an open switch. 5hen no current f!ows in the !oad circuit then the transistor acts !i$e a open switch. Gt can be shown that both emitter0base Junction and co!!ector0base Junction remain reverse biased. Thus this is ca!!ed as cut0off region. Transistor conducts heavi!9) Just !i$e a c!osed switch. >o) both emitter0base and co!!ector0 base Junction remain forward biased. Thus this is ca!!ed as saturation region. The region between cut0off and saturation is termed as active region. >o) emitter0base Junction remains in forward bias and co!!ector0base Junction in reverse bias is ca!!ed active region. 5hen transistor ma$es a transition from its cut off state) to the saturation state or -F state it ta$es a finite time to do so. Gt ta$es the finite time for the reserve transition from the -F to -(( state.

Del$& T#me:
19

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

This time is ta$en during turn -F. Gt is the time duration form the point when the input pu!se at base of the transistor reaches "# of its ma=imum amp!itude) to the point when the co!!ector current charges from # to "# of its ma=imum amp!itude. R#*e T#me: This time is a!so ta$en during turn -FK it is the time interva! in which the co!!ector current pu!se changes from "# to A# of its ma=imum va!ve. Sto+$%e T#me: The time interva! during turn off transition of the transistor is between the points when the input pu!se at the base changes to "# of its ma=imum amp!itude) to the point when the co!!ector current changes from "## to A# of co!!ector current. 8$ll T#me: "# The time interva! at turn off during which the co!!ector current decreases from A# of its ma=imum amp!itude is the fa!! time. to

PROCEDURE: ") Construct the circuit as per the circuit diagram. &) 8pp!9 a 2@p0p) 2 ;H/ square wave input and monitor both input and output waveforms on C.R.-. *) >$etch the input and output waveforms) carefu!!9 noting the precise output amp!itudes with respect to ground. ,) 1easure and record the rise and fa!! times of both input and output and a!so measure and record the de!a9 time and the storage time.

EXPECTED GRAPH:
20

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. RESULT: >witching characteristics of transistor is studied and determined the fa!! time) rise time) storage time and de!a9 time.

21

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

VIVA QUESTIONS:
". Cifferentiate between Ciode and Transistor as a switchD &. Cefine -F time) -(( time of the transistorD *. Gn which regions Transistor acts as a switchD ,. L=p!ain phenomenon of M!atching Min a Transistor switchD 2. Cefine Rise time ? fa!! time of a transistor switchD 4. Cefine >torage timeD B. Cefine turn -F time of a transistorD E. Cefine turn -(( time of a transistorD A. Cefine de!a9 timeD "#. 1ention the t9pica! va!ues for @be and @ce.sat) for 3e and >iD

EXPERIMENT NO. > STUD' O8 LOGIC GATES AIM: To stud9 the various !ogic gates b9 using discrete components and verif9 truth tab!es.
22

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

APPARATUS REQUIRED: Sl.no. ". &. *. , 2. 4. B. CIRCUIT DIAGRAM: Component Resistors Ciodes Transistor 7ower supp!9 +read board Connecting wires 1u!timeter R$n%e "##%) "$%0") "#$ %0" GF,##B +C "#B #0*#@ Qt&. & & &

(igure "

(igure &

(igure *

(igure ,

23

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

F-T 38TL (igure 2 THEOR': AND GATE: 8n 8FC gate has two inputs but on!9 one output signa!. Gt has high output when a!! the inputs are high.

OR GATE: 8n -R gate has two inputs but on!9 one output signa!. Gt has high output if an9 or a!! the inputs are high.

NOR GATE:
24

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

F-R gate is referred to a F-T -R gate , Read this as N= F-T .8 -R +). The on!9 to get high output is to have both inputs !ow. NAND GATE:

F8FC gate is referred to as F-T 8FC 38TL read this as N = F-T 8 8FC + or N = Comp!iment of 8 8FC +. +9 this gate the output is !ow when a!! the inputs are high. NOT GATE:

The Gnverter or F-T gate is with on!9 one input and on!9 one output. Gt is ca!!ed inverter because the output is a!wa9s opposite to the input.

PROCEDURE:
25

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

". Connect the circuit as shown in figure " &. 8pp!9 O#@P to !ogic O#P and 2@ to !ogic O"P using power supp!9. *. @erif9 the truth tab!es of various gates for different conditions of inputs. ,. Repeat the steps "?& for figures &) *) , ? 2. TRUTH TA9LES:

PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. RESULT: The theoretica! and practica! va!ues of the truth tab!e for the given !ogic gates is verified. VIVA QUESTIONS:
". 5h9 F8FC ? F-R gates are ca!!ed universa! gatesD &. Rea!i/e the LQ I -R gates using minimum number of F8FC gates. *. 3ive the truth tab!e for LQ0F-R .LQ0-RHF-T) and rea!i/e using F8FC gates ,. L=p!ain the operation of F8FC gate when rea!i/ed using discrete components 2. 5hat are the !ogic !ow and High !eve!s of TTL GCOs and C1-> GCOs. 4. Compare TTL !ogic fami!9 with C1-> fami!9. B. 5hich !ogic fami!9 is ca!!ed fastest and which !ogic fami!9 is ca!!ed !ow power dissipated E. L=p!ain the operation of -R) F-R gates when rea!i/ed using discrete Components A. 5h9 the transistor operates as F-T gate "#. Gn what regions does the transistor is operated such that it behaves !i$e a switch.

EXPERIMENT NO.?
26

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

STUD' O8 8LIP28LOPS

AIM: To verif9 the truth tab!e of >R (!ip0(!op) R0; f!ip0f!op) T f!ip0f!op and C f!ip0f!op. APPARATUS REQUIRED: ". (!ip0(!op Trainer $it. &. Connecting wires. CIRCUIT DIAGRAMS:

@ 2 A 8l#p 8lop

27

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

T2 8l#p 8lop

D : 8l#p 8lop

THEOR'6 (!ip0(!ops are bistab!e e!ements. These are the basic bui!ding b!oc$s of most sequentia! circuits. (!ip0f!op for a sequentia! device that norma!!9 samp!es its inputs and changes its outputs on!9 at times determined b9 c!oc$ing signa!. SR 8LIP28LOP: (ig. shows the timing diagram for an >R f!ip0f!op. 5hen both > and R are high so) the output S togg!e .S ?SP in same state). Thus we use c!oc$ed >R f!ip0f!op.

(ig. Logic s9mbo! for R> (LG70(L-7 CLOCKED RS FLIP-FLOP (RST FLIP-FLOP): 5e $now that the f!ip0f!ops are s9nchronous bistab!e devices. The term s9nchronous indicates that the output changes its state on!9 at a specified point on a triggering input ca!!ed the Oc!oc$PK i.e. changes in the output occur in s9nchroni/ation with the c!oc$.

(ig. Logic s9mbo! for c!oc$ed R> (LG70(L-7

28

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

D (DELAY) FLIP-FLOP: The C .Ce!a9) f!ip0f!op is used for storing the information. Gt is basica!!9 an R> f!ip0f!op with an inverter in the R input. (ig. shows a c!oc$ed C f!ip0f!op. The C f!ip0f!op is often ca!!ed a Ode!a9 f!ip0f!opP. The word Ode!a9P describes what happens to the data or information at input C. Gn other words) the data) i.e. # or " at the input C is de!a9ed b9 one c!oc$ pu!se from getting to output S.

1odification of c!oc$ed R> (!ip0(!op into C (!ip0(!op

T+"t) T$-le

JK FLIP-FLOP:
29

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

The R; f!ip0f!op has the features of a!! other f!ip0f!ops) and hence it can a!so be considered as OTniversa!P f!ip0f!op. This R; f!ip0f!op is a refinement of the R> f!ip0f!op. The indeterminate state .when R=>=") of the R> t9pe is defined in the R; t9pe. Gn that condition the state of the output is changedK i.e. the comp!ement of the previous state is avai!ab!e. Gn other words) if the previous state of the output S is #K it becomes "K and vice versa. (ig. shows the !ogic s9mbo! for R; f!ip0f!op and itPs truth tab!e.

Logic >9mbo!

Truth Tab!e T /TOGGLE( 8LIP28LOP: The sing!e input version of the R; f!ip0f!op is OT .togg!e) f!ip0f!opP and it is obtained from a R; f!ip0f!op if both inputs are connected together. The name T comes from the abi!it9 of the f!ip0f!op to Otogg!eP or change the state. (ig ". >hows the !ogic diagram of a c!oc$ed T f!ip0f!op which has on!9 one input referred to as T input.

30

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

(ig ".Logic

Truth tab!e

PROCEDURE: ". Connect the circuit diagram as shown in the diagram. &. @erif9 the truth tab!e of the >R !atch. *. Connect the R; f!ip0f!op circuit using *0input F8FC gates and verif9 the truth tab!e. ,. @erif9 the truth tab!e for T and C (!ip0f!ops. PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. RESULT: Theoretica! and practica! va!ues of the truth tab!es for the given !ogic gates are verified. VIVA QUESTIONS: ". Cifference between !atch and f!ip0f!op &. List the app!ications of f!ip0f!ops. *. L=p!ain the operation of R; master s!ave f!ip0f!op ,. 5hat is the difference between >R0f!ip f!op and c!oc$ed >R0((. 2. 5hat is meant b9 !eve! triggering and edge triggering in f!ip0f!ops. 4. L=p!ain the difference between Hve edge and Ive edge triggering B. 5hich t9pe of edge triggering is used in GC B,B4 R0; 1<> (!ip0f!opD E. L=p!ain the preset and c!ear inputs of a f!ip0f!op and wh9 are these Ca!!ed as9nchronous Gnputs A. 5hat is meant b9 togg!e and where do the T0((Os are used "#. 5here do the C0((Os are used and wh9 it is ca!!ed a de!a9 f!ip f!op
31

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

EXPERIMENT NO. B 9ISTA9LE MULTIVI9RATOR AIM: To stud9 and verif9 the output wave form of a +istab!e 1u!tivibrator. APPARATUS: Sl.no. ". &. *. ,. 2. 4. B. E. A. E!"#pment R$n%e Qt&. " " & & & & "

CR"H/ 0&#1H/ (untion generator "H/0"1H/ Resistors ,B#ohm)**$)"#$)"&#$ Capacitors "#nf)"nf Ciodes "F,##B Transistors +C"#B 7ower >upp!9 #0*#@ CR- probes Connecting wires

CIRCUIT DIAGRAM:

"1 470

10k

1n "4 ##k

10n $1 1N4007 VC1 !1 BC107

"# ##k VC2

$2 1N4007

" 10k

1n

"2 470

10n

!2 BC107 "% 120k "7 120k

Vi Vp-p,1KHz

square w ave,tri&&er pu'se

32

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

THEOR': A -#*t$-le m"lt#<#-+$to+ )$* t.o *t$-le o"tp"t *t$te*. Gt can remain indefinite!9 in an9 one of the two stab!e states) and it can be induced to ma$e an abrupt transition to the other stab!e state b9 means of suitab!e e=terna! e=citation. Gt wou!d remain indefinite!9 in this stab!e state) unti! it is again induced to switch into the origina! stab!e state b9 e=terna! triggering. +istab!e mu!tivibrators are a!so termed as O+inar9Ps or (!ip0f!opsP. (igure shows the circuit of a bistab!e mu!tivibrator using two F7F transistors. Here the output of a transistor S& is coup!ed put of a transistor S" through a resistor R&. >imi!ar!9) the output of a transistor S" is coup!ed to the base of transistor S & through a resistor R". The capacitors C& and C" are $nown as speed up capacitors. Their function is to increase the speed of the circuit in ma$ing abrupt transition from one stab!e state to another stab!e state. The base resistors .R* and R,) of both the transistors are connected to a common source .0@ ++). The output of a bistab!e mu!tivibrator is avai!ab!e at the co!!ector termina! of the both the transistor S " and S&. However) the two outputs are the comp!ements of each other. Let us suppose) if S" is conducting) then the fact that point 8 is at near!9 -F ma$es the base of S& negative .b9 the potentia! divider R& 0 R,) and ho!ds S& off. >imi!ar!9 with S& -(() the potentia! divider from @CC to 0@++ .RL&) R") R*) is designed to $eep base of S" at about #.B@ ensuring that S" conducts. Gt is seen that S" ho!ds S& -(( and S& ho!d S" -F. >uppose) now a positive pu!se is app!ied momentari!9 to R. Gt wi!! cause S & to conduct. 8s co!!ector of S& fa!!s to /ero) it cuts S" -(( and consequent!9) the +1@ switches over to its other state. PROCEDURE: ". Ta$e a bread board and connect the components as per circuit diagram. &. 8pp!9 the square wave input 2@p0p and ";H/ frequenc9 from the function generator. *. 8pp!9 the supp!9 vo!tage @CC = H 2 @ and connect CR- at the base of S". ,. Fote down the wave forms time period and amp!itude of wave form at the base of S". 2. Repeat the same procedure to note down the wave forms at base of S&. 4. >imi!ar!9 note down the wave forms at @C" ? @C& of S" ? S& respective!9. B. Fote down the @+L .>at) and .@CL .>at) vo!tages. E. Craw the wave forms on a graph. EXPECTED GRAPH:
33

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RECORD O9SERVATIONS: 817LGTGCL 8FC TG1L 7LRG-C -( @C") @+") @C&) @+& PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. ,. Gncrease the power supp!9 s!ow!9. 2. 8fter note down the readings switch off the power supp!9. RESULT: The operation of +istab!e mu!tivibrator is observed and the output waveforms are p!otted. VIVA QUESTIONS: 1. 4. ;. =. >. ?. B. C.
5hat are the app!ications of a +itab!e 1u!tivibratorD Cescribe the operation of commutating capacitorsD 5h9 is a +inar9 a!so ca!!ed a f!ip0f!opD 1ention the name of different $inds of triggering used in the circuit shownD 5hat are the disadvantages of direct coup!ed +inar9D How man9 t9pes of uns9mmetrica! triggering are thereD 5hat are catching diodesD 5hich triggering is used in binar9 counting circuits

EXPERIMENT NO. C
34

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

MONOSTA9LE MULTIVI9RATOR AIM: To construct the transistor monostab!e 1u!tivibrator and observe the response at base and co!!ector points. APPARATUS: Sl.no. ". &. *. ,. 2. 4. B. E. A. E!"#pment CR(untion generator Resistors Capacitors Ciodes Transistors 7ower >upp!9 CR- probes Connecting wires R$n%e "H/ 0&#1H/ "H/0"1H/ "$ 24$)"##$ "##nf "F,##B +C"#B #0*#@ Qt&. " " * " * " & "

CIRCUIT DIAGRAM:
V

1k

%k

"1 1k

100n 10k

100n $1 1N4007 +

100n (utput

10Vp-p,1KHz square w ave,tri&&er input

!2 BC107

!1 BC107 100k

THEOR': The basic co!!ector coup!ed monostab!e circuit is shown in figure.

35

1k

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

STA9LE STATE: Forma!!9 S& is in the -F state. +ecause it gets a sufficient base current through R*.This causes S" to be in the -(( state as S& co!!ector which fed to the base of S" is at its !ow @cc saturation va!ue. This is fact that a negative bias app!ied at the base of S" turns it -((. This is to the stab!e state. ENTR' TO QUASI STA9LE STATE: Fow if S& is forced to become off due to !arge e=terna! trigger app!ied at its base) its co!!ector vo!tage rises sharp!9. This gives a positive vo!tage through the vo!tage divider networ$ of R" and R& at the base of S". This is sufficient to over come. The effect of its negative bias and e=ceed the cut in vo!tage of itPs +L termina! it turn -F. The circuit has now e=tended a quasi stab!e state. RETURN TO STA9LE STATE: 5hen S" turns -F) the capacitors find a convenient path to change up to @CC through R* and S". Gf the capacitor is charging ti!! the vo!tage at the base of S& e=ceeds its cut in vo!tage at this point S& turn -F again and S& turn -((. The circuit returns to its stab!e state. Curing the quasi stab!e state the vo!tage at the co!!ector of S& has a high @CC !eve!. Thus a pu!se is obtained. The width of the pu!se is given b9 T = #.4A RC.

PROCEDURE: ". Ta$e a bread board and connect the components as per circuit diagram. &. 8pp!9 the supp!9 vo!tage @CC = H "& @ and connect CR- at the base of S". *. Fote down the wave forms time period and amp!itude of wave form at the base of S". ,. Repeat the same procedure to note down the wave forms at base of S&. 2. >imi!ar!9 note down the wave forms at @C" ? @C& of S" ? S& respective!9. 4. Ca!cu!ate the Suasi stab!e time period. B. Craw the wave forms on a graph

EXPECTED GRAPH:
36

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RECORD O8 O9SERVATION: THEORITICAL: R=24;ohm) C="##nf T.-F)=#.4ARC=#.4A=24="#*="##="#0A T =*.Amsec

(="<T="<*.Amsec=#.&24;H/ PRACTICAL: Tp=

PRECAUTIONS: ". Connections shou!d be firm.

37

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

&. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. ,. Gncrease the power supp!9 s!ow!9. 2. 8fter note down the readings switch off the power supp!9 RESULT: The theoretica! and practica! va!ues of monostab!e mu!tivibrator are verified and the output waveforms are observed. VIVA QUESTIONS:
". 5hat are app!ications of 1onostab!e 1u!tivibratorD &. 5h9 is a 1onostab!e 1u!tivibrator ca!!ed a gating circuitD *. Cescribe the operation of the capacitor C* in the circuit ,. 5h9 is the time period T a!so ca!!ed Ce!a9 timeD 2. Rustif9) 5h9 1onostab!e 1u!tivibrator is ca!!ed one0shot circuitD 4. 5h9 is the Ive vo!tage given at the base of S" transistorD B. 5hat is the no of quasi ? stab!e states of 1onostab!e 1u!tivibratorD E. 5hat is meant b9 quasi stab!e stateD A. 5hat is the function of commutating capacitorsD

EXPERIMENT NO. D ASTA9LE MULTIVI9RATOR AIM:

38

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

To stud9 the behavior of astab!e mu!tivibrator and ca!cu!ate the frequenc9 of square wave generator b9 using astab!e mu!tivibrator. APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. B. E. Component E!#"pment Resistors Capacitors Transistors CR7ower supp!9 +read board CR- 7robes Connecting wires R$n%e "E#$%) &.B$% "#nf +C "#B "H/0&#1H/ #0*#@ Qt&. & & & " "

CIRCUIT DIAGRAM:

2.7k

180k

180k

10n VC1 (utput !1 BC107

10n

2.7k

VC2 (utput !2 BC107

THEOR': 8n 8stab!e 1u!tivibrator has no stab!e states. The two transistors switch a!ternate!9 between two quasi stab!e states. Fo e=terna! trigger is required to effect this change and hence is ca!!ed as free running 1u!tivibrator. RC"? RC& are the co!!ector resistors for transistors S"?S& respective!9. C"?C& are coup!ing capacitors. Resistor R"?R& provide -F state base current to the transistor T"?T& during saturation region.
39

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

OPERATION: 8t time t=#) when the power supp!9 vo!tage gets app!ied) due to s!ight mismatch Gc" f!owing through S" is !itt!e more then the co!!ector Gc& of S&. Thus rate of fa!! of @c" is more then that of @c&. so @c"< @cc wi!! ma$e the base of S& negative. This ma$e the co!!ector vo!tage @c& increase towards @cc. This increase in @c& wi!! be transferred through capacitor C& to the base of S" and increasing the condition in S". Thus when 8stab!e 1u!tivibrator is switched we have the fo!!owing conditions. S" is in saturation S& is in off region

PROCEDURE: ". Ta$e a bread board and connect the components as per circuit diagram. &. 8pp!9 the supp!9 vo!tage vcc =H2@ and connect the C.R.- at desired points to observe the wave forms. *. Fote down the wave forms time period) amp!itude from C.R.- b9 connecting it at vc") vc&) ?vb") vb& respective!9. ,. Ca!cu!ate the frequenc9 of wave forms. 2. Chec$ whether theoretica! and practica! va!ues are correct or not.

EXPECTED GRAPH:

40

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

O9SERVATIONS: THEORETICAL VALUES: R" ="E#$=R& C"=C&="#nf TG=#.4A R"C" T&=#.4AR&C& T-T8L TG1L 7LRG-C =T=".*E RC = ".*E="E#="#*="#="#0A =&.2msec (requenc9 ="<T="<&.2ms=#.,##;H/

PRACTICAL VALUES: ". Time period at S"=T"=

41

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

&. Time period at S&=T&= *. Tota! Time period T=T"HT&= ,. (requenc9="<T

PRECAUTIONS: ". Connections shou!d be firm. &. Readings are noted without para!!a= error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 set at /ero position. ,. Gncrease the power supp!9 s!ow!9. 2. 8fter note down the readings switch off the power supp!9 RESULT: The operation of 8stab!e mu!tivibrator is observed and the output waveforms are p!otted. VIVA QUESTIONS: ". 5hat are the other names of 8stab!e mu!tivibratorD &. Cefine quasi stab!e stateD *. Gs it possib!e to change time period of the waveform with out changing R ? CD ,. Co!!ector waveforms are observed with rounded edges. L=p!ainD 2. L=p!ain charging and discharging of capacitors in an 8stab!e 1u!tivibratorD 4. How can an 8stab!e mu!tivibrator be used as @C-D B. 5h9 do 9ou get overshoots in the +ase waveformsD E. 5hat are the app!ications of 8stab!e 1u!tivibratorD A. How can 8stab!e mu!tivibrator be used as a vo!tage to frequenc9 converterD "#. 5hat is the formu!a for frequenc9 of osci!!ationsD

EXPERIMENT NO. 16 SCHMITT TRIGGER AIM:

42

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

To observe the operation of >chmitt trigger and determine the va!ues of upper triggering point and !ower triggering point. APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. B. Component (unction generator Resistors Capacitors CRConnecting 5ires CR- probes 7ower >upp!9 R$n%e ."H/0"1HU) *.A$%)&.&$%) &&$% "'f ."H/0&#1H/) .#0*#@) Qt&. " & " & " "

CIRCUIT DIAGRAM:

V 12

1u

#.)k V0 (utput !2 BC107 22k 2.2k

#.)k

2.2k 1u !1 BC107 10Vp-p,1KHz input,sine w ave

THEOR': >chmitt trigger is a specia! t9pe of +istab!e 1u!tivibrator. Gt differs from the basic binar9 circuit. Gn the basic circuit there wonPt be an9 resistive coup!ing between the output of S& and the input of S". 8!though the co!!ector of S"and the base of S& are coup!ed in usua! manner.
43

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

The emitter of S" and S& are Joined) and the9 are grounded through a common resistor Rc. The base of S"is connected to a vo!tage source @i. Gt shou!d be noted that the output of a >chmitt trigger is a square wave what ever the wave form of the input signa!. PROCEDURE: ". Connections are made as for the circuit diagram. &. 8pp!9 the supp!9 vo!tage @CC = "&@ ? connect the C.R.- at output termina!s. *. 8pp!9 the input sine wave frequenc9 of ";HU and amp!itude of "#@ .707). ,. -bserve the output wave form on C.R.- ? note down the amp!itude ? time period of square wave form. 2. >$etch the waveform on graph sheet. 4. (ind out LT7 and TT7 va!ues. EXPECTED GRAPH:

RECORD O8 O9SERVATIONS: ". The time period of square waveform = &. The amp!itude of square waveform = @TT7 =
44

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

@LT7 = @H = @TT7 0 @LT7 = PRECAUTIONS: ". Connections shou!d be tight. &. +efore switch on the power supp!9 set the a!! $nobs at /ero positions. *. Gncrease the power supp!9 s!ow!9 and smooth!9. RESULT: The operation of >chmitt triggers is observed and TT7 and LT7 va!ues are ca!cu!ated. VIVA QUESTIONS: ". 5hat are the app!ications of >chmitt TriggerD &. Cefine h9steresis actionD *. 5h9 is >chmitt Trigger ca!!ed a squaring circuitD ,. 5hat is TT7 and LT7D 2. 5hat is the difference between a +inar9 and >chmitt TriggerD

EXPERIMENT NO. 11 U@T RELAXATION OSCILLATOR AIM: To construct and stud9 the operation of TniJunction transistor as a re!a=ation osci!!ator. APPARATUS:
45

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

Sl.no. ". &. *. ,. 2. 4. B. E.

Component Resistors Capacitor TRT +read board 7ower supp!9 CRCR- probes Connecting wires

R$n%e "E$%) "##$% #."'( &F&4,4 .#0*#@) ."H/0&#1H/)

Qt&. " & " " " " "

CIRCUIT DIAGRAM:

".Lmitter &. +ase" *.+ase &

THEOR': The inJunction transistor has on!9 the 70F Junction. it has a 70t9pe emitter a!!o9ed to !ight!9 doped F t9pe materia!. There are two bases) +" and +&. +ase +" being c!oser to the emitter that base +&. The 70F Junction is formed between the 70t9pe emitter and F0t9pe si!icon bar. R+" is the resistance between base +" and the emitter) and it is a basica!!9 a variab!e resistance its va!ue being dependent upon the emitter Ge. R+& is the resistance between +& and the emitter and its va!ue is fi=ed.
46

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

@p =@r H@V @p = @r H @++ @V = @++

Gt is -bvious that if @L < @7 that TRT is -(() Gf @L > @7 the TRT is -F @@ =@a!!e9 @o!tage) @7 = pea$ vo!tage.

Gt is seen that when the capacitor vo!tage @> rises to the va!ue @7 the TRT readi!9 conducts. 5hen the TRT becomes -F the capacitor discharges and its vo!tage fa!!s. 5hen the vo!tage fa!!s to the va!!e9 point @v. The TRT becomes -(( and the capacitor charges again to @p. This c9c!e of charging and discharging of the capacitor C repeats and as a resu!t a saw tooth waveform of vo!tage across C is generated. The output across C shows in figure. Ts = >weep time PROCEDURE: ". &. *. ,. 2. Ta$e bread broad and connect the component as per circuit diagram. Connect @++="&@ and connect C.R.- across capacitor :CW. Fote down the waveform and connect C R - across R+"and R+& and note down the wave forms. Ca!cu!ate the time period and chec$ whether it is equa! to the theoretica! va!ue or not. >$etch the wave forms on graph. Tr = Return time or restoration time Tv= @a!!e9 time

EXPECTED GRAPH:

47

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RECORD O8 O9SERVATIONS: =@p<@++

=E.2.practica!)<"&=#.B# T= &.*RC!og"#."<"0) =&.*="2#="#*="#="#0A=*.2msec (="<T="<*.2msec=#.&E2;H/ PRACTICAL: T= TsHTr= PRECAUTIONS: ". Connections shou!d be tight. &. Readings are noted without para!!e! error. *. +efore switch on the power supp!9 a!! the $nobs of power supp!9 shou!d set at /ero position.
48

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RESULT: The theoretica! and practica! va!ues of TRT Re!a=ation -sci!!ator are verified and output waveform is observed. VIVA QUESTIONS:
". 5hat are the various app!ications of TRTD &. 5hat is meant b9 intrinsic stand off ratioD *. 5h9 TRT is ca!!ed as negative resistance deviceD ,. 5hat are the other negative resistance devicesD 2. 5hat is a re!a=ation osci!!atorD 4. >pecifications of TRTD B. 5hat is the importance of TRTD

EXPERIMENT NO. 14 9OOT STRAP SWEEP CIRCUIT AIM:

49

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

To stud9 the wor$ing of bootstrap sweep circuit. APPARATUS REQUIRED: Sl.no. ". &. *. ,. 2. 4. B. E. A. Component R$n%e CR" HU0&#1H/ (unction generator "H/0" 1H/ Resistors ".2$%)"$%)"#$% Capacitors "'f) ,B'f Transistors +C"#B Ciode "F,##B 7ower >upp!9 .#0*#@) CR- probes Connecting wires Qt&. " " " & " & " "

CIRCUIT DIAGRAM:

V 1N4007

47u

10k

C1 1u !1 BC107 10Vp-p,1 0 t( 200 Hz input,square w ave 1u !2 BC107 V0 1k (utput

Vi

1. k

THEOR': The circuit is transistor base sweep circuit. The output sweep circuit is ramp vo!tage genera!!9 the sweep circuits are emp!o9ed to trigger the hori/onta! amp!ifier of C R TPs in C R -Ps sweep circuit is used in te!evision sweep vo!tage trigger the hori/onta! amp!ifier.
50

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

8 ramp vo!tage is obtained b9 a!!owing a constant current to f!ow through it. This is achieved b9 using the transistor as switch. 5hen a transistor is -F it ma$es to f!ow a constant current through the output capacitor. 8 capacitor and resister at the base of the transistor forms a differentiator circuit that produces spi$es at the base of the transistor. The negative spi$es ma$e the transistor is off. These resu!ts in charging the output capacitor to @cc through Rc". thus the output vo!tage ta$en across the capacitor raises e=ponentia!!9. 5hen the positive e=cursion occurs at the base) the transistor wi!! be -F. Thus the capacitor discharging through the transistor. Thus this c9c!e continues hence giving up a sweep wave form. The output waveform is "E# X out off phase of the input e=citation signa! since the transistor is in CL mode. PROCEDURE: ". Connect the components as per circuit diagram. &. Connect the @cc = H2 v) and app!9 square wave of frequenc9 "2# to &##H/ and "#v .p0p) amp!itude at the input termina!s. *. Ta$e the output in CR- across the "'f capacitor. ,. -bserve the waveform on CR2. Fote down the p0p amp!itude and time period of the output sweep wave form. 4. Craw the input and output wave forms in graph

EXPECTED GRAPH:

51

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

RECORD O8 O9SERVATION: 8mp!itude of sweep waveform6 Time period of sweep waveform6 PRECAUTIONS: ". Connections must be done carefu!!9. &. -bserve the output waveforms without para!!e! error. RESULT: The wor$ing of +ootstrap circuit is studied and >weep time and retrace time va!ues are ca!cu!ated and output waveforms are observed. VIVA QUESTIONS: ". Gs the bootstrap sweep circuit generates positive going ramp or negative going rampD &. 5hat is the appro=imate va!ue of gain in bootstrap circuitD *. 5hat is the princip!e of bootstrapD ,. 5hat is the advantage of high input resistance amp!ifier in bootstrap sweep circuitD

EXPERIMENT NO. 1; DESIGN O8 VCO USING IC >??

52

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

AIM: i) To observe the app!ications of @C-0GC 244 ii) To generate the frequenc9 modu!ated wave b9 using GC 244 APPARATUS REQUIRED: S.No E!"#pment Component N$me " GC 244 & * , 2 4 Resistors Capacitors Regu!ated power supp!9 Cathode Ra9 -sci!!oscope (unction 3enerator Spe,#E#,$t#on* V$l"e Q"$nt#t& " "#;)".2; #." u()"## p( #0*# @) " 8 #0&# 1H/ #."0" 1H/ " " " " "

CIRCUIT DIAGRAM:

T)eo+&:
53

Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

The @C- is a free running 1u!tivibrator and operates at a set frequenc9 foca!!ed free running frequenc9. This frequenc9 is determined b9 an e=terna! timing capacitor and an e=terna! resistor. Gt can a!so be shifted to either side b9 app!9ing a d.c contro! vo!tage vcto an appropriate termina! of the GC. The frequenc9 deviation is direct!9 proportiona! to the dc contro! vo!tage and hence it is ca!!ed a :vo!tage contro!!ed osci!!atorW or) in short) @C-. The output frequenc9 of the @Ccan be changed either b9 R) C" or the vo!tage @C at the modu!ating input termina! .pin 2). The vo!tage @C can be varied b9 connecting a R"R&circuit. The components R"and C"are first se!ected so that @C- output frequenc9 !ies in the centre of the operating frequenc9 range. Fow the modu!ating input vo!tage is usua!!9 varied from #.B2 @CCwhich can produce a frequenc9 variation of about "# to ". De*#%n: 1a=imum deviation time period =T. fmin = "<T. where fmin can be obtained from the (1 wave 1a=imum deviation) Yf= fo Z fmin 1odu!ation inde= [ = Yf<fm +and width +5 = &.[H") fm = & .YfHfm) (ree running frequenc9)fo = &.@CC 0@c) < R"C"@CC PROCEDURE: ". The circuit is connected as per the circuit diagram shown in (ig". &.-bserve the modu!ating signa! on CR- and measure the amp!itude and frequenc9 of the signa!. *.5ithout giving modu!ating signa!) ta$e output at pin ,) we get the carrier wave. ,.1easure the ma=imum frequenc9 deviation of each step and eva!uate the modu!ating Gnde=. mf = [ = Yf<fm

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Vignana Bharathi Institute of Technology

Department of Electronics and communication Engineering ulse and Digital !ircuits "a#oratory

2013-14

PRECAUTIONS: Chec$ the connections before giving the power supp!9. Readings shou!d be ta$en carefu!!9. RESULT: (requenc9 modu!ated waveforms are observed and modu!ation Gnde=) +.5 required for (1 is ca!cu!ated for different amp!itudes of the message signa!.

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