Novel High Efficiency Multilevel DC-DC Boost Converter Topologies and Modulation Strategies

G. Butti1 and J. Biela2 1Newave SA, Research and Development Department, Via Luserte Sud 9 CH-6572 Quartino, Switzerland Email: gianluca.butti@newavenergy.com 2Laboratory for High Power Electronic Systems, ETH Zurich Physikstrasse 3, 8092 Zurich, Switzerland, Email: jbiela@ethz.ch

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Novel High Eciency Multilevel DC-DC Boost Converter Topologies and Modulation Strategies
G. Butti1 and J. Biela2
1

Newave SA, Research and Development Department, Via Luserte Sud 9 CH-6572 Quartino, Switzerland Email: gianluca.butti@newavenergy.com 2 Laboratory for High Power Electronic Systems, ETH Zurich Physikstrasse 3, 8092 Zurich, Switzerland, Email: jbiela@ethz.ch

Keywords
Multilevel Boost Converter, Modulation Strategies, Interleaving, Soft-Switching, High Eciency.

Abstract
In this paper new topologies and interleaving modulation concepts for multilevel DC-DC boost converter enabling a signicantly less loss and a reduced chip size of the power semiconductors are proposed. Moreover, a new soft switching concept is presented. The achievable eciency, chip area and boost inductance reduction are compared with existing solutions for VIn = 800 V, VOut = 3 kV and POut = 150 kW. A 30 % loss reduction and a chip area decrease by 50 % is achieved.

Introduction

For reducing greenhouse gas emissions and for establishing a sustainable energy supply, in the future more renewable energy sources and distributed energy storage systems are required. Many of these systems, as e.g. photovoltaic modules, fuel cells or batteries, provide a relatively low DC output voltage. At high-power levels such systems are advantageously connected to medium voltage distribution grids through multilevel voltage source inverters (VSI) [1], which enable operation at relatively low switching frequencies and to use fast low voltage devices as switching elements resulting in high eciencies and in low harmonic distortions. In order to adapt the output voltage of the energy supplies/storage systems to the medium voltage level, boosting of the DC voltage is required. For large voltage step-up ratios this task is advantageously performed by DC-DC converters based on galvanically isolated transformers. However, in case of smaller step-ratios, as often given in the considered applications, and if the galvanic isolation is not mandatory, a much higher eciency and power density can be achieved with non-isolated boost converter systems [2, 3]. As with the inverter systems, multilevel boost converter concepts basically enable to use faster semiconductor devices. This results in a higher eciency especially if a high operating frequency is required in order to achieve higher power densities and to avoid acoustic noise. Additionally, with the multilevel boost converter the DC-link capacitors of VSI can be balanced allowing a straightforward inverter control based on multilevel
4L CCM 4L VIL CCM

PV, Fuel Cell, Battery, SMES

VIn

Multilevel Boost Converter

4L VIL BCM 4L 2C VIL

VOut

Multilevel Inverter

4L ZVS 4L 2C VIL ZVS

Grid

5L CCM 5L 2C VIL 5L ZVS

a) b) Efficiency of Multilevel Boost Converter [%] Fig. 1: a) Connection of renewable energy sources and/or storage systems as photovoltaic systems (PV), fuel cells, batteries or superconducting magnetic energy storage systems (SMES) to medium voltage distribution grids via a DC-DC multilevel boost converter. b) Eciencies of the considered topologies for the specications summarised in Table I. The values for the 5-level topologies are hatched.

93.0

94.0

95.0

96.0

97.0

98.0

Table I: Specication summary for the proposed comparison of topologies.

Output Power POut Input Voltage VIn Output Voltage VOut Input Current Frequency fp Max. Junction Temperature Tjmax Ambient Temperature Ta

150 kW 800 V 3 kV 16 kHz 130 C 45 C

pulse-width modulation without regard to redundant state selection which limits the maximal modulation index [4, 5]. In [6, 7] DC-DC boost converters based on voltage multiplier concepts have been proposed. However these require a large number of capacitors and/or diodes and show an uneven current distribution amongst the semiconductors. A DC-DC boost converter with 3-level structure has been proposed in [8, 9]. For the considered high-power application, which requires a high switching frequency and which has an output in the medium-voltage range, these topologies do not represent an attractive solution since they require the use of slow high voltage switching devices resulting in low eciencies and large required chip area. In [10], a new 4-level boost converter and a modulation concept has been proposed. However, with this approach in every cycle of the input current, all switches of the boost converter must be turned on and o. This results in relatively high switching losses. In order to avoid these, new topologies and modulation concepts are proposed and evaluated in this paper. First, a modulation based on vertical interleaving is presented in section 2. With the vertical interleaving, in each cycle of the input current only one level of the multilevel output voltage is switched. This enables a signicant reduction of switching losses. Thereafter, a zero-voltage switching (ZVS) modulation, which avoids turn-on losses and signicantly reduces turn-o losses, is proposed in section 3. In order to be able to evaluate the performance of the new concepts, in section 4 a simulation model including the thermal design and parameters of real semiconductor devices is explained in detail. Finally, the performances of the proposed concepts are evaluated and compared with existing solutions in section 5. In the comparison, the specications given in Table I are assumed. There especially the lower frequency limit of the inductor current of16 kHz is important in order to avoid acoustic noise.

2
2.1

Vertical Interleaved DC-DC Boost Converters

4-level Converter

In [10] a 4-level boost converter operating in continuous conduction mode (4L CCM) as shown in Fig. 2a) and a modulation concept was proposed, where all 3 main switches turn on and o during one period of the input current. This implies high switching losses and a relatively low eciency. By adding two additional auxiliary switches for active clamping [11] on the freewheeling paths as shown in Fig. 2b) a new modulation concept (4L VIL), where only one main switch (single-cell) turns on and o during a fundamental period

LB vL LB CDC1 T1 Df,int vC1 T1 Df,ext vL LB CDC1 Ta VIn vSw vC2 VIn vSw T2 Da CDC2 vC2 T3 vC1 T2 Df,ext T1

Df,ext CDC1 vC1 Da Ta Tb Db Td

LB T1

Df,ext CDC1 Df,int vC1

iL

iL

CDC2 Dc

vC2 T2 VIn vSw

CDC2

vC2

VIn vSw T2

CDC2

CDC3

Tc

vC3

T3

CDC3

vC3

T3

CDC3

vC3

T3

CDC3

vC3

T4

Dd CDC4

vC4

T4

CDC4

vC4

a) 4L CCM, 4L 2C VIL

b) 4L VIL

c) 5L 2C VIL

d) 5L CCM, 5L 2C VIL

Fig. 2: Power circuit diagrams a) 4-level boost converter (4L CCM) presented in [10], b) proposed 4-level converter with vertical single cell interleaving (4L VIL), c) 5-level converter topology for single cell vertical interleaving (5L SC VIL) and d) 5-level converter with double cells vertical interleaving (5L 2C VIL). (VOut = N i=1 vCi , where N = 3, 4).

S1a

S2a

S1a

S3a

S1a

S4a

Fig. 3: Switching states of the circuit shown in Fig. 2b) where in each input current period a single main switch turns on and o (4L VIL). Non-current-carrying circuit components are grey coloured.

S1b

S2b

S3b

S2b

S1b

S2b

S4b

S2b

Fig. 4: Switching states for the 4L 2C VIL modulation strategy where in each input current period only two main switches turn on and o.

vSw iL
a)
0

S1a

S2a

S1a

S3a

S1a

S4a
t

vSw iL
b)
0

S2b S3b S2b S1b

S2b S1b

S4b S2b S2b S3b S2b S1b

t

IL,avg
dT T 2T 3T t

IL,avg
d 1T d 2T t3 T 2T 3T t

Fig. 5: Modulation strategy with resulting time behaviours of the voltage over the main switches vSw and input current iL in the boost inductor for a) the 4L VIL topology shown in Fig. 2b) and b) the 4L 2C VIL concept used on the circuit shown in Fig. 2a) (cf. Fig. 3 and Fig. 4).

of the input current, is enabled. This drastically reduces the switching losses and results in a smaller total amount of required chip area compared to the 4L CCM as will be shown in section 5. The modulation concept is called vertical interleaving (VIL) following the known interleaving concept of parallel connected converters, which also increases the ripple current frequency [12] compared to the switching frequency. In order to set a basis for a fair comparison between these two topologies both are operated in continuous conduction mode (CCM). In addition to the specications given in Table I, an inductor current ripple iLpp 15 % of the average value has been selected. This criterion has been applied also for all the other topologies operated in CCM presented in the following section. In Fig. 3 the sequence of switching states for the 4L VIL strategy is shown. Comparing with Fig. 5a), it can be noticed that in each period of the input current only one main switch/cell turns on/o. The duty cycles of the three states, where energy is transferred to the secondary side (i. e. S2a , S3a and S4a ), are controlled, so that the three capacitor voltages are balanced. With the original topology (Fig. 2a) also a double cell vertical interleaving (4L 2C VIL) would be possible. There two of the main switches are always turned on/o per input current period as shown in Fig. 4. Considering the time behaviour of the voltage over the main switches vSw given in Fig. 5b), the middle capacitor and one of the outer capacitors must be always charged. The switching sequence starts and ends with the middle main switch in order to avoid a double rated voltage stress on the external switches. The 2C VIL modulation strategy is also possible with the circuit given in Fig. 2b). In every current cycle, the central capacitor is charged together with an external one but in this case there is the possibility to select the cell with which to start the switching sequence.

2.2

5-level Converter

Increasing the number of levels results in the 5-level converters depicted in Fig. 2c) and d). Analogous to the 4-level topologies presented in the previous paragraph, the 5-level DC-DC boost converter can also be modulated by turning on and o all four main switches during one period of the input current (5L CCM) with the switching states represented in Fig. 6 and the resulting input current in Fig. 8a). For the 5L CCM converter, the switching sequence is accomplished as a function of the output voltages as described by the switching diagram shown in Fig. 7a). The overall switching state sequence suggested for this converter is S1c (S2c1 or S2c2 ) (S3c1 or S3c2 or S3c3 ) (S4c1 or S4c2 ) S5c . It can be noticed that this sequence is similar to that of a standard single-level DC-DC boost converter with additional switching states. The amount of time spent at the particular switching state is controlled depending on the reference

S1c

S2c1

S3c2

S4c1

S5c

S4c1

S3c2

S2c1

S1c

Fig. 6: Switching states of the 5L CCM converter shown in Fig. 2d) when vC 2 < vC 3 and vC 3 < vC 1 < vC 4 .

output voltage and the voltage imbalance between the output cells. The duration of states S3ci and S4ci can be controlled to maintain the voltage balance between the external capacitors C1 and C4 . The states are selected depending on which capacitor voltage is lower (cf. Fig. 7a). With the 5-level converter switching devices with a lower blocking voltage and therefore faster switching transients can be applied. However, due to the 5L CCM modulation with hard switching relatively high switching losses and a low eciency results as will be shown in section 5. In order to enable a single-cell vertical interleaving strategy (5L SC VIL) the topology of Fig. 2c) must be used. Because of the specications given in Table I, with a single-cell strategy it would not be possible to demagnetise the input inductor since VIn > VOut /N (N = 4). Accordingly, for the considered specications switching states where energy is transferred to two output cells at the same time must utilised. This concept can be obtained with a double cell vertical interleaving method (5L 2C VIL) without additional auxiliary switches for active clamping on the freewheeling paths using the circuitry shown in Fig. 2d). Besides having the great advantage of a lower number of switches reducing conduction/switching losses, required chip area as well as cost of supplementary gate drive units, this topology requires the same amount of freewheeling diodes as the 4-level circuit thanks to its symmetry with respect to the mid-point of the output voltage. In the 2C VIL modulation strategy applied to the 5-level topology two of the main switches are always turned on/o per input current period starting from the middle capacitor with the lower voltage and then with the second lowest voltage cell next to this (cf. Fig. 7a), Fig. 7b) and Fig. 8b)). The double cell vertical interleaving method enables a high eciency and requires a low amount of chip area as shown in section 5, since faster semiconductor devices with a lower blocking voltage can be applied and also less switching actions are performed for every input current period. The advantages of the presented topologies operated in CCM can be summarised by: With VIL a higher eciency and a higher power density could be achieved due to a size reduction of chip area, dc-link capacitors and input inductor (cf. section 5).
T1 T2 T3 T4 T1 T2 T3 T4 vC2 < vC3 T1 T2 T3 T4 1 1 1 1 vC1 < vC3 else T1 T2 T3 T4 vC3 < vC4 T1 T2 T3 T4 1 1 0 1 T1 T2 T3 T4 0 0 0 0 else T1 T2 T3 T4 1 0 0 0 1 0 0 1 T1 T2 T3 T4 0 0 0 1 vC1 < vC4

S2c1 / S2d1

1 0 1 1

S3c1 / S3d1

0 0 1 1

S4c1

S1d

S2d1

S3d1

S2d1

S1c / S1d

else

S3c2 / S3d2
T1 T2 T3 T4 1 1 0 0

S5c

S1d
b)

S2c2 / S2d2

else

a)

S3c3 / S3d3

S4c2

Fig. 7: a) Switching sequences for the 5-level converter shown in Fig. 2d) and modulated with 5L CCM or 5L 2C VIL strategies. At state S5c / S3d , the sequence is run through backwards for 5L CCM / 5L 2C CCM. In the tables the terminology used is 1 for switch Ti turned on, 0 for switch Ti turned o (i = 1, 2, 3, 4). b) Switching states of the 5L 2C VIL converter shown in Fig. 2d) when vC 2 < vC 3 and vC 1 < vC 3 .

vSw

S1c

S2c1 S3c2 S4c1 S5c S4c1 S3c2 S2c1 vSw S1d S2d1 S3d1 S2d1
t

iL
a) 0
d1T d2T d3T d4T T

IL,avg
t

iL
b)
0 d1T d2T T

IL,avg
t

Fig. 8: Modulation strategy with resulting time behaviours of the voltage over the main switches vSw and input current iL in the boost inductor for a) the 5L CCM topology and b) the 5L 2C VIL concept used on the circuit shown in Fig. 2d) (cf. Fig. 7a), Fig. 6 and Fig. 7b)).

 The SC VIL strategy enables a completely free balancing of the output voltages. As it is shown in section 5 the total silicon chip area of a 5-level topology can be lower than that of a 4-level topology, since the losses are distributed over more components resulting in improved cooling conditions. Whereas the limits of 4L VIL compared to 4L CCM are: More gate driver circuits are required. The SC VIL strategy works only if Vin < vCi (2C VIL and if Vin < 2 vCi ). With 4L 2C VIL, the central capacitor is always slightly more charged than the two outer ones, requiring for example an inverter as a load.

Soft Switching DC-DC Boost Converters

All the converter systems proposed in the previous section operate in CCM with hard switching, thus resulting in high switching losses. In order to reduce the losses, the topologies are modied as represented in Fig. 9. Here a circuitry consisting of an anti-parallel diode / a capacitor connected in parallel to each main switch and a new modulation method prevents turn-on losses and reduces turn-o losses due to zero-voltage switching (ZVS) conditions [13]. With the sequence of the switching states and the input current time behaviour in Fig. 10 and Fig. 11, it can be seen that the system of Fig. 9a) operates in boundary conduction mode (BCM). After turning o all main switches at current zero-crossing (i.e. at t = t4 , cf. Fig. 11), the energy transfer via the external diodes Df,ext ends and since the voltage across the boost inductor is negative, the input current becomes negative and discharges the snubber capacitors (LC-oscillation). As soon as the anti-parallel diodes of the IGBTs start to conduct, the main switches are turned on with no losses. As described in section 5, the eciency increases despite the higher peak current which has to be turned o. Additionally, the boost inductance is much smaller compared to the existing system (4L CCM). The ZVS condition also could be applied to the other topologies and modulation strategies presented in the previous section. For a single-cell vertical interleaving modulation with ZVS, the topology in Fig. 2b)

LB vL LB T1 Df,ext CDC1 vL LB vC1 T1 DT1 vL LB vC1 T1 Df,ext CDC1 Ta Da vC2 VIn vSw T2 CDC2 vC2 T3 T1

CDC1 DT1 CSnb1 Df,int

vC1

iL

iL

T1s D1s CDC1 CSnb1 T2s D2s CDC2 T2 D3s T3s

iL

DT1 CSnb1 Df,int

DT1 CSnb1

vC1 T2 VIn vSw

CDC2

vC2

VIn vSw T2

CDC2

vC2

VIn vSw

CDC3

vC3

T3

CDC3

vC3

T3

CDC3 D4s T4s

vC3

T3

CDC3

vC3

T4

CDC4

vC4

d) 5L ZVS, 5L 2C VIL ZVS c) 4L 2C VIL ZVS b) 4L SC VIL ZVS a) 4L ZVS, 4L 2C VIL ZVS Fig. 9: Circuit diagrams of a) 4-level ZVS soft switching converter (4L ZVS). b) 4-level ZVS converter with four small additional switches for single-cell vertical interleaving (4L SC VIL ZVS) and c) 4-level ZVS converter for 2C VIL with the possibility to select the starting cell. In d) a 5-level version of the ZVS converter is shown, which is also considered in the comparison presented in section 5. (VOut = N i=1 vCi , where N = 3, 4).

S1e

S2e

S3e

S4e

S5e

S6e

S7e

S8e

S9e S1e

Fig. 10: Switching states of the 4L ZVS soft switching converter shown in Fig. 9a) when vC 1 < vC 3 . (The switches turned on are shown in black)

vSw iL

S1e

S2e S4e S6e S3e S5e S7e

S8e S9e
t

IL,avg
0 d1T d2T d3T t4 t5 T t

Fig. 11: Modulation strategy with time behaviour of the main switches voltage vSw and input current iL in the boost inductor for the 4L ZVS topology shown in Fig. 9a) when vC 1 < vC 3 (cf. Fig. 10).

must be modied as given in Fig. 9b). The control strategy works in the same manner as in the CCM case, where at the beginning of each input current period the cell with the lowest voltage is selected and then charged during the demagnetisation of the boost inductor. The additional switches connected anti-parallel to the external freewheeling diodes are required since with the specications given in Table I, it would not be possible to completely discharge the snubber capacitors with the resonance between Lb and CSnb as the dierence between the cell and the input voltage is smaller than the input voltage. Therefore, the additional switches T1s and T4s are turned on shortly before the zero crossing of the current at t2 in Fig. 12b), so that the voltage vSw is clamped to the converter output voltage and energy is transferred from the output capacitors to the boost inductor and the inductor current becomes negative (cf. state S4f in Fig. 12). As soon as enough energy is stored in the boost inductor (i.e. at t = t3 , cf. Fig. 12b)) , T1s and T4s are turned o at ZVS and the snubber capacitors are discharged, so that also the main switches can be turned on at zero voltage. With the original topology in Fig. 9a) also a double cell vertical interleaving with ZVS (4L 2C VIL ZVS) is possible and allows ZVS conditions without additional switches. As described in the previous section, but this time with the circuit operated in BCM, always the central main switch plus either the upper or the lower main switch are turned on/o per input current period. There, the switching sequence starts always with the middle main switch (cf. Fig. 13-14). As shown in section 5 with this concept the system eciency could be increased up to 0.7 % compared to the 2C VIL operated in CCM and also reduces the boost inductance value.
S1f S2f S3f S4f S5f S6f S1f
a) vSw iL b) N
0 d1T t2 t3 t4 T

S1f

S2f

S3f

S4f

S5f S6f
t

IL,avg
t

Fig. 12: a) Switching states of the soft switching converter shown in Fig. 9b) modulated with a 4L SC VIL strategy (4L SC VIL) when vC 2 < vC 1 and vC 2 < vC 3 . b) 4L SC VIL ZVS modulation strategy with time behaviours of the main switches voltage vSw and input current iL in the boost inductor for the topology shown in Fig. 9b) when vC 2 < vC 1 and vC 2 < vC 3 (cf. Fig. 13).

S1g

S2g

S3g

S4g

S5g

S6g

S7g S1g

Fig. 13: Switching states of the soft switching converter shown in Fig. 9a) modulated with 4L 2C VIL strategy (4L 2C VIL ZVS) when vC 1 < vC 3 .

vSw iL

S1g

S2g S4g S3g

S5g

S6g S7g
t

IL,avg
0 d1T d2T t4 t5 T t

Fig. 14: 4L 2C VIL ZVS modulation strategy with time behaviours of the main switches voltage vSw and input current iL in the boost inductor for the topology shown in Fig. 9a) when vC 1 < vC 3 (cf. Fig. 13).

For the sake of completeness it has to be mentioned, that the 2C VIL ZVS modulation strategy could also be applied to the circuit given in Fig. 9c). Consequently, with this topology it is possible to begin the switching sequence with any cell.

Simulation Model and Eciency Calculation

For evaluating the performance of the proposed converter topologies and modulations strategies and for comparison with existing solutions, a detailed simulation model has been developed using GeckoCIRCUITs [14]. In the model, the conduction and switching losses of the power semiconductor, calculated by the algorithm described in [15], are included based on data sheet values and measurements. Moreover, the complete thermal design of the power semiconductors and the heat sink are included, so that the junction temperature is calculated and the dependency of the losses on the junction temperature is also considered. The semiconductor devices used for the dierent circuit topologies are listed in Table II a) and b). In all the topologies operated in CCM, SiC-diodes are used in order to signicantly reduce the turn-on losses of the main switches by avoiding reverse-recovery of the diodes. This, however, results in higher costs for the diodes. Based on [18, 19] the turn-on losses for the combination IGBT/SiC diode, which are considered in the simulation, have been reduced by 30 % compared to the data sheet values. This is not the case for the central switch of the 4L VIL topology, since this switch utilises the anti-parallel silicone diodes of the IGBTs as freewheeling diodes. For the turn-o losses under ZVS conditions, a reduction of 40 % compared to the data sheet values is assumed. This assumption is based on the values presented in [13]. For all the topologies with soft-switching modulation, cheap fast Si diodes can be used as freewheeling diodes, resulting in signicantly lower costs. With the detailed circuit simulation and the thermal model, the chip area of the semiconductors for all the topologies/modulation strategies has been minimised given the temperautre constraints, such that the
a) Component T1-T4 Ta-Tb Da-Db Df,ext Df,int
Cree C2D20120D -

4L CCM

4L VIL CCM 4L 2C VIL

Eupec-Infineon FZ400R17KE4 Eupec-Infineon FZ400R17KE4 Eupec-Infineon FZ400R17KE4 Cree CPW3-1700S025

5L CCM
Eupec-Infineon FZ400R12KS4 -

5L 2C VIL
Eupec-Infineon FZ400R12KE4

b) Component 4L VIL BCM T1-T4 T a, T b D a, D b DT Df,ext Df,int

Eupec-Infineon FZ400R17KE4 Eupec-Infineon FZ400R17KE4 Cree CPW3-1700S025 -

4L ZVS
Eupec-Infineon FZ400R17KE4

4L 2C VIL ZVS

5L ZVS
Eupec-Infineon FZ400R12KS4

Eupec-Infineon FZ400R17KE4 Semikron SEMIPACK SKKD 60F Semikron SEMIPACK SKKD 42F12 Eupec-Infineon FZ400R12KS4

Cree C2D20120D

Table II: Summary of the semiconductor devices used in the implementation for a) the proposed circuit topologies operated in CCM described in section 2 and b) for the solutions driven in BCM employing ZVS described in section 3.
Df,int Df,ext T2 T1

4L CCM
Conduction Turn-on Turn-off PV,Tot = 7.88kW
0 100 200 300 400 500 600 700 800 900 [W]

Df,ext Da Ta T2 T1

4L VIL CCM
Conduction Turn-on Turn-off PV,Tot = 3.87kW
0 100 200 300 400 500 600 700 800 900 [W]

Df,int Df,ext T2 T1

4L 2C VIL
Conduction Turn-on Turn-off PV,Tot = 6.37kW
0 100 200 300 400 500 600 700 800 900 [W]

Fig. 15: Semiconductor power loss distribution of the 4-level DC-DC boost converter topologies operated in continuous conduction mode (CCM) and with an input current frequency of 16 kHz. In the loss calculations the parameter of a 1700 V IGBT-Module (Eupec-Inneon FZ400R17KE4, [16]) and of a 1200 V resp. 1700 V SiC Schottky Diodes (Cree C2D20120D, Cree CPW3-1700S025, [17]) are considered (cf. Table II).
Df,ext Da Ta T2 T1

4L VIL BCM
Conduction Turn-on Turn-off PV,Tot = 4.79kW
0 100 200 300 400 500 600 700 800 900 [W]

Df,int Df,ext T2 T1

4L ZVS
Conduction Turn-on Turn-off PV,Tot = 5.51kW
0 100 200 300 400 500 600 700 800 900 [W]

Df,int Df,ext T2 T1

4L 2C VIL ZVS
Conduction Turn-on Turn-off PV,Tot = 5.17kW
0 100 200 300 400 500 600 700 800 900 [W]

Fig. 16: Semiconductor power loss distribution of the 4-level DC-DC boost converter topologies operated in boundary conduction mode (BCM) with ZVS and an input current frequency of 16 kHz. In the loss calculations the parameter of a 1700 V IGBT-Module (Eupec-Inneon FZ400R17KE4, [16]) and of a 1700 V resp. 1700 V Fast Diode Modules (Semikron SEMIPACK SKKD 60F, Semikron SEMIPACK SKKD 42F12, [22]) are considered (cf.Table IIb).

Df,int Df,ext T2 T1

5L CCM
Conduction Turn-on Turn-off PV,Tot = 4.19kW
0 100 200 300 400 500 600 700 800 900 [W]

Df,int Df,ext T2 T1

5L 2C VIL
Conduction Turn-on Turn-off PV,Tot = 3.15kW
0 100 200 300 400 500 600 700 800 900 [W]

Df,int Df,ext T2 T1

5L ZVS
Conduction Turn-on Turn-off PV,Tot = 4.10kW
0 100 200 300 400 500 600 700 800 900 [W]

Fig. 17: Semiconductor power loss distribution of the 5-level DC-DC boost converter topologies operated in continuous conduction mode (CCM) or in boundary conduction mode (BCM) with ZVS and an input current frequency of 16 kHz. In the loss calculations the parameter of the semiconductor devices summarised in Table IIa)-b) are considered.

maximum junction temperature must be below T j = 130 C for an ambient temperature of 45 C. There, only commercially available devices have been considered, and the chip area has always been increased/decreased by the area of a complete device. Therefore, in some cases a maximum junction temperature signicantly below 130 C results (cf. Fig. 18a)), thus enabling a further reduction of chip area by applying custom modules. A loss comparison with variable semiconductor chip area and thermal model adaptation as proposed in [20, 21] could be studied in the future and could reveal interesting insight into the loss sharing between the dierent semiconductors. With the simulation models, the loss distributions of the dierent converters are evaluated for the specications given in Table I. The obtained result for the power loss distribution of each of the proposed DC-DC multilevel boost converter are shown in Fig. 15-17.
4L VIL BCM Achip, T = 9.15 cm2, Achip, T = 9.15 cm2
1 2

4L CCM 4L VIL CCM 4L VIL BCM 4L 2C VIL 4L ZVS 4L 2C VIL ZVS 5L CCM 5L 2C VIL 5L ZVS

Tj [C] 130
125 120 115 110 105 100 95 90

5L CCM 4L 2C VIL 5L ZVS 4L CCM 5L 2C VIL 4L ZVS

Achip, T = 6.34 cm2, Achip, T = 6.34 cm2

1 2 1 2

4L VIL CCM Achip, T = 4.58 cm2, Achip, T = 9.15 cm2 Achip, T = 9.15 cm2, Achip, T = 18.30 cm2
1 2

Achip, T = 6.34 cm2, Achip, T = 6.34 cm2

1 2

Achip, T = 18.30 cm2, Achip, T = 18.30 cm2

1 2

Achip, T = 9.23 cm2, Achip, T = 6.34 cm2

1 2

Achip, T = 13.73 cm2, Achip, T = 13.73 cm2

1 2 1 2

4L 2C VIL ZVS Achip, T = 9.15 cm2, Achip, T = 13.73 cm2

a)

T1

T2

b)

Max Energy in LB [mJ]

10

15

20

25

Fig. 18: a) Maximum steady state junction temperature of the mains switches b) Maximal energy stored in the boost inductors.

Performance Evaluation of DC-DC Boost Converters

The basis of the following comparison are the specications given in Table I. The converters supply an unbalanced resistive load that model an imbalance that would exist with a connected inverter. The output is controlled so that the capacitor voltages are balanced and that the total DC-link voltage is VOut = 3 kV. The frequency of the inductor current is set to 16 kHz in order to avoid acoustic noise caused by magnetostrictive phenomena. Furthermore, a maximal ripple VOutpp of the total output voltage of 3 % is selected as well as a maximal current ripple iLpp 15 % of the average value in case of CCM operation. In the performance evaluation, for all the considered topologies the minimum semiconductor chip area is determined so that the maximal junction temperature is 130 C at an ambient temperature of 45 C. The resulting semiconductor chip areas required are shown in Fig. 19a). There also the value of the boost inductance and the value of the required output capacitance are depicted where the converter eciencies are shown in Fig. 1b) and c). In Fig. 18b) the maximal energy stored in the boost inductors is given, which is approximately proportional to the volume. The 4L CCM proposed in [10] shows the lowest eciency and requires the largest chip area as well as the largest boost inductance value. The new proposed 4L VIL converter enables an eciency improvement by 2.5 %, a chip area reduction by 40 % and a reduction of the boost inductance by more than 60 %. The reason for the performance improvement is that only one output capacitor voltage (= 1 kV) is used to control the inductor current, so that the eective boost ratio is only from 800 V to 1 kV resulting in a smaller boost inductance. Furthermore, the eective switching frequency is reduced by a factor of 3, i.e. the switches operate at approximately 5.3 kHz compared to 16 kHz in case of the 4L CCM.

4L CCM 4L VIL CCM 4L VIL BCM 4L 2C VIL 4L ZVS 4L 2C VIL ZVS 5L CCM 5L 2C VIL 5L ZVS

4L CCM 4L VIL CCM 4L VIL BCM 4L 2C VIL 4L ZVS 4L 2C VIL ZVS 5L CCM 5L 2C VIL 5L ZVS

4L CCM 4L VIL CCM 4L VIL BCM 4L 2C VIL 4L ZVS 4L 2C VIL ZVS 5L CCM 5L 2C VIL 5L ZVS

a)

10

Total Chip Area [cm2]

20

30

40

50

60

70

b)

200

Boost Inductor LB [mH]

400

600

800

1000

1200

c)

0 10 20 30 40 50 60 70 80 90 100 110

Output Capacitor CDC [mF]

Fig. 19: a) Total semiconductor chip area required for a maximal junction temperature Tjmax 130 C and a current frequency fp =16 kHz. b) Boost inductor values LB for a maximal input current ripple iLpp 15 %IL,avg in case of operation in CCM. c) DC-link capacitors for a maximal output voltage ripple VOut,pp 3 %VOut .

With the 4L ZVS soft switching concept a reduction of the boost inductance value by a factor of 13 is possible. However, due to the discontinuous input current, which results in high peak current values, the reached increase of the semiconductor eciency is lower than with the 4L VIL but results 1.5 % higher than with the 4L CCM. Parameter LB [H] CCD [F] AChip [cm2 ] Semi 4L CCM 1050 63.5 58.39 95.0 % 4L VIL CCM 390 42 35.35 97.5 % 4L 2C VIL 1050 63.5 40.09 96.0 % 5L CCM 1075 87.5 28.84 97.3 % 5L 2C VIL 780 64 34.61 97.9 %

Table III: Boost inductance LB , output capacitor CCD , total chip area AChip and semiconductor eciency Semi for the considered topologies operated in CCM (cf. section 2).

Parameter LB [H] CCD [F] AChip [cm2 ] Semi

4L VIL BCM 30 35 44.50 96.9 %

4L ZVS 80 73 60.60 96.5 %

4L 2C VIL ZVS 70 64 46.25 96.7 %

5L ZVS 80 100 50.50 97.3 %

Table IV: Boost inductance LB , output capacitor CCD , total chip area AChip and semiconductor eciency Semi for the considered topologies modulated with ZVS control strategies (cf. section 3). The values concerning the 4L VIL power circuit circuit (cf. Fig. 2b)) in this case are obtained with BCM strategy.

Conclusion

In this paper new topologies and modulation concepts based on vertical interleaving (VIL) for hard and soft switched 4- and 5-level DC-DC boost converters are presented. With VIL, the semiconductor losses as well as the value of the boost inductance can be reduced by 50 % and 60 % respectively. Also, due to the lower switching losses the required chip area could be reduced by 40 %. Additionally, a new soft switching concept for multilevel converter is presented. Due to the higher peak current values with ZVS only a loss reduction by 30 % compared to known 4L CCM is achieved. All the new concepts are explained in detail and the achievable performance (eciency/required chip area/boost inductance values/output capacitance) is compared with existing solutions based on simulation models including the thermal design of the system. In the comparison VIn = 800 V, VOut = 3 kV and POut = 150 kW are assumed. Furthermore, for all topologies an input current with a fundamental frequency of 16kHz and the same output voltage ripple are considered.

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