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“Soft” Turn-off Feature

Products with Feature: ACPL-333J, ACPL-330J, ACPL-332J, ACPL-331J, HCPL-316J

HCPL-316J V E 16 V LED2+ 15 100 pF DESAT 14 100 Ω D DESAT
HCPL-316J
V E
16
V LED2+
15
100 pF
DESAT
14
100 Ω
D DESAT
V
CC2
13
V C
12
V
OUT
11
R g
V
EE
10
V
EE
9

Application Note 5315

Introduction

Avago’s gate optocoupler “Soft” turn-off feature is used to increase the reliability of an application during short- circuit or over-current periods. This feature works after the DESAT protection is activated, which provides pro- tection for transistor switches (IGBT/MOSFET) against short-circuit and over-current events. The desaturation protection circuit is illustrated in Figure 1. With the “Soft” turn-off feature, the gate voltage will be reduced slowly in order to reduce IGBT current. This is a two stage turn-off system. It will slowly discharge the IGBT gate to prevent a fast change in drain current. The “Soft” IGBT turn-off method will avoid an over-voltage spike across the IGBT caused by lead and wire inductances.

How does desaturation protection and “Soft” shut-down work? This is illustrated in Figure 2.

Figure 1. Desaturation Protection using the HCPL-316J t DESAT (FAULT) t DESAT (10%) A t
Figure 1. Desaturation Protection using the HCPL-316J
t DESAT (FAULT)
t DESAT (10%)
A t DESAT (LOW)
7 V
V
DESAT
50%
t DESAT (90%)
90%
V
OUT
B
10%
FAULT
C 50% (2.5 V)
t RESET (FAULT)
RESET
50%

Figure 2. Desaturation, Gate Output Voltage V OUT , FAULT and RESET Waveforms During Short-circuit or Overcurrent

Note:

t DESAT(90%) is the DESAT Sense to 90% V OUT time delay t RESET(FAULT) is the RESET to High Level FAULT signal time delay

i.

Fault Detection:

IGBT collector-emitter voltage, VCESAT is monitored through the DESAT pin 14. The IGBT is turned off if the voltage threshold (typically 6.5 V to 7 V) is reached (Point A).

ii. Soft Turn-off:

This is a two stage process. In the first stage, a weak pull-down device in the output drive stage will turn on to ‘softly’ turn off the IGBT. This device slowly discharges the IGBT. This turn off delay time of the gate optocoupler is labeled as DESAT sense to 10% VOUT delay, t DESAT(10%) , in Figure 2. During soft turn-off, the internal 1xDMOS tran- sistor is turned on (Figure 3b).

During the slow turn off, the large output pull-down device, which is the second stage (Point B) remains off until the output gate voltage falls below V EE + 2 V, at which time the large pull-down device, 50x DMOS tran- sistor, clamps the IGBT gate to V EE . The 50x represents a DMOS device 50 times larger than a 1x device (figure 3a).

This t DESAT(10%) time is dependent on the gate resistor R g , gate capacitance C g , output supply voltage V CC2 , and DMOS R ds(on) value. In the HCPL-316J datasheet, t DESAT(10%) is typically 2 ms for R g = 10 W and C g = 10 nF.

An approximation of the DMOS R ds(on) can be obtained by V OUT /I OL = 2.5/2.3 = 1.09 W (Page 9 of the HCPL-316J datasheet, Low Level Output Current). Hence the 1x DMOS R ds(on) is 50 x 1.09 = 54.5 W. The time constant can be approximated using C g (R g + 54.5).

Using the same calculation method for the ACPL-332J, R ds(on) = 2.5/1.5 = 1.7 W. Hence the 1xDMOS R ds(on) is 50x1.7 = 85 W.

Two characterization graphs reflecting the influence of Rg and Cg to the DESAT sense to 10% time are shown in Figure 4 and Figure 5. Both graphs can be found on page 13 in the ACPL-332J datasheet

iii. Fault Output and Off State:

After the DESAT sense to Low-level FAULT signal delay time, t DESAT(FAULT) , the FAULT signal goes low (Point C). The fault detect circuitry is disabled to prevent false ‘fault’ signals. The driver outputs will remain low (IGBT off) until the following two conditions are met:

The DESAT detection is low AND there is a RESET signal (HCPL-316J) or a RESET by the next INPUT PWM high signal is sent (ACPL-331J, ACPL-332J), ACPL-332J) or an internal automatic fault RESET after a fixed-mute time of typically 26 ms (ACPL-330J, ACPL-333J).

250 µA V E (16) DESAT (14) + V IN+ (1) V (2) LED -
250 µA
V
E (16)
DESAT (14)
+
V
IN+ (1)
V
(2)
LED
-
7 V
IN -
V
CC1 (3)
V
CC2 (13)
UVLO
-
GND (4)
DELAY
+
12 V
V
C (12)
FAULT (6)
Q
V
OUT (11)
R
S
RESET (5)
FAULT
50 x
V
EE (9,10)
1 x
FAULT

Figure 3a. Behavioral Circuit Schematic

250 µA V (16) E DESAT (14) + LED - 7 V V (13) CC2
250 µA
V
(16)
E
DESAT (14)
+
LED
-
7 V
V
(13)
CC2
UVLO
-
+
12 V
O
V
(12)
C
O
O
O
V
(11)
OUT
O
O
FAULT
50 x
O
O
I
O
ON
V
(9,10)
EE
O
I
1 x
O OFF
Figure 3b. Normal Operation 250 µA V (16) E DESAT (14) + LED - 7
Figure 3b. Normal Operation
250 µA
V
(16)
E
DESAT (14)
+
LED
-
7 V
V
(13)
CC2
UVLO
-
+
12 V
V
(12)
C
I
V
(11)
OUT
I
FAULT
50 x
I
O
I
OFF
V
(9,10)
EE
I
1 x
I ON

Figure 3c. Soft-shutdown Operation

0.012 -------V cc2 =15 V V cc2 =30 V 0.008 0.004 0.000 0 10 20
0.012
-------V cc2 =15 V
V
cc2 =30 V
0.008
0.004
0.000
0
10
20
30
40
50
T DESAT10% - DESAT Sense to 10% Vo Delay - ms

Figure 4. Normal Operation

LOAD CAPACITANCE - nF

4.0 ------- V cc2 =15 V V cc2 =30 V 3.0 2.0 1.0 0.0 10
4.0
-------
V cc2 =15 V
V
cc2 =30 V
3.0
2.0
1.0
0.0
10
20
30
40
50
T DESAT10% - DESAT Sense to 10% Vo Delay - us

LOAD RESISTANCE - ohm

Figure 5. Soft-shutdown Operation

Soft-turn off Function with External Current Buffer Drive:

To increase the IGBT gate drive current, a non-inverting current buffer, Figure 5, can be used. Inverting types are not compatible with the desaturation fault protection circuitry and should be avoided.

To preserve the slow IGBT turn-off feature during a fault condition, a 10 nF capacitor should be connected from the buffer input to VEE and a 10 Ω resistor inserted between the output and the common NPN/PNP base. For this soft-shutdown circuit topology, it is assumed that the load capacitor should be greater than the 10 nF used.

In this circuit, after a desaturation fault is detected, the weak pull-down device 1xDMOS transistor will pull the external RC circuit before the current buffer (R=10 Ω, C=10 nF). Refer back to Section ii, soft turn-off for details.

The circuit topology in Figure 6 is also applicable for other Avago DESAT featured gate optocoupler drivers, like the ACPL-332J, ACPL-331J, ACPL-333J and ACPL-330J.

The MJD44H11/MJD45H11 transistor pair is appropriate for currents up to 8 A maximum. The D44VH10/D45VH10 transistor pair is appropriate for currents up to 15 A maximum.

HCPL-316J V 16 E 100 pF V 15 LED2+ DESAT 14 V 13 CC2 MJD44H11
HCPL-316J
V
16
E
100 pF
V
15
LED2+
DESAT
14
V
13
CC2
MJD44H11 or
V
12
D44VH10
C
4.5
10 Ω
V
11
OUT
2.5
10 nF
V
10
EE
MJD45H11 or
D45VH10
V
9
EE
15 V
-5 V

Figure 6. Current Buffer for Increased Drive Current

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. AV02-0073EN - July 21, 2010

Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. AV02-0073EN - July 21,