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Type C791 thyristor is suitable for phase control applications such as for HVDC valves,static VAR compensators and synchronous motor drives.The silicon junction design utilizes a second generation pilot gate and a unique orientation of emitter shorts which promote the lateral expansion of conducting plasma resulting in lower spreading losses while achieving high dv/dt withstand.It is supplied in an industry accepted disc-type package,ready to mount using commercially available heat dissipators and mechanical clamping hardware .
On-State Characteristic
On-State Current, It (A) 60000
REPETITIVE PEAK REVERSE AND OFF-STATE BLOCKING VOLTAGE TJ= 0 t o1 2 5oC MODEL VD R M VR R M ( v o l t s ) ( v o l t s ) C791EP 5000 5000 C791DT 4900 4900 C791DN 4800 4800 C791DS 4700 4700 C791DM 4600 4600 C791DE 4500 4500 MECHANICAL OUTLINE
J
C L
C L
Thermal Impedance
.01 Zthj-case (degC/watt)
A B
2 0 5
.0001 0.001
o1a:t305tau
0.01
10
ELECTRICAL CREEPAGE / STRIKE 1 . 6/1 . 0i n 40.6 / 25.4 mm CLAMPING FORCE ( r a n g e ) 17000-19000 lb.
C791 / 6RT302
LIMITING CHARACTERISTICS AND RATINGS
Repetitive peak offstate & reverse volts @ 5Hz Repetitive working crest voltage, 60Hz Off-state & reverse leakage current, 60Hz Average on-state current Peak half-cycle non-rep surge current On-state voltage VD R M VR R M T J=0 t o1 2 5oC u pt o 5000 V
VD W M VD R M I D W M I R W M I T(AV)
T J=0 t o1 2 5oC T J=0 t o1 2 5oC T case= 70oC 60 Hz 50 Hz I =4000A T =8.3ms t P T J=125oC T J=125oC 60 Hz T J=125oC V D =.67VD R M T J=125oC 2 A / u s 5 A / u s Vd=.5VD R M 5A/us,-100V 20V/us to 2000V
I2t Mamp2sec
10
I2t Itsm
A
I TSM
4 4 . 5 4 1 . 5 2 . 0 0
kA
VT M
d i / d t r e p d v / d t
100
A/us
1000
V/us
I R M
A 90 195
10000
t d T off
4 500
u s u s
01l:C791ITSM
1 10
R thJC F
. 0 0 5 17000 -19000
c/w l s . b
THYRISTOR GATE IMPEDANCE Enhanced by fast rising gate voltage,increasing anode bias and junction temperature.It is at a minimum for dc current, zero anode bias and low temperature. GATE SUPPLY Prefer 50V/10 ohm for supporting the di/dt rating and life expectancy. The short circuit current risetime should be nominally 0.5us and the duration longer than the expected delay time for all magnitudes of anode bias. Practically 10-30us is recommended followed by a back porch of 750ma if needed to sustain conduction. MINIMUM ACCEPTABLE GATE CURRENT The intersection of the load line and gate impedance characteristic indicates the minimum value of actual current needed during the delay time interval to support di/dt.A different load line meeting this criterion may be used. MAXIMUM GATE RATINGS Peak gate power,Pgm(100us) = 300 W Average gate power,Pg(av) = 50W Peak gate current,Igfm = 25 A Peak reverse voltage,Vgrm = 25 V
30
load line
20
10 static (dc) @ 25 C
Sh2 Rev. 4
10/29/01
C791 / 6RT302
FULL CYCLE AVERAGE POWER DISSIPATION
120-deg Conduction -includes spread loss as function of Overlap Angle , U
Average Power , Pavg (watts) 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 0 500 1000 1500 2000 2500 3000 3500 4000
U = 2 deg U = 20 U = 40
120 degrees
dt
100
U
120 deg + U
U
di I dt
RM(REC) (REC)
Tj = 125degC
Process Maximum
10 0.1
di/dt (A/us)
5000
single shot
2000
150
4000
conduction angle
120
50/60 Hz
3000
1500
90
1000
60
2000
30
500
di/dt in A/us
sh 3.
Rev. 4. 10/29/01