EXPERIMENT NO. 1.

AIM: To study transient and dc analysis of NMOS Inverter. APPARATUS: Tanner software, PC and power supply. THEORY:
An inverter circuit outputs a voltage representing the opposite logic level to its input. Inverters can !e constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this "resistive drain# approach uses only a single type of transistor, it can !e fa!ricated at low cost. There are two types of electrical co$ponents, na$ely active and passive co$ponents. Passive components can#t introduce net energy into the circuit. They also can#t rely on a source of power, e%cept for what is availa!le fro$ the &AC' circuit they are connected to. As a conse(uence they can#t a$plify &increase the power of a signal', although they $ay increase a voltage or current &such as is done !y a transfor$er or resonant circuit'. Passive co$ponents include two ter$inal co$ponents such as resistors, capacitors, inductors, and transfor$ers A purely passive load is when either a capacitor or ideal inductor is connected to the load. In this case the current which flows through the generator)load circuit is *+ degrees out of phase and there is no heat generated nor power transferred to the load ele$ents. An NMOS inverter using passive load uses a resistor as a load. A resistor is a passive co$ponent and hence the passive load.

Nmos based inver ckt

Timing waveform

Spice Netlist for Nmos Based Inverter

* SPICE netlist written by S-Edit Win32 7.00 * Written on Nov 11, 2013 at 1 !02! 2

* Wave"or# $robin% &o##ands .$robe .o$tions $robe"ilena#e'()ile e*$1.dat( + $robesdb"ile'(C!,-sers,Natty,.es/to$,tannerE.0,1S$i&e70,)ile e*$1.sdb( + $robeto$#od2le'(3od2le0(

* 3ain &ir&2it! 3od2le0 31 b a 4nd 4nd N35S 6'22 W'222 0.'77$ P.'2 2 0S'77$ PS'2 2 32 8dd 8dd b 4nd N35S 6'22 W'222 0.'77$ P.'2 2 0S'77$ PS'2 2 .tran9o$ 10n 100n #et:od'bd" .in&l2de (C!,-sers,Natty,.es/to$,tannerE.0,#odels,#l2;12<.#d( v1 a 4N. d& < =I1 >?10101010101010@A v2 vdd 4N. < .$rint tran v>aA v>bA .$ower v2 0 100n

* End o" #ain &ir&2it! 3od2le0

Results Power Analysis

Transistor Count

RESULT: The study of transient and dc analysis of NMOS Inverter has !een done.

EXPERIMENT NO. 1.B

AIM: To study transient analysis ,AC analysis and ,c analysis off CMOS Inverter using step
input.

APPARATUS: M-.TISIM * software, PC and power supply. THEORY:

CMOS is also so$eti$es referred to as comp ementa!"#s"mmet!" meta $o%i&e$ semicon&'cto! &or COS MOS'. The words /co$ple$entary sy$$etry/ refer to the fact that the typical digital design style with CMOS uses co$ple$entary and sy$$etrical pairs of p t ype and n type $etal o%ide se$iconductor field effect transistors &MOS01Ts' for logic functions. CMOS circuits are constructed in such a way that all PMOS transistors $ust have either an input fro$ the voltage source or fro$ another PMOS transistor. Si$ilarly, all NMOS transistors $ust have either an input fro$ ground or fro$ another NMOS transistor. The co$position of a PMOS transistor creates low resistance !etween its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied.
B

2hen a low voltage &+ 3' is applied at the input, the top transitor &P type' is conducting &switch closed' while the !otto$ transitor !ehaves li4e an open circuit. Therefore, the supply voltage &5 3' appears at the output. Conversely, when a high voltage &5 3' is applied at the input, the !otto$ transitor &N type' is conducting &switch closed' while the top transitor !ehaves li4e an open circuit. 6ence, the ouput voltage is low &+ 3'. The function of this gate can !e su$$ari7ed !y the following ta!le8 Input Output 6igh .ow .ow 6igh

B B

B B

The output is the opposite of the input this gate inverts the input.

Notice that always one of the transistor will !e an open circuit and no current flows fro$ the supply voltage to ground.

(IR(UIT )IA*RAM:
C#os Inverter

1i#in% Wave"or#

Ces2lt 0nalysis 1ransistor Co2nt

S$i&e Netlist * SPICE netlist written by S-Edit Win32 7.00 * Written on Nov 11, 2013 at 1 !1D!22

* Wave"or# $robin% &o##ands .$robe .o$tions $robe"ilena#e'()ile0.dat( + $robesdb"ile'(C!,-sers,Natty,.es/to$,tannerE.0,1S$i&e70,)ile0.sdb( + $robeto$#od2le'(3od2le0(

* 3ain &ir&2it! 3od2le0 31 = 0 4nd 4nd N35S 6'22 W'222 0.'77$ P.'2 2 0S'77$ PS'2 2 8

32 = 0 8dd 8dd P35S 6'22 W'222 0.'77$ P.'2 2 0S'77$ PS'2 2 .tran9o$ 10n 100n #et:od'bd" .in&l2de (C!,-sers,Natty,.es/to$,tannerE.0,#odels,#l2;12<.#d( v1 a 4N. d& < =I1 >?101010101010@A v2 vdd 4N. < .$rint tran v>aA v>bA .$ower v2 0 100n

* End o" #ain &ir&2it! 3od2le0 Power 0nalysis

EXPERIMENT NO. +
1sti$ation of 9esistance, Capacitance and Inductance (apacitance Estimation In a typical 3.SI chip, the parasitic interconnect capacitances are a$ong the $ost difficult para$eters to esti$ate accurately. 1ach interconnection line &wire' is a three di$ensional structure in $etal and)or polysilicon, with significant variations of shape, thic4ness, and vertical distance fro$ the ground plane &su!strate'. Also, each interconnect line is typically surrounded !y a nu$!er of other lines, either on the sa$e level or on different levels. 0igure :.;; shows a possi!le, realistic situation where interconnections on three different levels run in close pro%i$ity of each other. The accurate esti$ation of the parasitic capacitances of these wires with respect to the ground plane, as well as with respect to each other, is o!viously a co$plicated tas4.

,i-'!e 11: 1%a$ple of si% interconnect lines running on three different levels. -nfortunately for the 3.SI designers, $ost of the conventional co$puter aided 3.SI design tools have a relatively li$ited capa!ility of interconnect parasitic esti$ation. This is true even for the design tools regularly used for su! $icron 3.SI design, where interconnect parasitics were shown to !e very do$inant. The designer should therefore !e aware of the physical pro!le$ and try to incorporate this 4nowledge early in the design phase, when the initial floorplanning of the chip is done. 0irst, consider the section of a single interconnect which is shown in 0ig;<. It is ssu$ed that this wire seg$ent has a length of &l' in the current direction, a width of &w' and a thic4ness of &t'. Moreover, we assu$e that the interconnect seg$ent runs parallel to the chip surface and is separated fro$ the ground plane !y a dielectric &o%ide' layer of height &h'. Now, the correct esti$ation of the parasitic capacitance with respect to ground is an i$portant issue. -sing the !asic geo$etry given in 0ig ;<, one can calculate the parallel plate capacitance Cpp of the interconnect seg$ent. 6owever, in interconnect lines where the wire thic4ness &t' is co$para!le in $agnitude to the ground plane distance &h', fringing electric fields significantly increase the total parasitic capacitance &0ig;='.
10

,i-'!e1+: Interconnect seg$ent running parallel to the surface, used for parasitic capacitance esti$ations.

,i-'!e 1.: Influence of fringing electric fields upon the parasitic wire capacitance. 0igure ;: shows the variation of the fringing field factor 00 > Ctotal)Cpp, as a function of &t)h', &w)h' and &w)l'. It can !e seen that the influence of fringing fields increases with the decreasing &w)h' ratio, and that the fringing field capacitance can !e as $uch as ;+ <+ ti$es larger than the parallel plate capacitance. It was $entioned earlier that the su! $icron fa!rication technologies allow the width of the $etal lines to !e decreased so$ewhat, yet the thic4ness of the line $ust !e preserved in order to ensure structural integrity. This situation, which involves narrow $etal lines with a considera!le vertical thic4ness, is especially vulnera!le to fringing field effects.

11

,i-'!e#1/: 3ariation of the fringing field factor with the interconnect geo$etry. A set of si$ple for$ulas developed !y ?uan and Tric4 in the early ;*@+As can !e used to esti$ate the capacitance of the interconnect structures in which fringing fields co$plicate the parasitic capacitance calculation. The following two cases are considered for two different ranges of line width &w'.

&:.;'

12

&:.<' These for$ulas per$it the accurate appro%i$ation of the parasitic capacitance values to within ;+B error, even for very s$all values of &t)h'. 0igure :.;5 shows a different view of the line capacitance as a function of &w)h' and &t)h'. The linear dash dotted line in this plot represents the corresponding parallel plate capacitance, and the other two curves represent the actual capacitance, ta4ing into account the fringing field effects.

,i-'!e#10: Capacitance of a single interconnect, as a function of &w)h' and &t)h'. Now consider the $ore realistic case where the interconnection line is not CaloneD !ut is coupled with other lines running in parallel. In this case, the total parasitic capacitance of the line is not only increased !y the fringing field effects, !ut also !y the capacitive coupling !etween the lines. 0igure ;E shows the capacitance of a line which is coupled with two other lines on !oth sides, separated !y the $ini$u$ design rule. 1specially if !oth of the neigh!oring lines are !iased at ground potential, the total parasitic capacitance of the interconnect running in the $iddle &with respect to the ground plane' can !e $ore than <+ ti$es as large as the si$ple parallel plate capacitance. Note that the capacitive coupling !etween neigh!oring lines is increased when the thic4ness of the wire is co$para!le to its width.

13

,i-'!e#11: Capacitance of coupled interconnects, as a function of &w)h' and &t)h'. 0igure ;F shows the cross section view of a dou!le $etal CMOS structure, where the individual parasitic capacitances !etween the layers are also indicated. The cross section does not show a MOS01T, !ut Gust a portion of a diffusion region over which so$e $etal lines $ay pass. The inter layer capacitances !etween the $etal < and $etal ;, $etal ; and polysilicon, and $etal < and polysilicon are la!eled as C$<$;, C$;p and C$<p, respectively. The other parasitic capacitance co$ponents are defined with respect to the su!strate. If the $etal line passes over an active region, the o%ide thic4ness underneath is s$aller &!ecause of the active area window', and conse(uently, the capacitance is larger. These special cases are la!eled as C$;a and C$<a. Otherwise, the thic4 field o%ide layer results in a s$aller capacitance value.

,i-'!e#12: Cross sectional view of a dou!le $etal CMOS structure, showing capacitances !etween layers. The vertical thic4ness values of the different layers in a typical +.@ $icron CMOS technology are given !elow as an e%a$ple.
14

0ield o%ide thic4ness Hate o%ide thic4ness Poly ; thic4ness Poly $etal o%ide thic4ness Metal ; thic4ness 3ia o%ide thic4ness Metal < thic4ness nI Gunction depth pI Gunction depth n well Gunction depth

+.5< ;E.+ +.=5 +.E5 +.E+ ;.++ ;.++ +.:+ +.:+ =.5+

u$ n$ u$ u$ u$ u$ u$ u$ u$ u$

&$ini$u$ width +.@ u$' &$ini$u$ width ;.: u$' &$ini$u$ width ;.E u$'

The list !elow contains the capacitance values !etween various layers, also for a typical +.@ $icron CMOS technology. Poly over field o%ide Poly over field o%ide Metal ; over field o%ide Metal ; over field o%ide Metal < over field o%ide Metal < over field o%ide Metal ; over poly Metal ; over poly Metal < over poly Metal < over poly Metal < over $etal ; Metal < over $etal ; &area' &peri$eter' &area' &peri$eter' &area' &peri$eter' &area' &peri$eter' &area' &peri$eter' &area' &peri$eter' +.+EE +.+:E +.+=+ +.+:: +.+;E +.+:< +.+5= +.+5; +.+<; +.+:5 +.+=5 +.+5; f0)u$< f0)u$ f0)u$< f0)u$ f0)u$< f0)u$ f0)u$< f0)u$ f0)u$< f0)u$ f0)u$< f0)u$

0or the esti$ation of interconnect capacitances in a co$plicated three di$ensional structure, the e%act geo$etry $ust !e ta4en into account for every portion of the wire. ?et this re(uires an unaccepta!le a$ount of co$putation in a large circuit, even if si$ple for$ulas are applied for the calculation of capacitances. -sually, chip $anufacturers supply the area capacitance &parallel plate cap' and the peri$eter capacitance &fringing field cap' figures for each layer, which are !ac4ed up !y $easure$ent of capacitance test structures. These figures can !e used to e%tract the parasitic capacitances fro$ the $as4 layout. It is often prudent to include test structures on chip that ena!le the designer to independently cali!rate a process to a set of design tools. In so$e cases where the entire chip perfor$ance is influenced !y the parasitic capacitance of a specific line, accurate = , si$ulation is the only relia!le solution.

15

0 Inte!connect Resistance Estimation The parasitic resistance of a $etal or polysilicon line can also have a profound influence on the signal propagation delay over that line. The resistance of a line depends on the type of $aterial used &polysilicon, alu$inu$, gold ...', the di$ensions of the line and finally, the nu$!er and locations of the contacts on that line. Consider again the interconnection line shown in 0ig;<. The total resistance in the indicated current direction can !e found as

&:.<' where the gree4 letter ro represents the characteristic resistivity of the interconnect $aterial, and 9sheet represents the sheet resistivity of the line, in &oh$)s(uare'. 0or a typical polysilicon layer, the sheet resistivity is !etween <+ :+ oh$)s(uare, whereas the sheet resistivity of silicide is a!out < : oh$)s(uare. -sing the for$ula given a!ove, we can esti$ate the total parasitic resistance of a wire seg$ent !ased on its geo$etry. Typical $etal poly and $etal diffusion contact resistance values are !etween <+ =+ oh$s, while typical via resistance is a!out +.= oh$s. In $ost short distance alu$inu$ and silicide interconnects, the a$ount of parasitic wire resistance is usually negligi!le. On the other hand, the effects of the parasitic resistance $ust !e ta4en into account for longer wire seg$ents. As a first order appro%i$ation in si$ulations, the total lu$ped resistance $ay !e assu$ed to !e connected in series with the total lu$ped capacitance of the wire. A $uch !etter appro%i$ation of the influence of distri!uted parasitic resistance can !e o!tained !y using an 9C ladder networ4 $odel to represent the interconnect seg$ent &0ig;@'. 6ere, the interconnect seg$ent is divided into s$aller, identical sectors, and each sector is represented !y an 9C cell. Typically, the nu$!er of these 9C cells &i.e., the resolution of the 9C $odel' deter$ines the accuracy of the si$ulation results. On the other hand, si$ulation ti$e restrictions usually li$it the resolution of this distri!uted line $odel.

,i-'!e#13: 9C ladder networ4 used to $odel the distri!uted resistance and capacitance of an interconnect.

16

IN,-CTANC18
A E+ H67 cross coupled differential .C CMOS 3CO is presented in this paper, which is opti$i7ed for a large fre(uency tuning range using conventional MOS01T varactors. The MMIC < is fa!ricated on digital *+ n$ SOI technology and re(uires a circuit area of less than +.; $$ including the 5+ output !uffers. 2ithin a fre(uency control range fro$ 5<.= H67 to E+.E H67, a supply voltage of ;.5 3 and a supply current of ;: $A, the circuit delivers a very constant output power of JE.@ +.< dK$ and yields a phase noise !etween J@5 to *< dKc)67 at ; M67 fre(uency offset. INT9O,-CTION8 Over the last years, the speed gap !etween leading edge III)3 and CMOS technologies has !een significantly decreased. Today, SOI CMOS technologies allow the efficient scaling of the transistor gate length resulting in a ft and f$a% of up to <:= H67 and <+@ H67, respectively L; <M. This $a4es the reali7ation of analog CMOS circuits at $icrowave fre(uencies possi!le leading to pro$ising $ar4et perspectives for co$$ercial applications. Circuits such as a <E :< H67 low noise a$plifier L=M and a =+ :+ H67 $i%er L:M have !een reali7ed de$onstrating the suita!ility of SOI CMOS technologies for analog applications at $illi$eter wave fre(uencies. To the !est 4nowledge of the authors, the highest oscillation fre(uency of a CMOS 3CO reported to date is 5; H67 L5M. The circuit uses +.;< $ !ul4 technology and has !een opti$i7ed for a high oscillation fre(uency. Since high oscillation fre(uency and high tuning range are contrary goals, the achieved tuning range at fi%ed supply voltage of ;.5 3 is less than ;.5B. ,ue to the high process tolerances of aggressively scaled CMOS technologies, the oscillation fre(uency can significantly vary co$pared to the no$inal value. Thus, in practice, a $uch higher tuning range is desired to allow a co$pensation of these variations. A :+ H67 SOI CMOS 3CO with ;.5 3 supply voltage, a phase noise of *+ dKc)67 at ; M67 offset and a high tuning range of *B has !een reported LEM. The high tuning range is achieved !y applying special accu$ulation MOS varactor diodes having a high capacitance control range c9 > Cv$a%)Cv$in of E LFM. These varactors re(uire additional processing steps $a4ing the technology $ore e%pensive. An off chip !ias T is re(uired for the !uffer a$plifier to $ini$i7e the loading of the oscillator core. TAK.1 ICOMPA9ISON 2IT6 STAT1 O0 T61 Center Tuning Phase noise fre(uency range N;M67 offset SiHe 6KT)ft>;<+H67 :=H67 ;;.@B *EdKc 5;H67 <B @5Kc)67 +.;< $ CMOS)n.a. :+H67 *B *+dKc)67 +.;= $ SOI CMOS)f$a%>;E@H67 *+n$ SOI 5FH67 ;EB *+dKc)67 CMOS)f$a%>;E+H67 E+H67 ;:B *:dKc)67 Technology) Speed A9T 3COs Supply power =3 ;<;$A ;.53 E.5$A ;.53 F.5$AO ;.53 ;:$A ;.<3 @$A 9ef. L@M L5M LEM This wor4

17

In this paper, a fully integrated E+ H67 SOI CMOS 3CO is presented, which applies conventional MOS01T varactors. To allow process variations and high yield, the circuit is opti$i7ed for high fre(uency tuning range. Target applications are co$$ercial wide!and 2.AN and optical transceivers operating around E+ H67. ,espite the high oscillation fre(uency, which to the !est 4nowledge of the authors is the highest reported to date for a CMOS !ased oscillator, a high tuning range of $ore than ;+ B is achieved with varactors having a c9 of only <. A co$parison with recently reported silicon !ased 3COs is given in TAK.1 I. II. T1C6NO.OH? The 3CO was fa!ricated using a *+ n$ IKM 3.SI SOI CMOS technology featuring a $etal stac4 with @ $etal layers. A thin isolation layer !etween the active region and the su!strate allows a relatively high su!strate resistivity of ;=.5 5 c$ without increasing the threshold voltages 3th of the 01Ts re(uired for digital applications. Thus, relatively high P factors and operation fre(uencies can !e achieved for the passive devices, which are $andatory for analog applications and oscillators. The possi!ility of highly integrated single chip solutions $a4es this technology well suited for future co$$ercial applications.

18

EXPERIMENT NO. .
M-.TIP.1Q198
In electronics, a $ultiple%er or $u% &occasionally the ter$s $ulde% or $ulde$ are also found for a co$!ination $ultiple%er de$ultiple%er' is a device that perfor$s $ultiple%ingR it selects one of $any analog or digital input signals and forwards the n selected input into a single line. A $ultiple%er of < inputs has n select lines, which are used to select which input line to send to the output.

An electronic $ultiple%er $a4es it possi!le for several signals to share one device or resource, for e%a$ple one A), converter or one co$$unication line, instead of having one device per input signal. On the other end, a de$ultiple%er &or de$u%' is a device ta4ing a single input signal and selecting one of $any data output lines, which is connected to the single input. A $ultiple%er is often used with a co$ple$entary de$ultiple%er on the receiving end. An electronic $ultiple%er can !e considered as a $ultiple input, single output switch, and a de$ultiple%er as a single input, $ultiple output switch. The sche$atic sy$!ol for a $ultiple%er is an isosceles trape7oid with the longer parallel side containing the input pins and the short parallel side containing the output pin. The sche$atic on the right shows a < to ; $ultiple%er on the left and an e(uivalent switch on the right. The sel wire connects the desired input to the output.

0unctional coding for Multiple%er

$odule $u%;&out,a,!,sel'R input aR input !R inputselR output outR wirenotselR wire y+,y;R not g+&notsel,sel'R
19

and g;&y+,a,notsel'R and g<&y;,!,sel'R or g=&out,y+,y;'R end$odule

0unctional coding for ,e$ultiple%er8

In teleco$$unications, a $ultiple%er is a device that co$!ines several input infor$ation signals into one output signal, which carries several co$$unication channels, !y $eans of so$e $ultiple% techni(ue. A de$ultiple%er is in this conte%t a device ta4ing a single input signal that carries $any channels and separates those over $ultiple output signals.

In teleco$$unications and signal processing, an analog ti$e division $ultiple%er &T,M' $ay ta4e several sa$ples of separate analogue signals and co$!ine the$ into one pulse a$plitude $odulated &PAM' wide !and analogue signal. Alternatively, a digital T,M $ultiple%er $ay co$!ine a li$ited nu$!er of constant !it rate digital data strea$s into one data strea$ of a higher data rate, !y for$ing data fra$es consisting of one ti$eslot per channel. In teleco$$unications, co$puter networ4s and digital video, a statistical $ultiple%er $ay co$!ine several varia!le !it rate data strea$s into one constant !andwidth signal, for e%a$ple !y $eans of pac4et $ode co$$unication. An inverse $ultiple%er $ay utili7e several co$$unication channels for transferring one signal.

0unctional coding for ,e$ultiple%er8

Module de$u%&y+,y;,y<,y=,s+,s;,d'R input s+,s;,dR output y+,y;,y<,y=R not &s+!ar,s+'R

20

not &s;!ar,s;'R and &y+,d,s+!ar,s;!ar'R and &y;,d,s+!ar,s;'R and &y<,d,s+,s;!ar'R and &y=,d,s+.s;'R end$odule

,ecoder
A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original infor$ation can !e retrieved. The sa$e $ethod used to encode is usually Gust reversed in order to decode. In digital electronics, a decoder can ta4e the for$ of a $ultiple input, $ultiple output logic circuit that converts coded inputs into coded outputs, where the input and output n codes are different. e.g. n to < , !inary coded deci$al decoders. 1na!le inputs $ust !e on for the decoder to function, otherwise its outputs assu$e a single /disa!led/ output code word. ,ecoding is necessary in applications such as data $ultiple%ing, F seg$ent display and $e$ory address decoding. The e%a$ple decoder circuit would !e an AN, gate !ecause the output of an AN, gate is /6igh/ &;' only when all its inputs are /6igh./ Such output is called as /active 6igh output/. If instead of AN, gate, the NAN, gate is connected the output will !e /.ow/ &+' only when all its inputs are /6igh/. Such output is called as /active low output/.

1%a$ple8 A < to : .ine Single Kit ,ecoder A slightly $ore co$ple% decoder would !e the n to < type !inary decoders. These type of decoders are co$!inational circuits that convert !inary infor$ation fro$ #n# coded inputs to a n n $a%i$u$ of < uni(ue outputs. 2e say a $a%i$u$ of < outputs !ecause in case the n #n# !it coded infor$ation has unused !it co$!inations, the decoder $ay have less than < outputs. 2e can have < to : decoder, = to @ decoder or : to ;E decoder. 2e can for$ a = to @ decoder fro$ two < to : decoders &with ena!le signals'. Si$ilarly, we can also for$ a : to ;E decoder !y co$!ining two = to @ decoders. In this type of circuit design, the ena!le inputs of !oth = to @ decoders originate fro$ a :th input, which acts as a selector !etween the two = to @ decoders. This allows the :th input to ena!le either the top or !otto$ decoder, which produces outputs of ,&+' through ,&F' for the first decoder, and ,&@' through ,&;5' for the second decoder.
21 is also 4nown as a decoder de$ultiple%er. A decoder that contains ena!le inputs
n

Thus, we have a : to ;E decoder produced !y adding a :th input shared a$ong !oth decoders, producing ;E outputs.

0unctional coding for ,ecoder8

Module dec&d, a, !, e'R outputL=8+M dR input aR input !R input eR wire a!ar,!!ar,e!arR not n;&a!ar,a'R not n<&!!ar,!'R not n=&e!ar,e'R nand n:&dL+M,a!ar,!!ar,e!ar'R nand n5&dL;M,a!ar,!,e!ar'R nand nE&dL<M,a,!!ar,e!ar'R nand nF&dL=M,a,!,e!ar'R end$odule ,igital co$parator A digital co$parator or $agnitude co$parator is a hardware electronic device that ta4es two nu$!ers as input in !inary for$ and deter$ines whether one nu$!er is greater than, less than or e(ual to the other nu$!er. Co$parators are used in a central processing units &CP-' and $icrocontrollers. 1%a$ples of digital co$parator include the CMOS :+E= and :5@5 and the TT. F:@5 and F:E@< #@*. The analog e(uivalent of digital co$parator is the voltage co$parator. Many $icrocontrollers have analog co$parators on so$e of their inputs that can !e read or trigger an interrupt. Co$parator truth ta!les inputs A + + ; ; K + ; + ; Outputs ASK + ; + + + ; A>K ; + + ; + ATK +

The operation of a two !it digital co$parator can !e e%pressed as a truth ta!le

0unctional coding for COMPA9ATO98

22

$odule progra$ :&A,K,AltK,Ae(K,Agt K'R inputL=8+MA,KR output AltK,Ae(K,Agt KR reg Alt K,Ae(K,Agt KR always N&A or K' !egin Alt KS>&ASK'R Ae( KS>&A>>K'R Agt KS>&ATK'R end end$odule $odule co$p &%,y,7,a,!'R inputa,!R output %,y,7R reg %R reg yR reg 7R always N&aor!' !egin *E'1Fb0G yE1Fb0G HE'1Fb0G if &a>>!' *E'b1G else if &aT!' yE'1Fb1G else if &aS!' HE'1Fb1G end end$odule

9esult8

23

EXPERIMENT No. /
Analytical Modeling and si$ulation +of I 3 characteristics of a p channel)n channel MOS01T Ai$8To study the I8 C:annel C:ara&teristi&s o" P&:annel9N &:annel 3os"et
0$$arat2s CeI2ired! 3i&rowind, PC, Power S2$$ly. 1:eory! 35S)E1! layo2t, &ross-se&tion, sy#b ols

Jey ele#ents! K inversion layer 2nder %ate >de$ endin% on %ate volta%eA K :eavily-do$ ed re%ions rea&: 2nderneat: %ate in-version layer ele&tri&ally &onne&ts so2r&e and drain K -ter#inal devi&e! bod y volta%e i#$ ortant Cir&2it sy#b ols 1wo &o#$le#entary devi&es! K n-&:annel devi&e >n-35S)E1A on $-Si s2bstrate 24

>2ses ele&tron inversion layerA K $-&:annel devi&e >$-35S)E1A on n-Si s2bstrate >2ses :ole inversion layerA

I-8 &:ara&teristi&s 4eo#etry o" $roble#!

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60L5-1

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I8 C:ara&teristi&s

I8 2

9esult8

27

EXPERIMENT No. 0
3odelin% and Si#2lation o" N35S M C35S &ir&2its 2sin% S$i&e 0i#! 1o 3odel and si#2late N35S M C35S &ir&2its 2sin% S$i&e. 0$$arat2s reI2ired! S$i&e si#2lation So"tware, PC, Power s2$$ly. 1:eory. 1:e N35S M C35S &ir&2its are #odelled and si#2lated 2sin% t:e s$i&e si#2lation so"tware tool. 8ario2s $ara#eters :as been analyHed as a res2lt o" si#2lation. S&:e#ati& .ia%ra#!

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0nalysis

29

Net ist ! SPIC" netlist written by S#"dit $in%& '()) ! $ritten on Nov *&+ &)*% at *,-&%-%%

! $aveform probing commands (probe (options probefilename./0ilee1pnan(dat/ 2 probesdbfile./C-34sers3Natty35esktop3tanner"5A3TSpice')30ilee1pnan(sdb/ 2 probetopmodule./6odule)/

! 6ain circuit- 6odule) 6* N' B 7nd N8 N69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u 6& 9ut A N' N& N69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u 6% 9ut A ;dd N< P69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u 6, 9ut B ;dd N, P69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u (tran=op *)n *))n met>od.bdf (include /C-34sers3Natty35esktop3tanner"5A3models3ml&?*&<(md/ v* a 7N5 dc < BIT @A*))*)*))*BC v& b 7N5 dc < BIT @A*))*)*))*BC v% vdd 7N5 < (print tran v@aC v@bC v@outC ! "nd of main circuit- 6odule)

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Ces2lt

31

1QP19IM1NT NO E Modeling and analysis of MOS capacitor S$all signal Analysis Ai$8 To Model and analy7e the s$all signal analysis of MOS Capacitor. Apparatus 9e(uired8 Microwind, Power Supply, PC Sc4ematic )ia-!am:

32

.ayout of the circuit

Analysis of Capacitance

33

3erilog Code for capacitance o!tained8 $odule c$osNand<& A,K,Nand<'R input A,KR output Nand<R n$os U&;<;' n$os&Nand<,w;,A'R )) ;.+u +.;<u p$os U&;<;' p$os&Nand<,vdd,A'R )) <.+u +.;<u p$os U&;<;' p$os&Nand<,vdd,K'R )) <.+u +.;<u n$os U&;+F' n$os&w;,vss,K'R )) ;.+u +.;<u end$odule

)) Si$ulation para$eters in 3erilog 0or$at always U;+++ A>VAR U<+++ K>VKR

)) Si$ulation para$eters )) A C.W ;+ ;+ )) K C.W <+ <+

9esult8

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