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VLSI TEST AND MEASUREMENT

EE 274
Lecture 1 and 2 : Test: An overview
Khosrow Ghadiri
Electrical Engineering Department
San Jose State University
Khosrow Ghadiri
Outline
Testing and diagnosis
Level of abstraction
Reliability and testing
Design Process
Verification & testing
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EE Dept. SJSU
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Verification & testing
Faults and their detection
Fault coverage
Types of tests
Test applications
Design for Test
Test economics
Reliability and Testing
Reliability of electronics systems is no longer
limited to military, aerospace and banking
They are ubiquitous in the workplace
Used by almost everyone
Khosrow Ghadiri VLSI Design for Testability
EE Dept. SJSU
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Made of smaller and smaller devices
Have continually new failure modes
Reliability depending on being error free
Failures in both software and hardware
Here we concentrate on hardware
Testing and diagnosis
Testing of a system is an experiment in which the system is
exercised and a resulting response is analyzed to ascertain
whether it behaved correctly.
If incorrect behavior is detected, a second goal of a testing
experiment may be to diagnose, or locate, the cause of the
misbehavior.
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misbehavior.
Diagnosis assumes knowledge of the internal structure of the
system under the test.
The subject of this course is testing and diagnosis of VLSI
circuits with emphasis on digital systems. "Digital system"
denotes a complex digital circuit.
The complexity of a circuit is related to the level of
abstraction required to describe its operation in a meaningful
way.
Level of abstraction
The level of abstraction of digital system can be roughly
characterized by the type of information processed by
the circuit.
Control Data Level of abstraction
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Logic values ( or sequences of
logic values)
Logic level
Logic values
instructions
Words
Words
Programs
Data
structures
Messages
Register level
Instruction set level
Processor level
Systemlevel
Logic level
Although a digital circuit can be viewed as processing analog
quantities such as voltage and current, the lowest level of
abstraction we will deal with is the logic level.
The information processed at this level is represented by
discrete logic values.
The classical representation uses binary values (0 and I)
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The classical representation uses binary values (0 and I).
More accurate models, however, often require more than two
logic values.
A further distinction can be made at this level between
combinational and sequential circuits.
Unlike a combinational circuit, whose output logic values
depend only on its present input values, a sequential circuit
can also remember past values, and hence it processes
sequences of logic values.
2
Design Cycle
Design cycle
Concept
Behavioral
Description
Behavioral
Synthesis
MaskData
Layout
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EE Dept. SJSU
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RTL Description
LogicSysnthesis
GateDescription
TechnologyMapping
Floor Planning
Technology
Dependent Network
Product
Testing
Goodproduct
Manufacturing
Shrinking Design Cycle
Shrinking design cycle
Time
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EE Dept. SJSU
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System
Logic
Physical
1985 1995 1990
A System on a Chip
SoC
Controller
(algorithm)
RAM
Interface Block
(RT Level )
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RAM
U
D
L
UDL
DSP
(Netlist)
Micropro.
(Layout)
FPGA
Hardware Design
Hardware design done on paper in the past.
Now, Hardware design is described in HDL
(Hardware description Language)
Advantages:
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Management of complexity, Most viable
design
Shortening of design cycle.
Testing
Verification and Testing
Testing a circuit prior to fabrication is known as design
verification
Verification is certainly done at various stages of the
design process as shown before
Most viable design verification is simulation ideally
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g y
formal verification
Testing is identifying that the fabricated circuit is free
from errors
Need to specify what errors testing is looking for
DFT Cycle
DFT cycle
Behavioural
Description
Behavioral
DFT
Synthesis
RTL Description
Technology
Mapping
Layout
Gate
Libraries
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Logic
DFT
Synthesis
GateDescription
Test Pattern
Generation
Fault
Coverage?
Manufacturing
GoodProduct
Test Application
Product
Parameter
Extraction
Libraries
low high
3
Faults and their Detection
Physical failures are manifested as electrical failure and
are interpreted as faults on the logic level
Physical defects will be discussed in chapter 2
Several physical defects may be mapped into fewer or
even one fault type
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yp
The main fault used in digital circuit is the infamous
Stuck-at Fault
A fault is detected by a test pattern
This is an input combination the confirm the presence of
the fault
Possible Defects
Z
B
A
R1
R
L
Z
A
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EE Dept. SJSU
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Two technologies, two physical defects map into the
same stuck-at zero fault
Also, A SA0, or A/0
R1
R2 B
A
Z
A Z
(a)
(b)
Detecting Stuck-at Faults
Detecting SA fault
A
B
Z
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Inputs FF Faulty Response
AB Response A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1
Detecting Stuck-at Faults
SA Faults: AND example
A
B
Z
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Collapsed fault list = {A/0, A/1, B/1}
Inputs Fault Free Faulty Responses
AB Response A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1
Sequential Circuit
Sequential
R
S
Q
A
1
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S
2
Inputs FF Faulty Response
SR Response A/0 S/0 R/0 A/1 S/1 R/1
01 0 0 0 X 0 0 1
00 0 1 0 X 1 0 1
10 1 1 0 1 0 1 1
11 0 0 0 1 1 1 1
Types of Tests
The exhaustive test used to detect the faults
on a 2-input AND gate is not practical for
circuits with 20 or more primary inputs
Pseudoexhaustive: exhaustive for components
i th i it
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EE Dept. SJSU
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in the circuits
segmentation or partitioning
A random test is also viable to detect faults,
but pseudo-exhaustive tests are more realistic
Stuck-at Faults
Deterministic or fault oriented tests
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Circuit Segmentation
Exhaustive: 6 inputs
26 = 64 patterns
Pseudoexhaustive:
a 22 = 4
A
B
R
Z1
o
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EE Dept. SJSU
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b 23 = 8
c 23 = 8
Total = 20
saving 44/64 = 69%
Reliability and testing
H
E
C
G
F
D
W
V

Z2
|
Test evaluation - Fault coverage
An important problem in testing is test evaluation, which
refers to determining the effectiveness, or quality, of the
test.
The effectiveness of a test set is quantifiable.
It is the percentage of the faults detected by a test and is
known as the Fault coverage
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EE Dept. SJSU
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known as the Fault coverage.
A more realistic expression is:
Where detectable fault =all faults untestable faults.
Fault detected
Fault coverage
Total #of faults
=
Fault detected
Fault coverage
Detectablefaults
=
PRTPG: an LFST
Reliability and testing
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EE Dept. SJSU
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Q
Q D
Q
Q D
Q
Q D
1
2 3
Test Application
Off-chip and on-chip testing
Off chip: requires expensive testers
On chip: uses the embedded testing technique
On chip may also be done during normal operation of the
circuit: on-line testing
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circuit: on line testing
On Line Testing
On line testing
Circuit Under
Encoded
Output
N
N
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Test
Checker
N
P
On- vs Off-Chip Testing
On- vs off-chip testing
HighBandwidth
LowBandwidth
HighBandwidth
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Analog
Logic
RAM
Embeddedtest External test
Source/
sink
Logic
RAM
Analog
Embeddedtest External test
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Test Economics
High quality requires a large investment in time and
money.
The life cycle of a product is shorter than its design cycle
Time to market need thus to be shorten
Testing is necessary for reliability and for improving yield
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EE Dept. SJSU
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Testing is necessary for reliability and for improving yield
Disciplined design to facilitate testing is know as design
for test (DFT)
Time to Market
Revenue loss due to a delay in arrival of the product to
market.
T A
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EE Dept. SJSU
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Timein Months
R
e
v
e
n
u
e
s
AT
Timeto
Market
Loss of
Revenues
Revenue peak
Yield
The yield Y of IC manufacturing is defined as:
It is hard to find exact value of Y because:
Lack of data for a part once they are sold
#
# #
G
Y
G B
=
+
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EE Dept. SJSU
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Lack of data for a part once they are sold
Lack of possibility to test all chip
Test may pass as good, bad chip (miss the fault not
modeled)
Many factor effect the yield:
Die area of wafer
Process maturity
# of process steps
Yield mathematical models
Murphy yield model:
where A is the area, D is defect density.
The defect level is the fraction of the bad chip that passed
1
AD
e
Y
AD

=
L A
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EE Dept. SJSU
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the test. Measured in defect per million (DPM) thus a defect
level of 0.1% is equivalent to 1000 DPM.
Williams model:
Where t is the fault coverage of functional test used.
For small DL of less than 1000 DPM
where TT=1-T is the testing transparency
( ) 1 1 DL Y T =
( ln ) DL TT Y =
Yield and Defect Level
Yield and Defect Level.
Defect Level
1
% DPM
10000
5000
Y=50% Y=90%
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EE Dept. SJSU
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0.1
0.01
0.001
TT%
1000
500
100
50
10
.01 0.1 1 10
99.99 99.9 99 90 C%
Yield and Fault Coverage
Yield and Fault Coverage.
20
25
30
L
e
v
e
l
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EE Dept. SJSU
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0
5
10
15
0 10 20 30 40 50 60 70 80 90 100
Fault Coverage
D
e
f
e
c
t

L