International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 9 pp 583-589 December 2013 www.ijsret.org ISSN 2278 0882

NBTI INDUCED CLOCK SKEW REDUCTION IN GATED CLOCK TREES

M. FARJANAAMEERA M.E VLSI Asst. Prof. K. VENKATESAN SIET, Coimbatore.

Abstract: Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show stoppers of circuit reliability in nanometre scale devices due to its deleterious effects on transistor threshold voltage. Interface traps are electrically active physical defects. Interface traps are formed due to crystal mismatches at the Si-Sio2 interface. During oxidation of Si, most of the tetrahedral Si atoms bonds to the formation of weak Si-H bonds, thereby generating interface traps. They are manifested as an increase in absolute PMOS transistor threshold voltage and a reduction in absolute Ion current of PMOS devices making them slower. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits proven to be a growing threat to circuit reliability in nanometer scale technology. The variation in temperature and threshold voltage leads to a phenomenon called NBTI. Clock gating impacts the extent of NBTI induced Vth degradation and, thus increased clock buffers leading to no uniform NBTI degradation and thus increased clock skew. So here we propose a system of the clock gating implementation by selecting NAND or NOR gate as output stage of integrated clock gating cells with the objective of minimizing NBTI induced clock skew. An experimental result shows that, the NBTI induced clock skew is minimized more than up to74%. The main aim is to reduce the delay variation by the clock skew induced due to NBTI and increase the device performance and efficiency.

I.

INTRODUCTION

Negative Bias Temperature Instability (NBTI) is a key reliability problem in MOSFETs. NBTI provide evidenceas an increase in the threshold voltage and continuous decreases in drain current and Trans conductance of a MOSFET. The degradation use of logarithmic dependence on time. Here, P- channel MOS devices concerns no delay. Since they almost operate

with negative gate to source voltage, it also affects NMOS transistors when biased in the accumulation. Those traps cannot be recovered over a reasonable time of operation. There are some permanent traps. Those traps are created by channel hot carrier. In the case of NBTI, the electric field is able to break Si-H bonds located at the silicon oxide interface. H is released in the substrate where it moves. The remaining dangling bonds Si - (Pbcenter) offers the particular quality to the threshold voltage degradation.Negative Bias Temperature Instability (NBTI) has concealed as a major reliability challenge for the semiconductor industry in recent years. NBTI impact is getting worse in each technology generation with greater performance and reliability loss. When a negative voltage is applied at a p-channel transistor (PMOS) gate, interface traps are formed near oxide layer, causing a change in transistor characteristics. When the input to a PMOS is low (logic zero), the transistor is in a difficulty phase. During the stress phase, the transistor parameters slowly deviate from the nominal value. When the input to the PMOS is high (logic one), the transistor is in a recovery phase. During the recovery phase, trapped charges are released, regaining the original transistor state. The PMOS enters into stress and recovery phases alternately, when the input to the PMOS is dynamic.Reference [6] noted that stressing a device even for1% of the time followed by recovery phase for 99% of the timeis still sufficient to slowly build up interface charge. However, the recovery phase is very important to be considered for thecorrect estimation of the NBTI effect. The lifetime estimation of NBTI without considering the recovery phase can be anorder of magnitude lower than the actual value [7]. To account for the relative time of stress and recovery phases caused ina PMOS device due to its input, it is common to analyse the signal probability of the input pin. Since the NBTI effect happens due to negative bias (i.e., input gate voltage at logicLOW), we are interested in tracking probability that a given signal is at logic LOW. In the remainder of this paper, for any signal we

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 9 pp 583-589 December 2013 www.ijsret.org ISSN 2278 0882

will denote the probability of a signal to be at logicLOW as SP, for simplicity.In recent times, due to several effects such as parametric variation, lack of high-quality interconnect models and environment factors such as spatial temperature variation, maintaining low clock skew has become a challenge. The challenge is to come up with schemes such that all the path delays can be made as close to each other as possible, thus maximizing frequency of operation.Typically, integrated clock gating (ICG) cells are inserted in the design, which conceptually are composed of a latch followed by AND/ORgate. The presence of latch avoids glitches and premature ending of clock signal. When using the NAND gate as the output stage of ICG, the value coming out of latch should be the controlling value, i.e., logic LOW. Similarly,when using the NOR gate at the output stage of ICG, thecontrolling value of logic HIGH needs to come out of latch. Asthe clock signal switches every cycle, the PMOS devices in clock buffer experience alternate stress and recovery phases of equal duration. However, PMOS devices that are part of heavily gated clock buffers do not experience stress and recovery for equal durations.

(such as intrinsic delay and input gate capacitance) of the NAND and NOR gates, the clock path delays may need to be tweaked by appropriate sizing of the NAND /NOR gates and moving the merging point of clock routing. For minute delay differences, techniques such as interconnect snaking can be applied if it does not introduce congestion. A consider the clock tree shown in Figure 3.1where the shaded subtree is currently gated by active low GATE signal. As a result of this, though the PMOS device inside a nongated clock buffer experiences alternate NBTI stress and recovery cycles, the PMOS inside a gated buffer undergoes constant stress. This may cause increase in skew of the whole clock tree. Also of importance is the workload-dependent temporal variation in the temperature of the clock buffers. Due to strong dependence of the NBTI effect on duty cycle and temperature, the study of its impact on skew degradation of clock tree is strongly mandated.

II.

PROPOSED WORK

1. DESIGN FLOW The aim of the proposed design technique is to reduce the skew of a clock tree arising due to the asymmetry in the VTH degradation of the clock buffers. This asymmetry is due to difference in probability of signal to be at logic LOW (SP)at different parts of the clock tree due to clock gating. The use of both NAND and NOR gates (instead of just one of them) to implement clock gating is proposed here. Using NAND (NOR) gate to shut down the clock allows freezing the clock tree at logic HIGH (LOW), thus decreasing (increasing) the SP for all clock buffers in the fanout cone. By intelligently choosing which gate to use for each clock gating element, the SP of the clock tree can be modulated to reduce the clock skew. The input to this technique is a clock tree construct using inverters or buffers. Using RTL simulation, clock gating opportunities at some of the clock inverters are identified. In traditional clock gating, these inverters would be replaced by ICGs with NAND gates at their output stage with the second input of NAND gate tied to active LOW clock gating enable signal. However, in this approach some of these ICGs were replaced with those that neither have NOR gate at their output stage. Owing to the different characteristics

Figure 3.1 Clock gating Consider the clock tree shown in Fig. 3.2 that drives four latches. The clock tree nodes (represented as inverters indexed by the name under it) that have clock gating ability are circled and referred to as gated nodes. The nominal skew of the clock tree is zero due to symmetry. For the gated nodes, the probability of clock gating (G) of each node is also shown. A value of G = 0 implies that this particular node inever gated, whereas G = 1 means that clock is always gated. Assuming 50% duty cycle of clock at input (i.e., Sin= 0.5), we computed the skew at clock tree leaves using HSPICE after aging the circuit by 10 years. When all the gated nodes areimplemented as NAND -gated ICGs, the skew of the clock tree is 1 .90ps, whereas for a configuration of all- NOR-gated ICGs,theclock skew is 1.36 ps. The best configuration is obtainedwhen N2 = NOR,N3= NOR,N5= NAND with a value of skewof only 0 .16 ps, a reduction of almost

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 9 pp 583-589 December 2013 www.ijsret.org ISSN 2278 0882

90%. This neither proves that simply choosing all gates as NAND or all gates as NORis not the right choice.

ability), the output SP is trivially equal to(1 S). Let us assume the delay of an INV, NAND, and NORgateis DINV(S, G), DNAND(S, G), and DNOR(S, G), respectively,which are functions of the switching probability (S) and clock. Table 3.1 Formulation of gates to calculate delay

Figure 3.2 Clock Inverter Based Clock gating in clock tree. In this section, the ground rules are setup for propagation of SP and delay when implementing clock gating through NAND or NOR gates. The probability of a signal to be atlogic LOW is denoted by SP. Consider a clock tree invertershown on the left-hand side in Figure 3.3 the input SP of the inverter is S and the probability of clock gating is G. If this inverter is replaced by a NAND -gated ICG, the SP of the clock gating signal would be G itself because logic LOW is the controlling value for NAND. In such a scenario, the output SP of the NAND gate is (1 G)*(1 S).

Figure 3.4 Calculations of Signal Probability and Delay If X = 1, the delay of the cell is DNAND(S, G), else it is DNOR(S, G). Delay of aclock inverter that does not clockgating capability is simply DINV(S, G). Table 3.1 summarizesthese observations that are used for propagating the symbolicSP and delayvalues through the clock tree from the root tothe clock leaves.The information from table 3.1 can be combined to get thefollowing expression for the output SP and delay through aclock gating enabled gate in terms of the binary variable X: SPout = 1+S G S X G D = X DNAND(S,G)+X DNOR(S,G) (1) Important properties of the delay expression ofany gate, which will help make the ILP formulation tractablelater in this paper. Lemma 1: Signal probability of any gate is at most a linearfunction of X. Proof: If input signal probability, S, is linearOr constant in X then output SPoutis also linear since Gis a constant. As SPoutbecomes theinput signal probabilityfor a fan

Figure 3.3 Clock Inverter Gating replaced by NAND and NOR gates. On the other hand, if the inverter is replaced by a NORgate,the SP of the clock gating signal would be (1 G). This isbecause logic HIGH is the controlling value of NOR and gating probability (GP) of G means (1 G) period of non-gating when the logic LOW is present. The output SP can then be obtainedas 1 S *(1 G). Let the binary variable X represent this choicebetween using NAND or NORgate. X = 1 implies usingNANDgate for clock gating and X = 0 neither implies choosing NORgate.For the regular inverters in the clock tree (i.e., those that do nothave clock gating

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 9 pp 583-589 December 2013 www.ijsret.org ISSN 2278 0882

out gate, the linearity property remains recursively true. As the base case, SP of clock tree root is a constantnumber. Lemma 2: If cell delay is linearly dependent on input signalprobability, delay expression of any gate is at most a quadraticfunction of X: Proof: From the above lemma, signal probability is a linear function of X. From the delay expression is a linear combination of two expressions where X is multiplied by thedelay of the NAND or NORcell. As long as the delay of eachcell is a linear function of the input signal probability, the delay expression is at most a quadratic function of X. Using the above expressions as well as that for an inverterfrom Table 3.1 starting at the root of the clock tree and recursively compute the symbolic SP and the delay from theroot of the clock to each leaf level sink. An example of thisis as follows. 2. AWARE DELAY MODEL The NAND and NOR gates are sized to match their rise and falldelay to those of an inverter (INV). In this way, replacement ofthe INV by any other gate will not change the nominal clockskew. The ratios of PMOS to NMOS width for INV, NAND, andNORgates in our library thatachieved this iso-delay setting are 2.2, 1.36, and 4 .46, respectively. The delay computed throughHSPICE has a nominal value of 22.69 PS for fanout-4 loadat 50 C. The next step is to characterize the delay of thesecells as a function of clock SP and GP. Since NBTI does notimpact the output load capacitance of the gate in any way, theload-dependent delay is ignored for degradation analysis. Ouraim for delay characterization is to extract simple high fidelityapproximations to guide the optimization engine in the rightdirection. Therefore, linearization is used of near-linear curves.To consider the impact of SP on delay, first SP is related to VTH.The VTHdegradation as a functionof SP using the SKmodel, extensively employed in other works is performed.Using the obtained VTHvalues,SPICE simulation to obtain the rise andfall delay of the NAND, NOR, and inverter gatesis performed. Since NBTIimpacts only PMOS devices, the fall delay of the gates wasobserved to be nearly constant for all SP. However, the risedelay of these gates varies by as much as 10% when the Spin creases from 0 to 100%. The dashed curves showsthe rise delay of INV, NAND, and NORgates as a functionof SP.There is

a large increase in delay degradation near very lowvalue of SP of approximately 5%. However, the curve flatten S out for larger values of SP. This observation is consistent withthose obtained to model this behaviour, we performed piecewise linear fit for the case of SP 5% and for SP > 5% obtainedthrough the Gnu plot tool with R2coefficient of fit as 0.88.The actual curves and the fit were forced to coincide at SP = 0%,SP = 5%, and SP = 99%. These linear fits are as follows: D INV (SP) = (0.4428*SP + 22.69) ps: SP 0 .05 (0.0417*SP + 24.79) ps: SP >0 .05 D NAND (SP) = (0.4213*SP + 22.69) ps: SP 0 .05 (0.0410*SP + 24.69) ps: SP >0 .05 D NOR (SP) = (0.2682*SP + 22.69) ps: SP>0.05 (0.0315*SP + 23.97) ps: SP >0.05. From the previous discussion, it is clear that clock SP hasdirect impact on the delay of the fan out gate. Next, we considerthe impact of GP of a NAND /NORgate on its own delay. BothNAND and NORgates have two PMOS transistors driven bytwo separate pins. One of the input pins is driven by the clocksignal from the previous stage of clock tree with probabilityof logic LOW as SP and the other pin is driven by gatingenable signal latched in the ICG with probability of logic LOW equal to GP. In the case of NAND gate, due to parallel paths to VDD through the twoPMOS devices, even if thePMOS connected to gating enable signal degrades; the net impact on the rise time is negligible. On the other hand, in thecase of NORgate, different values of gating enable probabilitylead to different VTHdegradation of the PMOS driven by agating enable signal. This directly affects the pull-up capabilityof the NOR gate due to the inherent PMOS stack in it. In short, for a NORgate impact of degradationis considered of bothPMOS transistors. To capture this effect,the rise delay of the NORgate as a function of the VTHdegradation of PMOS driven byan input clock for different gating enable probabilities drivingthe second PMOS input is simulated. The rise delay of theNORgate as a function of the GP at it on the x -axis (i.e., how frequently it is gated), for different SP of the clock pin.From this figure, it is immediately visible that GP can play asignificant role in determining the rise delay of the NORgatedue to the stacking effect. Fortunately, in the most relevantrange of signal probabilities the delay dependence can be veryclosely approximated by a linear dependence. Clearly, the higher the GP at the gating enable signal (i.e., of clock being gated), the higher the

IJSRET @ 2013

International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 9 pp 583-589 December 2013 www.ijsret.org ISSN 2278 0882

proportion of the timelogic HIGH neither (controlling value for NORgate) is fed to theNORgate, which translates into lower NBTI degradation. The risedelay of the NORwas observed to decrease approximately 8%in a near-linear manner when the clock GP varies from 0% to100%. Hence, we incorporated this GP dependence by linearly scaling the NORdelay as follows: NOR(SP, GP)=DNOR(SP) (1 0 .08 GP) (2) Using the expression for dependence on SP and GP, the delay of each of the threecells for any combination of these variables is written. These expressions can be used for optimizing clock skew of large scalecircuits using integer programming formulation described next. 3. Skew Reduction Formulation Using the models developed in the previous section, the optimization program formulation for skew reduction of a clock tree in the presence of NBTI degradationafter 10 years of aging is presented. Let the set of sinks in the clock treebe given as S. For the ith sink Si, using the piecewise lineardelay model developed in Section III-B, theformula for arrival time of the clock signal is obtained. Obviously, the arrival time is a function of the SP of the clock interconnectsand GP of clock buffers connecting sink Si to the clock signal root. This can be represented as ATi(Xi,SPi), whereXiand SPicapture the binary variables for the choice of NAND /NOR clock gating and signal probabilities along the path. There are two interesting problems that can be formulated.The first is anoptimizationproblem to identify the optimalChoiceofNAND /NORgate configuration to minimize the skew of the clock tree. This case is of special importance for high performance designs or when the clock tree structureis already fixed but timing closure is difficult to achieve. The second problem is a satisfiability problem which, givena clock tree structure, decides whether there is any configuration of NAND /NORassignment that meets a particular skew constraint after circuit aging.The optimizationproblem is important due to its more practical use. Consider the followingformulation: Minimize (MAX MIN) Subject to ATi ({Xi}, {SPi}) MAX i S (3) ATi ({Xi}, {SPi}) MIN i S Xi {0, 1} i S MAX 0 MIN 0

In this formulation, MAX and MIN are dummy variables that represent the largest and the smallest arrival time of the clock signal among all sinks, as indicated by the first two constraints over all sinks. All the Xivariables are constrained to be binary.By minimizing the objective (MAX MIN), we are effectivelyminimizing the clock skew of the whole clock tree. For a clock tree with n sinks, the number of constraints is clearly O(n).Assuming a balanced tree structure, there are log(n) levels thus each of the ATi (Xi,SP i) has at most O(log( n)) binaryvariables.The expression of arrival time contains multiplication of binary variables which can causesolvers to fail. We proved that the delay expression can have multiplication of at most two binary variables. To decompose such expressions,following transformationis used. Let XA and XB be the two binary variables whose multiplication appears in arrivaltime expression. A binary variable XAB is introduced such that, XA+ XB 1+XAB (1 XA)+(1 XB) 2 2 XAB By replacing XA XBbyXAB, and adding the above constraints to the ILP, the new problem is equivalent but withoutany multiplication of binary variables.Consider a design with 100k cells out of which 10%, i.e., 10k of these cells may be flops. Assuming each leaf levelclock buffer can drive ten flops, the clock tree will have 1kleaf level clock buffers or approximately 2k total clock buffersin the clock tree. Even if 10% of these clock buffers are gatingenabled, at most 200 binary variables are present. Therefore, theabove formulation can be solved readily by solvers, branch band bound techniques, or simulated annealing methods to get the optimal solution for skew minimization.

III.

RESULTS AND DISCUSSION:

Figure 5.1 Clock gating waveform

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International Journal of Scientific Research Engineering & Technology (IJSRET)

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We will get the corresponding output according to the inputs are given. If the gate pin is enabled (say 1) gating will occur and if the gate pin is disabled (say 0) gating will not occur.

Figure 5.2 Clock tree waveform Here the inputs are given to the corresponding tree nodes and the output waveform is obtained. When 0 is given clock goes low and 1 is given clock goes high. Not gate can be replaced by Nand/Nor Gate, we can calculate the Signal Propagation (SP) and delay. We will get the output when the Corresponding inputs are given. Finally we get the Clock delay variations depends on the Binary Variables X2 & X4

some of the interface traps resulting in partial recovery. Due to the induced NBTI some of the physical variations such as voltage and temperature variations takes place which increases clock skew. It cause the device works slower and causes delay variations. Hence we propose a system which uses NAND or NOR gate as output stage of integrated gating cells, it minimizes NBTI induced clock skew. By exploiting our technique we were able to reduce the NBTI induced clock by up to 74% compared to Traditional Method. Our future work clock skew reduction more than 74% compared to Traditional method. After analysing the Temperature and Voltage variations further, we can reduce clock skew in clock gating technique. Use software MICROWIND 3.0 Version, then we will analyse. REFERENCES 1. Ashutosh chakra borty, Member, IEEE and David Z. Pan, senior Member, Skew Management Of NBTI Impacted Gated Clock Trees,IEEE Transactions on computer-aided design of integrated circuits and systems, vol. 32. No. 6. 2. Blam .M, Kuuoglu .H, Varghese .D, and Mahapatra .S (2007) A comprehensive model for PMOS NBTI degradation, Recent progress Microelectron Rehab., vol.47, no.6, pp. 853 862. 3. Bhardwaj, Wang .W, Vattikonda .R, Cao .Y, and Vrudula .S (Sep.206) Predictive modeling of the NBTI effect for reliable design, IEEE customer Integer circuits conf., pp. 189 192. 4. Chakraborty, G. Ganesan, A. Rajaram, and D. Pan (Apr. 2009) Analysis and optimization of NBTI induced clock skew in gated clock trees, in Proc. Des. Autom. Test Eur., pp.296- 299. 5. Crupi .F, Pace .C, Cocorullo.G, Groeseneken .G, Aoulaiche .M and Houssa (Jun 2005) Positive bias temperature instability in nMOSFETS with ultrathin Hf-silicate gate delectrics, Microelectronics, Eng., vol. 80 pp.130 133. 6. Jhon J.M (Dec 2003) Method for Reducing Design Effect of wear out mechanisms on signal skew in Integrated Circuit Design. 7. Jifengchen, and Mohammed Tehranipoor (Jan. 2013) A Novel flow for Reducing clock skew considering NBTI effects and process variations, in proc. IEEE Int.symp. Quality Electron Design.

. Figure 5.3 Clock skew Output Waveform

IV.

CONCLUSION

We proposed a project for reducing the clock skew effect due to increased threshold voltage (Vth) which leads to NBTI (Negative Bias Temperature Instability). NBTI is well-known reliability concern for PMOS transistors, based on the reaction diffusion mechanism. NBTI occurs due to the generation of the interface traps at the Si-Sio2 interface when a negative voltage is applied to the PMOS gate stress. It manifests itself as an increase in the magnitude of Vth of the PMOS transistors. Removal of the stress can anneal

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International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 9 pp 583-589 December 2013 www.ijsret.org ISSN 2278 0882

8. Kewal .k, Saluja, ShriramVijayakumar, WarinSootkaneng and Xaingning Yang, (2008)NBTIdegaradation, IEEE VLSI.43, pp. 1063 9667. 9. Kumar .S, Kim .C and Sapatnekar .S (Nov.2006) An analytical model for negative bias temperature instability, In Proc. IEE/ACM Int. Conf. Computer Aided Des., pp. 493 496 10. Kumar .S, Kim .C, andSapatnekar .S (Jun. 2007) NBTI aware synthesis of digital circuits, in Proc. ACM/IEEE Des. Autom. Conf., pp. 370 375. 11. Kumar .S, Kim .K, and S. Sapatnekar .S (Mar. 2006) Impact of NBTI on SRAM read stability and design for reliability, in Proc. Int. Symp. Quality Electron. Des., Mar. 2006, pp. 213 218. 12. MickaelDenais, Vicent Huard, ChitoorParthasarthy, GullaumeRibes, France Perries Nathalie Revil, and Alain Bravain (December 2004) Interface Trap generation and

hole trapinng under NBTI and PBTI in advanced CMOS technology with a 20nm gate oxide, IEEE transcations on devices and materials reliability, Vol.4.No.4. 13. Sang Yun Kim, Tai Su Park, Jae Sung Lee, Donggun Park, ki Nam Kim and Jong Ho Lee (Jan 2005) NBTI of Bulk Fin FETs, IEEE 052113716 43rd Annual International Relability Physics Symposium. 14. Vattikonda .R, W. Wang .W, and Y. Cao .Y (jun. 2006) Modelinng and minimization of PMOS NBTI effects for robust nanometer design, in Proc. ACM/IEEE Des. Autom. Conf., pp. 1047 1052. 15. Wang .W,Yang .S, Bhardwaj .S, Vattikonda .R, Vrudhula .S, Liu .F and Cao .Y (jun. 2007) The impact of NBTI on the performance of combinational and sequential circuits, in Proc. ACM/IEEE Des, AutomConf, pp. 364 369.

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