2013 Interational Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]

A Comparison of PWM Control and Digital Control

Strategy for Asymmetrie DC-AC Caseaded H-bridge
Multilevel Inverter with Rand Motor Load
IircoleexhJ
Dept.of ELectricaL and ELectronics Engineering
..1Engineering CoLLege
Chennai,l ndia
jkshiv714@gmaiL.com
Anhumoni!
Dept. of ELectricaL and ELectronics Engineering
..1Engineering coLLege
Chennai, lndia
Ab8lmcl-This paper proposes a comparison between the
PWM control and Digital control strategy between cascaded
multilevel inverter where the conventional method produces
2n+ 1 output level for n independent DC sources and the digital
control strategy produces 2"+
1
_1 output level for the same n
independent DC sources also with the same number switches.
This paper also brings out the advantage of using Digital control
over the conventional PWM control by producing a low total
harmonie distortion level (THD) level for R-load. Also the paper
compares the performance of both the method in a Real time
load. This simulation is done with the help of
MA TLAB/SIMULINK
0d0x Terms-Cascaded H-bridge inverter, multi level inverter,
THD, PWM Control strategy, Digital control strategy
. INTRODUCTION
Recent years has put major developing countries on red
alert due to the increase in power demand which has just raised
exponentially with time unable to meet the demand the
countries are forced to im pose power cut thereby the increase
in the usage of inverters is high to meet the demand. Hence to
improve the quality of inverters various methods to produce
continuous power supply is being analyzed which would
reduce the losses and also the cost which includes reducing the
cost of components used and also to optimize the switches and
the components in the best way possible. This paper deals one
such method which would increase the output level from the
same number of switches from that of the conventional
method. Cascaded multilevel inverters in general use n DC
sources to produce fve level outputs whereas the proposed
method produces seven level output with the mere change in
the control strategy. The proposed method also provides
protection to controlled behavior. The proposed method
978-1-4673-4922-2/13/$31.00 20 13 IEEE 187
M0honoxundorom
Assistant Professor
Dept. of Electrical and Electronics Engineering
..1Engineering CoLLege
Chennai,lndia
Irohho/orcn
Dept. ElectricaL and ELectronics Engineering
..1Engineering coLLege
Chennai, lndia
doesn't switch on extra switches so the power dissipation and
the heat dissipation in the circuit also introduces also the circuit
produces a redundant technology. The soft switching technique
reduces the switching losses and also the stress in the device.
This paper brings out the diference between the
conventional PWM control strategy and digital control
strategy. Where the conventional method produces 2n+ 1
output level for n dc input whereas the digital technique
produces 2"
+
1
_
1 output level for n dc input sources.
Section II gives a overview of cascaded multilevel inverter.
Section III brings out the operation of conventional muItiievel
inverter. Section IV shows the operation in digital control of
inverter. Section V focuses on the simulation resuIts fom
MATLAB. Section VI draws out the conclusion of the paper.
H. CASCADED MULTI LEVEL INVERTER
Cascaded multilevel inverter comprises of n independent
DC sources with n H-Bridge circuits. Each H-bridge comprises
of four switches, the switches used may be MOSFET, IGBT,
thyristor etc, in which two switches operate in positive cycle
and two switches works during the negative cycle. Each H
bridge produces three voltage level they are + V de, 0,-V dc.the
voltage levels are produced with the different switching
combination of switches in the H-bridge. Cascaded multilevel
inverters can be used both in single and three phases by just
adding the number of H-bridge used. One are more H-bridge
used in the same circuit produces the cascaded multilevel
inverter. The input DC source may be any DC sources which
may aIso be sources such as photovoItaic cell etc. fnally the
total output is the summation of individual H-bridge used .the
2013 Interational Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]
control techniques for the H-bridge inverters are PWM
technique, SVM technique etc.
51
J
53
54
J
52
K
55
J
57
5
5
J
Fig l. Cascaded H-Brdge multi level inverter
III. CONVENTIONAL PWM MULTILEVEL INVERTER
Cascaded H bridge multilevel inverter consists of a series
of H bridge inverter. Cascaded inverter uses separate dc
sources which can be obtained from cells such as fuel ceIl,
hydrogen ceH, photovoltaic ceH etc. the ceHs are connected in
series so that they add up the voltage. Cascaded inverter is also
advantageous that it doesn't require any voltage-c1amping
diodes or voltage-balancing capacitors. For example if there
are any n level inverters and the output voltage Van=
Val + Va2+ Va3+ ....... Van. The output of the inverter are three
stages they are + V dc,O,and-V dc. the circuit used in this paper
has two H-bridge inverters, with each inverters has four
switches, so totaHy the circuit has 8 switches they are
Sl, S2,S3, S4,S5,S6,S7, S8.and the two dc voltage source used
are Vdcl,Vdc2. A simple circuit diagram is given in fig.2.and
fg 3. Shows the PWM control H-bridge inverter with motor
laod.The conventional switching method produces 2n+l output
for n dc sources. In this circuit we uses 2 H-bridge inverters so
for conventional PWM method we get 2(2) + 1=50utput levels

,ewea.
:
1
Vdc

VI
Sopl
Fig.2. PWM control H-bridge multilevel inverter with R load
188
JUN
.UN
UN
UN
-1UN
-.UN
-JUN

):w?']1'

P1;,
.
~

`,\:
t

|?|l?1s1|?T?1
Fig 3. PWM control H-bridge multilevel inverter wilh Motor load
TABLE . CONDUCTION TABLE FOR PWM CASCADED H-BRIDGE
MULTI LEVEL INVERTER
S1 S? SJ S4 S5 Sb S7
1 1 U U 1 U
U U U U 1 U
1 1 U U U U U
1 1 1 1 U U U
U U 1 1 U U U
U U U U U U 1
U U 1 1 U U
Sb
U
U
U
U
U
1

Fig 2. Shows the switching state for the conventional

muItilevel inverter. The switching state brings out the switches
which remain Turned ON when producing the required output
voltage level
2013 Interational Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]
UV *V 2V V UV UV -V -2V -V UV
S
t t t

1 t t

I

2
I
S
S

I

I I I

S
S



I I

S
.
I
d
S
S
I
Fig. 3. SWllchmg slale for PWM H-bndge mullllevle mverter
IV. DIGITAL CONTROL TECHNIQUE IN H-BRIDGE MULTILEVEL
INVERTER
The JK fip-fop is a negative triggered device, which has
three inputs they are JK, and a CLK. on the negative edge or in
the falling edge the JK fip fop produces to outputs Q and Q!
Depending upon the falling truth Table in table Ir.
TABLE H. TRUTH TABLE OF 1FLIP-FLOP
J K Q Q'
U U '-i '-i
U U
U U
'-i' '-i
There are two side of driver control they are Active-low
And active-high control. In active-Iow control the FET is
c10sed when the control signal is low or O,and the FET remains
open when the signal is high or l.In active-high control the
control signal is opposite. When the control is used in a H
Bridge with two switches working in active-Iow and active
High control the opening and c10sing of the switch depends
upon the PWM signal along with the Enable signal, when the
enable signal is high the circuit remains open and doesn't
conduct
The digital control uses 4 fip fops they are JK fip fop1,
JK fip fop2, JK fip fop3, JK fip fop4 and the outputs are
(Q1,Q1 '),(Q2,Q2'),(Q3,Q3'),(Q4,Q4').we know that fip
fops are c10ck edge triggered instead of level triggered, the
fip fops are given a c10ck signal and the input for the JK fip
189
fop1 is given through the constant as l.the technique works as
a counter in this process to get a seven level output we need
n+2 bit counters. The output of JK fip fop1 and JK fip fop2
are made to operate in the first half cycle of the positive cyc1e
and in reverse in the second half of the positive cyc1e. In the
first half of the cyc1e it acts as a up counter as the steps starts
on increasing are done by Q3' in the second half of the cycle it
acts as a down counter as the steps starts on decreasing are
done by Q3.Q4 and Q4' has been used as the control bits and
they are also used to separate the positive and negative
switches.
:s-:-,
= :-.:
,.w,.
:
'
ca t
M
M
ca!

:i :J

\::;- _

\:'|:;-
SPE

1::-!
Fig 4. Digilal conlrol in cascaded mullilevel inverler wilh R load
The proposed method uses two dc sources they are V dc and
V de/2, MATLAB software doesn't support counter directly so
we use JK fip fops and the output of which is given to the
AND or OR gates to generate the necessary gating pattern. We
do know that the output of logic gates is Boolean so to convert
Boolean function to double we use data conversion block. The
reason to use double as the conversion type is IGBT devices
accept fring signals in the form of double. In fg.6 fring
circuit we have 3 diferent sections they are counter section,
logic circuit and pulse separation. The counter counts from
0000 to 1111.Q3 and Q4 are used as control bits for the logic
circuit and pulse separation between positive and negative
pulses the various switching pattern in the circuit is gi yen as
fig.lO.a to lO.f
2013 Interational Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]
D
Fig 5. Digital gate signal for cascaded multilevel inverter
S2

Out

Ou

Out

Out
S1,S

Out
S7

Ou
ut
Fig 6. Firing sequence
Table III. CONDUCTION TABLE FOR DIGITAL CONTROL
S1 S? SJ S4 S5 Sb S7 Sb
JUN U U U U
.UN U U U U 1 U U
UN U U U U U U
-1UN U U U U U U
-.UN U U U U U U 1
-JUN U U U U 1
Table III gives conduction table for the digital control for the
cascaded muItilevel inverter
190
:.-
;

,+
tl
l
l!
l
l!
l
:
l6
Fig 7. Digital control with motor load
Fig
7
shows the digital control technique with a motor load
V.
S
IMULATION RESULTS
The simulation results
MA TLAB/SIMULINK
are obtained from
The simulation results of the output are shown in fg.8
which uses switches
SI
,
S2
, S3,
S4
,
S5
,
S6
,
S7
and S8, the
input of I H-bridge and 2
n
d
bridge combine together to
produce fve level output
.
.

. : . . . w : . .
Flg 8. Output of PWM cascaded multllevel mverter
The THD level of the PWD cascaded multilevel inverter is
found using the J analysis.the THD level is found to be
30.18%,the Figure is shown in Fig V.
2013 Interational Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]
Signal tuanalyze Availablesignals
Display s|e-ed saa' _ Display rri window
Sruc ur
Selecled signal: 250 cycles. FFT window (in red): 5 cyeles
IScopeData20

=!

-^

4.8 4.85 4.9 4.95 5
ll1+^dcw
Time{s)
Sr|| s).
'l1analysis
|!! 8.
~urdamerla| (50Hz) = 108.3. THD= 30.18%
ru0|| |rqu0cy|I)
20

.
f ll1settings
i
15 ||8y8 y
IBar (relaliveto fundamil)
`
10
b D ,

c
rrqu0cyx|s
`
I | I
-..
'
Hxrr|dI
0
1'000
0 200 400 600 800 1000
Frequency(Hz)
-
Fig 9.FF analysis of PW cascaded multilevel inverter
The gate pattern for the digital control technique is shown
below for switches SI , S2, S3, S4, S5, S6, S7 and S8
Hg 10.a. Gatmg patter of SWltch SI, SS
~
'
.
Flg LO.b. GatJng patter of sWltch S2
Flg LO.c. Galmg patter of sWltch S3,S7
191
.
. L .
Flg 10.d. Gattng patter of S4
Flg LO.e. GatJng patter of S6

Flg 10.f. Galmg patter of S8

The THD level of Digital control cascaded muItilevel inverter
is found using the FFT analysis. The THD level is found to be
14.32% is shown in 12.
Fig 11. Output of digital control of cascaded multilevel inverter
2013 Interational Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]
:a|toaa|,c [A vailable sa|s
Displ ay se'e:1e! signal _Displ ay FFT w|+tew
srucure:
Selected signal: 250 cycles. uaa.uared): 5 cycles
.

1ime(,)
SI,rtlim'I'l'
.
||aa,ss
Nu mberofcycl es:
48 4. 85 4. 9 4. 95 5 r
|| w|ndow
15
c 5
Fundamental (50Hz) = 94.24 THD= 14.32%
'"d,m,m,' ,,,"",oc, 1Hz)
1000
Frequency z,
.` .
||sc..s
Displ ay styl e "
'0ure'.ve1euatamea1e') -'
Baseval ue
Frequencyaxis

MaxFrequency(Hz
e::
Fig 16. FFf analysis of digital control of cascaded multi level inverter
Table IU. Difference between PWM cascaded multi level inverter and
Digital control multi level inverter
S.No Parameters Conventional Proposed
for n sources method method
1 Number of 2n+l 2
1
n+
1}
_
1
levels
2 Number of 4n 4n
switches
3 THD(without 20.48% 16.80%
flter)
4 Complexity Complex simple
in designing
circuit
Fig 13. Speed graph ofPWM multi level inverter
The speed graph of the PWM inverter is shown in fgure 13
and that of the digital graph is shown in Fig 14,the speed of the
PWM inverter with motor runs faster than that of the digital
control but the input to digital is very smooth so that the life of
the motor is beter compared to that of the PWM and speed
variation is smooth in digital but in PWM inverter its rough
192
Ftg 14. Speed graph of dtgIlal control multlevel Inverter
VI. CONCLUSION
This deals with the both the cascaded and Digital control in
multilevel inverter the results shows that for the PWM the
output is fve level for the same number of switches and the
Digital control produces seven level output for the same
number of switches also the THD has been decreased
considerably in to about 10% between the two control
techniques. So the new control provides safe operating of the
devices compared to the other technique.
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