JK Flip-Flop Applications

Name: __________________________

Objective: The purpose of this experiment is to introduce IC-type JK flip-flops and some of their basic applications. This will include the characteristics of the Toggle (T) flip-flop and the Delay (D) flip-flop connections of JK flip-flops. It will also investigate JK flipflop ripple counters. Equipment: One standard Logic Lab Kit and TTL chips. Procedure: 1.0 The JK Flip-Flop Complete the Q(t + 1) column on Table 1.1. Then, connect the circuit shown in Figure 1.1 and verify proper circuit operation by completing the Q(t + 1) Lamp column. If PRE and/or CLR input(s) are available, they are useful in forcing the initial conditions of Q(t).

Q(t) 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0

Q(t + 1)

Q(t + 1)-LAMP

1 0 1 0 1 0 1 Table 1.1: JK Flip-Flop

2.0 The Toggle (T) Flip-Flop Complete the Q(t + 1) column on Table 1.2. Then, connect the circuit shown in Figure 1.2 and verify proper circuit operation by completing the Q(t + 1) Lamp column. Q(t) 0 0 1 1 T 0 1 0 1 Table 1.2: T Flip-Flop Q(t + 1) Q(t + 1)-LAMP

3.0 Delay (D) Flip-Flop

Complete the Q(t + 1) column on Table 1.3. Then, connect the circuit shown in Figure 1.3 and verify proper circuit operation by completing the Q(t + 1) Lamp column. Q(t) 0 0 1 1 D 0 1 0 1 Table 1.3: D Flip-Flop Q(t + 1) Q(t + 1)-LAMP

4.0 The JK Ripple Counter A simple ripple counter can be implemented by connecting a series of T flip-flops together with each Q output tied to the clock input of the next flip-flop. Each flip-flop stage divides its input frequency by two. 4.1 Connect the four-stage ripple counter shown below in Figure 1.4 with each Q output wired to a lamp. 4.2 Clock the circuit manually or with a free-running clock at a rate of about 1 Hz and verify that the circuit is operating properly. (Each flip-flop lamp, going from left to right, should blink at one-half the rate of each previous lamp).

5.0 Divide-By-N Ripple Counters 5.1 Connect the circuit below in Figure 1.5 and verify its operation by analysis and testing.

When you have completed all of the above, have your instructor sign below.

_______________________________ Instructor's Signature

Figures
Note: In the figures that follow, the PRE and CLR inputs are active-low inputs. Hence to disable them they need to be tied high.

Connect the J, K inputs, the CLK pulse input, and the preset (PRE) and clear (CLR) inputs to switches. Tie the output Q to an LED.

PRE J Q

CLK

K CLR

Figure 1.1

The J, and K inputs have been tied together. Connect this input to a switch. The CLK pulse input, and the preset (PRE) and clear (CLR) inputs are tied to switches as before. Tie the output Q to an LED.

PRE J Q

CLK

K CLR

Figure 1.2

The J, and K inputs have been tied together with a NOT gate. Connect this input to a switch. The CLK pulse input, and the preset (PRE) and clear (CLR) inputs are tied to switches as before. Tie the output Q to an LED.

PRE J Q

K CLK CLR

Figure 1.3

Connect flip-flop outputs A, B, C, and D to LEDs. The reset (RST) input should be tied to a switch.

1
J A J B J C J D

CLK

CLK

CLK

CLK

CLK

K CLR

K CLR

K CLR

K CLR

RST

Figure 1.4

Connect flip-flop outputs A, B, and C to LEDs.

1
J
CLK

A
CLK

J
CLK

K CLR

K CLR

K CLR

Figure 1.5

Questions (3 points) 1. The maximum clocking frequency for a ten stage ripple-counter using 35 nsec flip-flops is about (a) 350 nsecs (b) 1 MHz (c) 350 MHz (d) 3 MHz

2. An RS F-F, without additional gating, may be connected as (a) Either a D or a T F-F A D but not a T F-F (e) A D, T, or JK F-F (b) A T but not a D F-F (d) A JK F-F (f) None of the above

3. A JK F-F, without additional gating, may be connected as (a) An RS F-F (b) A D F-F (c) A T F-F (d) None of the above (e) All the above