International Journal of Research in Computer and ISSN (Online) 2278- 5841 Communication Technology, Vol 2, Issue 11, November-

2013 ISSN (Print) 2320- 5156

Design of Reversible Mod-16 Synchronous Counter

T.V.V.S.S.Varalakshmi,M.Vidya P.G Student, Kakinada Institute of Engineering and technology, korangi, JNTUK , A.P, INDIA Assistant professor, Kakinada Institute of Engineering and technology, korangi, JNTUK ,A.P, INDIA varalakshmi1001@gmail.com,vidyameka@gmail.com

AbstractReversible logic is very important in lowpower circuit design and quantum computing. And also Reversible logic is gaining interest in the recent past Due to its less heat dissipating characteristics. A lot of research has been done in combinational as well as sequential design of reversible circuits. In this paper we have proposed a reversible T-Flip-flop which is better than the existing designs in the literature. A novel design of reversible synchronous mod-16 counter proposed in this paper. The important reversible gates used for reversible logic synthesis are Feynman gate, Fredkin gate, TSG gate and sayem gate etc. In this paper we have also proposed a new reversible gate which can be used as copying gate.The transistorized implementation of reversible gate presented in this paper are completely reversible in nature i.e. it can perform both forward and backward computation.Layouts for each gate and power,delay and LVS done through Tanner EDA tools . Index TermsReversible Logic, Reversible Gate, Power Dis-sipation, Flip-Flop, Garbage. I. INTRODUCTION Energy dissipation is becoming a major barrier in the evolving nano-computing era. As reversible logic ensures low energy dissipation [1] [2] it has gained importance in the recent past.An operation is said to be physically reversible if there is no energy to heat conversion and no change in entropy. On same lines, reversible logic computation implies that no information about the computational state can ever be lost. R. Landauer[3] has shown that for every bit of information that is erased during an irreversible logic computation kTln2 joules of heat energy is generated, where k is the Boltzmann constant and T is the temperature in kelvin at which the system is operating. C. H. Bennett [4] showed that the kTln2 amount of

energy dissipation would not occur if a computation is carried out in a reversible way. A reversible gate is a logical cell that has the same number of inputs and outputs with a bijective mapping between the input and output vectors. Direct fan-outs from the reversible gate and feedbacks from a gate output directly to its inputs are not permitted. Reversible circuits do not lose information and reversibl e computation in a system can be performed only when the system consists of reversible gates.Reversible logic i s likelyto be indemand in high speed power aware circu its, lowpower CMOS design.The main challengesof de signing reversible circuits are to reduce number of gates, garbage outputs, delayand quantumcost. Another important matter is hardware complexity. In the existing designs i n literature of sequential circuits several designs are pro posed.In this paper we have proposed most optimized designs of reversible edge trigged T-flip flop. While designing the reversible latchesfew researchers conentrated on red ucing the number of gates and garbage output, while other tried to reduced the quantum cost. II. FUNDAMENTALS OF REVERSIBLE LOGIC Reversible logic is a concept of digital circuit design which was born with the concept of creating digital logic circuits with zero power dissipation. It replaces irreversible logic gates with reversible gates in the conventional digital circuits. Some basic concepts of reversible logic are as follows Reversible gates are denoted as (n, n) digital logic gates, where (n, n) can be elaborated as (Total number of input signals, Total number of output signals). In reversible logic gates both the number of input signals and the number of output signals are equal. In these gates we can generate the input combinations at any instance by knowing the output combinations only. There exists a one to one mapping between the input and output signals i.e. a unique output combination

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International Journal of Research in Computer and ISSN (Online) 2278- 5841 Communication Technology, Vol 2, Issue 11, November- 2013 ISSN (Print) 2320- 5156
occurs for individual input combinations. Generally reversible gates follow these norms[1] Total number of input signals = Total number of output signals. [2] One to one mapping between input and output variables. [3] No feedback. [4] Individual output bits are high for a total of half the number of total input combinations. 2) LAYOUT:

Fig-4 layout of Reversible Feynman gate. B.FREDKlN GATE: Figure 5 shows a 3*3 Fredkingate.The input vector is I(A,B,C) and the output vector is 0(P,Q,R).The output is defined by P=A, Q=A'B+ACand R=A'C +AB.

Fig-1 Block diagram of (n, n) Reversible logic gate III. REVERSIBLE LOGIC GATES A. FEYNMAN GATE: Fig. 1 shows a Feynman Gate. Feynman Gate (FG) can be used as a copying gate. Since a fan-out is not allowed in reversible logic, this gate is useful for duplication of the required outputs.

Fig-5 Fredkin gate 1)TRANSISTOR IMPLEMENTATION Figure 6 shows the transistor implementation of the Fredkin Gate that need only four transistors.In the implementation,the output P is directly taken from input A as output P is same as input A.The proposed transistor implementation is suitable both for forward as well as backward computation,i.e.,completely reversible in nature.The forwardand backward computations for Fredkin gate are explained below.

Fig-2 Feynman gate 1)TRANSISTOR IMPLEMENTATION Figure 3 shows the transistor implementation of the Feynman gate.The transistor implementation is fully reversible, that is, the given circuit can also work for forward as well as reverse operation.

Fig-3 Reversible Transistor Implementation of the Feynman gate.

Fig-6 Reversible Transistor Implementation of the Fredkin gate

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International Journal of Research in Computer and ISSN (Online) 2278- 5841 Communication Technology, Vol 2, Issue 11, November- 2013 ISSN (Print) 2320- 5156

2) LAYOUT:

Fig-7 layout of Reversible Fredkin gate. C. SAYEM GATE: Sayem gate (SG) is a 4x4 reversible gate. The input and output vector of this gate are, Iv = (A, B,C,D) and Ov=(P,Q,R,S). The block diagram of this gate is shown in Fig 8. This gate can be used as a two input universal gate means it can perform any two input Boolean function. The sayem gate can be used to build reversible T- flipflop along with Feynman gate.

Fig-9 Reversible Transistor Implementation of the sayem gate. 2) LAYOUT:

Fig-8 sayem gate. 1)TRANSISTOR IMPLEMENTATION Figure 9 shows the Transistor implementation of Sayem gate. Actually the Sayem Gate is the combination of Fredkin Gate (FRG) and Feynman Gate (FG), and so it can simultaneously generate three output functions (from Q, R and S). The output P is taken with a nmos transistor. It takes 29 transistors for proposed completely reversible implementation of the Sayem gate. The proposed implementation is suitable for forward as well as backward computation.

Fig-10 layout of Reversible sayem gate. D.REVERSIBLE NEGATIVE EDGE TRIGGERED T FLIP-FLOP: As the name suggests, this flip-flop circuit used to toggle the output when input is high (1) and retains the output when input is low (0), thus it does two operation, it either holds the last state or toggles the output. Essentially, it has a logical symmetry with Controlled NOT kind operation. The reversible realization of T Flip-flop has two SG gates and one Feynman Gate is shown in fig. 11.

Fig-11 Reversible Positive Edge Triggered T Flipflop

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International Journal of Research in Computer and ISSN (Online) 2278- 5841 Communication Technology, Vol 2, Issue 11, November- 2013 ISSN (Print) 2320- 5156

1)LAYOUT:

Fig-12 layout of Reversible T-flip flop. All these layouts are drawn with 0.25um technology with double metal. And transistor sizes are wp=1.65um and wn=0.55um. E. PROPOSED COUNTER: MOD16 SYNCHRONOUS

From the above table we have T0=1 T1=Q0 T2=Q0Q1 T3=Q2Q0Q1 So we need 4 T-flip flops and 2 and gates to design mod 16 counter. F: PROPOSED REVERSIBLE MOD 16 SYNCHRONOUS COUNTER:

Fig-13 mod16 synchronous up counter. The above figure represents mod 16 synchronous up counter. The mod number represents = log means that we need to count 16 states we need 4 flip flops. For T flip-flop consider below table.1

By observing the table we have = ( + 1).design of mod 16 counter by taking present state(Qn) and next state means after applying a clock pluse(Q(n+1)) from the below table.2.And by using kmap we find what are the inputs for each flip-flop.

Fig-13 mod 16 reversible synchronous up counter. From the above figure to construct reversible mod 16 counter it needs 4 reversible T-flip-flops and 5 Fredkin Gates and 2 Feynman Gates. Fredkin gates with constant in puts acts as a reversible copying and also for AND operation. The Feynman gates used for copying the intermediate signals because in reversible gates fan out is not allowed.In this paper we implemented irreversible mod 16 counter and by using replacement method we constructed the reversible mod 16 up counter. The reversible gates used in this method is listed below:

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International Journal of Research in Computer and ISSN (Online) 2278- 5841 Communication Technology, Vol 2, Issue 11, November- 2013 ISSN (Print) 2320- 5156

Fig-14 fredkin gate acts as copying gate.

d) Reversible T-flip flop:

Fig-15 fredkin gate acts as AND gate.

Fig-16 feynman gate acts as copying gate. IV.SIMULATION RESULTS: Simulation is based on TANNER TOOL V13. Graph presented below are input and output signal at respective input and output terminal at each gate. a) Feynman gate: e) Mod 16 synchronous counter:

b) Fredkin gate: f) comparisons of gates with power,delay, and area: 1.power:

c) sayem gate: 2.delay:

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International Journal of Research in Computer and ISSN (Online) 2278- 5841 Communication Technology, Vol 2, Issue 11, November- 2013 ISSN (Print) 2320- 5156
TOOLS V 13.0 REFERENCES [1] R. Landauer, Irreversibility and heat generation in the computation process, IBM Journal of Research and Development, vol. 5, 1961, pp. 183-191. [2] V.V. Zhirnov, R.K. Cavin, J.A. Hutchby, and G.I. Bourianoff, Limits to binary logic switch scaling a Gedanken model, Proceedings of the IEEE, vol. 91, no, 11, 2003, pp. 1934-1939. [3] C. Bennett, Logical reversibility of computations, IBM Journal of Research and Development, vol. 17, 1973, pp. 525-532. [4] De Benedici, Report on future technologies for supercomputing, SANDIA Laboratories, 2007. [5] G. Schrom, Ultra-Low-Power CMOS Technology, PhD thesis, Technischen Universitat Wien, June 1998. [6] E. Knill, R. Laflamme, and G.J. Milburn, A scheme for efficient quantum computation with linear optics, Nature, 2001, pp. 64-52. [7] M. Nielsen and I. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, 2000. [8] S. Bandyopadhyay, Nanoelectric implementation of reversible and quantum logic, Supperlattices and Microstructures, vol. 23, 1998, pp. 445-464. [9] H. Wood and D.J. Chen, Fredkin gate circuits via recombination enzymes, Proceedings of Congress on Evolutionary Computation (CEC), vol. 2, 2004, pp. 1896-1900. [10] M. Perkowski, L. Joziwak, A. Mishchenko, A. AlRabadi, A. Coppola, A. Buller, X. Song, M.H.A. Khan, S. Yanushkevich, V.P. 246 Shmerko, and M. Chrzanowska-Jeske, A general decomposition for reversible logic, Proceedings of Reed-Muller Workshop, 2001, pp. 119-138. [11] D.M. Miller, Spectral and two-phase decomposition techniques in reversible logic, Proceedings of the IEEE Midwest Symposium on Circuits and Systems, 2002, pp. II493-II496. [12] D.M. Miller, D. Maslov, and G.W. Dueck, A transformation based algorithm for reversible logic synthesis, Proceedings of the IEEE Design Automation Conference, 2003, pp. 318-323. [13] P. Kerntopf, A new heuristic algorithm for reversible logic synthesis, Proceedings of the IEEE Design Automation Conference, 2004, pp. 834-837. [14] A. Agarwal and N.K. Jha, Synthesis of reversible logic, Proceedings of the Conference on Design, Automation and Test in Europe, vol. 2, 2004, pp. 21384-21385. [15] G. Yang, X. Song. W.N.N. Hung, and M.A. Perkowski, Fast synthesis of exact minimal reversible

3.area:

4.T-flip flop and mod-16 counter:

V.CONCLUSION AND FUTUREWORK: Reversible logic is very important for low power and quantum circuit design. Most of the attempts on reversible logic design concentrate on reversible combinational logic design. Only a few attempts were made on reversible sequential circuit design. The major works on reversible sequential circuit design propose implementations of flip-flops and suggest that sequential circuit be constructed by replacing the flipflops and gates of the traditional designs by their reversible counter parts. This method leads to reversible sequential circuits with higher realization costs and garbage outputs. As this is new approach to sequential circuit design using reversible gate. We made attempt to compare our design of different reversible circuits with respect to power dissipation factor. We observed that mod-16 Synchronous counter has less power dissipation and delay, area of this counter is little bit more. In future work, we plan to implement the reversible logic circuits with less area and less delay. Mostly these reversible logic circuits can be implemented with pass transistor logics due to this threshold voltage drops we should not get the full swing levels at the out put. so we need to redesign the gates to overcome these problems. ACKNOWLEDGMENT I am very thankfully to KIET College for providing a good lab facility. We simulate the Result on TANNER

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circuits using group theory, Proceedings of the IEEE Asia and South Pacific Design Automation Conference, 2005, pp. 1002-1005. [16] A. De Vos and Y.V. Rentergem, Reversible computing: from mathematical group theory to electronic circuit experiment, Proceedings of the 2nd Conference on Computing Frontiers, 2005, pp. 35-44. [17] D.P. Vasudevan, P.K. Lala, J. Di, and J.P Parkerson, Reversible-logic design with online testability, IEEE Transaction on Instrumentation and Measurement, vol. 55, no. 2, 2006, pp. 406-414. [18] V.V. Shende, I.L. Markov, and S.S. Bullock, Synthesis of quantum logic circuits, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, 2006, pp. 10001010. [19] P. Gupta, A. Agarwal, and N.K. Jha, An algorithm for synthesis of reversible logic circuits, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, 2006, pp. 2317-2330 . [20] M. Mohammadi and M. Eshghi, Heuristic methods to use dont cares in automated design of reversible and quantum logic circuits, Quantum Information Processing, vol. 7, no. 4, 2008, pp. 175192. [21] D. Maslov, G.W. Dueck, D.M. Miller, and C. Negrevergne, Quantum Circuit Simplification and Level Compaction, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 27, 2008, pp. 436-444. [22] A. Chakrabatri and S. Sur-Kolay, Nearest neighbour based synthesis of quantum Boolean circuits, Engineering Letters, vol. 15, no. 2, 2007. [23] M.H.A. Khan, Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits, Engineering Letters, vol. 16, no. 1, 2008, pp. 1-5. [24] J.E. Rice, Technical Report: The State of Reversible Sequential Logic Synthesis, Technical Report TR-CSJR2-2005, University of Lethbridge, Canada, 2005. [25] S.K.S. Hari, S. Shroff, S.N. Mohammad, and V. Kamakoti, Efficient building blocks for reversible sequential circuit design, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2006. [26] H. Thapliyal and A.P. Vinod, Design of reversible sequential elements with feasibility of transistor implementation, International Symposium on Circuits and Systems (ISCAS 2007), 2007, pp. 625-628. [27] M.-L. Chuang and C.-Y. Wang, Synthesis of reversible sequential elements, ACM journal of Engineering Technologies in Computing Systems (JETC), vol. 3, no. 4, 2008. [28] A. Banerjee and A. Pathak, New designs of Reversible sequential devices, arXiv:0908.1620v1 [quant-ph]12 Aug 2009. [29] L.K. Chang and F.-C. Cheng, Automatic synthesis of composable sequential quantum Boolean circuits, Proceedings of the 2005 International Conference on Computer Design (ICCD05), 2005. [30] M. Kumar, S. Boshra-riad, Y. Nachimuthu and M. Perkowski, Comparison of State Assignment methods for "Quantum Circuit" Model of permutative Quantum State Machines, Proc. CEC 2010. [31] M. Lukac and M. Perkowski, Evolving Quantum Finite State Machines for Sequence Detection,Book chapter, New Achievements in Evolutionary Computation, Peter Korosec (Eds.), URL: http://sciyo.com/books/show/title/newachievements-inevolutionary-computation, ISBN: 978-953-307-053-7, 2010 [32] M. Kumar, S. Boshra-riad, Y.Nachimuthu, and M. Perkowski, Engineering Models and Circuit Realization of Quantum State Machines, Proc. 18 th International Workshop on Post-Binary ULSI Systems, May 20, 2009, Okinawa. [33] M. Lukac, M. Kameyama, and M.Perkowski, Quantum Finite State Machines - a Circuit Based Approach, Quantum Information Processing, accepted with revisions. Authors Profile:
V.V.S.S.Varalakhmi Temanaboyina completed my B.Tech in Electronics and Instrumentation Engineering in 2009 from PRAGATI Engineering college,surampalem,Andhra Pradesh and pusuing my M.Tech in VLSI System Design from Kakinada Institute of Engineering and Technology, Korangi, Andhra Pradesh, India.

Vidya Meka completed her B.Tech in Electronics and Communication Engineering, in 2005 and M.Tech in Embedded systems VLSI Design in 2010 from college of engineering,pune,India. she was responsible for teaching in VLSI to post graduate students. Currently she is working as a Assistant Professor in Kakinada Institute of Engineering and Technology from two years. Her research areas include Embedded systems,low-voltage, low power, and high-performance integrated circuit design.

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