Notes Final Mid HW Studio Quizes 4 1

Analog Versus Digital Chapter 1 Introduction
What is digital design ? Slide 1 Analog v. Digital Digital Devices Digital Abstraction Slide 3 Analog devices process signal that can assume any value across a continuous range and produce results that are also in continuous form. Examples of continuous signal include voltage, current, force, etc.. Digital devices process signals that take on only two discrete values such as 0 and 1 and produces output that can be represented by 0 and 1.
Examples What is Digital Design ?

Slide 2 Also referred to as logic design, digital design is concerned with designing digital circuits, devices or systems such as computers. Slide 4 Analog Devices: solid-state devices TV (except for digital TV), telephone, etc. Digital Devices: Computer, CD player, digital TV, digital cellular phone, electronic calculator, DVD, and digital camera.
Advantages of Digital Systems

Reproducibility Slide 5 Easy of design via logic design Programmability-digital devices can be reprogrammed Robust to noise and perturbations Slide 7 AND gate OR gate NOT gate
Gates (contd)
Digital Devices: Gates

Slide 6 The most fundamental building blocks of a digital system are gates. A digital system (a chip) consists of many, many gates. They have one or more digital inputs and one digital output. Gates are digital devices that perform various basic logic operations. See Figure 1-1 Slide 8
AND gate
Performs the AND logic operation on its inputs and outputs its result.
Input output
Characteristics of 2-Input AND gate

Slide 9 Four possible input combinations lead to two dierent outputs. Slide 11
Characteristics of 2-Input OR gate

Four possible input combinations lead to two dierent outputs.
OR gate
Performs the OR logic operation on its inputs and outputs its result.
Input output
NOT gate
Also referred to as inverter, produces an output value that is the opposite of the input value. Slide 12
Input output
Slide 10
Digital Abstraction Flip-Flop

Slide 13 A ip-op (FF) is a device that stores a value of either 0 or 1. The state (stored value) of a ip-op depends on its current clock input. Flip-op can be constructed from gates. It is often used in sequential circuit since it remembers. Memory is made up of FFs. Slide 15 Alternatively, high and low are often used to represent 1 and 0 while discussing electronic logic.
Outputs Voltage Logic 1 Noise Margin Inputs
Logic 1
High 3,5 V
Invalid 1.5 V Logic 0 Logic 0 Low
Software for Digital Design Digital Abstraction

Digital circuit deals with analog voltages and currents. Digital abstraction allows analog behavior to be ignored. This can be accomplished by associating a range of voltages with each logic value. For example, the signals in a digital system might be restricted to two levels -5 and + 5 volts, corresponding to two discrete values of 0 and 1. It is necessary to understand the operating environment (e.g., voltage, temperature, loading, ..) under which the digital abstraction can be guaranteed. Software is widely used in digital design. It can signicantly reduce design time, design cost, and improve design quality. It has been mainly used for drawing schematic diagrams Slide 16 circuit simulation and modeling testing and debugging timing analysis Software for simulation (e.g. LogicWorks) and programming language (e.g. VHDL) for programming logic devices.
Slide 14
Integrated Circuits (contd)

An IC usually consists of legs, referred to as pins or DIPs (Dual in line). Pins are input/output connectors. The functionality or purpose of each pin can be obtained from the pin diagram or data sheet.
Integrated Circuits
Slide 17 A collection of one or more gates fabricated on a single silicon chip to achieve a specic function is called an integrated circuit or IC for short. Slide 19
Integrated Circuits (contd)

Based on the size (number of gates) of an IC, it can be classied as small-scale integration (SSI), medium-scale integration (MSI), large-scale integration (LSI), and very large-scale integration (VLSI). SSI usually contains less than 20 gates, MSI about 20-200 gates, LSI about 200 to 200,000 gates, and VLSI up to 1 million gates. The latest VLSI has 5 million gates.
Slide 18
Slide 20
Programmable Logic Devices

Most digital devices can be programmed or reprogrammed for dierent functionalities without physically replacing or rewiring the devices Programmable Logic Arrays (PLA) Programmable Array of Logic (PAL) Field Programmable Gate Array (FPGA)
Slide 21
Printed Circuit Boards

Slide 22 An IC is normally mounted a breadboard, often referred to as printed circuit board (PCB), to connect it with other ICs on the board. IC components are attached to the PCB using surface mount technology (SMT).
Chapter 2 Number Systems and Codes

Introduction Slide 1 Positional Number Systems Binary Addition and Subtraction Representation of Negative Numbers Slide 3
Positional Number Systems

In the positional number systems, each number is represented by a string of digits. The value of the number is equal to the weighted sum of all digits, with the weights determined by the digit positions (relative to the decimal point) and the base (radix) of the numbering system.
Introduction
Slide 2 Digital design deals with binary digits. In practice, very few numbers, events, conditions, and operations are in binary. This chapter shows how to represent non-binary numeric quantities and how to perform numeric operations in binary.
Slide 4
Positional Number Systems (contd)

In the decimal system, we have 10 digits (0-9) and the base is 10. So
7856.32 = 7 103 + 8 102 + 5 101 + 6 100 + 3 101 + 2 102
Positional Number Systems (contd)

In general, for a decimal number with N digits to the left of the decimal point and P digits to the right of the decimal point, its value D is
N 1
Binary Number
Slide 7 A N bit binary number can represent up to 2N distinctive binary codes. The 2N distinctive codes can be formed by successively adding 1 to the previous code until all N bits are 1s. For example, for 2 bit binary number, it has 4 codes: 00 01 10 11.
Slide 5
D=
i=P
di bi
where di is the ith digit and b is the base of the numbering system.
Binary and Decimal Number Conversion

Unsigned binary to Decimal
100112 = 1 24 + 0 23 + 0 22 + 1 21 + 1 20 = 1910
Binary Number
Slide 6 Binary numbers consist of a string of digits of values 0 or 1 such as 0101. The leftmost digit is called the most signicant bit (MSB) while the rightmost one the least signicant bit (LSB). Slide 8
Decimal to unsigned binary The binary equivalent of a decimal number is obtained by successively dividing the decimal number by 2 until the quotient is 1. The binary number is formed by the reminder (modulus) of each successive division and the nal quotient, with the nal quotient as the MSB and the rst reminder as the LSB. For example, 17910 = 101100112
HEX and Binary Conversion

HEX to Binary: replace each HEX digit with four corresponding binary digits as shown in Table 2-1.
HEXADECIMAL Number
HEXADECIMAL number has a base of 16, consisting of 16 digits ranging from 0 to 9 and A to F. For example, F1A3. Each hex digit corresponds to 4 binary digits. The decimal value of a hex digit ranges from 0 to 15. Hex numbers are often used to describe computer memory location. They are only used for human consumption.
F 1A316 = 1111000110100011 Binary to HEX: starting from right, replace each four binary digits with the corresponding HEX digit as shown in Table 2-1. Add leading 0s if there are fewer than 4 bits.
Slide 9
Slide 11
HEX to DECIMAL
HEX to Decimal
F 1A316 = 15 163 + 1 162 + 10 161 + 3 160 = 6185910 Decimal to HEX For example,
Slide 10
The HEX equivalent of a decimal number may be obtained by successively dividing the decimal number by 16 until the quotient is less than 16. The HEX number is formed by the reminder of each successive division and the nal quotient, with the nal quotient as the most signicant digit (the left most) and the rst reminder as the least signicant (the right most) digit. For example, 341710 = D 5916
Slide 12
011000110011102 = 18CE16
Refer to Table 2-2 for a summary of conversion methods.
OCTAL Numbers (contd) Binary to Decimal

For a binary number of many digits, to convert it to decimal, it is convenient to convert it to HEX rst, and then from HEX to decimal. Similarly, for a large decimal number, to convert it to binary, it will be more ecient to convert it to HEX and then to binary. For example, 101110110012 = 5D916 = 5 162 + 13 161 + 9 160 = 149710 OCTAL to decimal and the vice verse can be carried out the same as HEX to decimal except for using base 8 instead of 16. OCTAL to binary conversion can be accomplished the same way as HEX to binary except that each OCTAL digit corresponds to 3 binary bit. While converting binary to OCTAL, starting from the LSB and working towards left, separating binary bits into groups of 3 bits and replacing each group with the corresponding OCTAL digit. Octal to Hex (or vice verse) conversion needs to convert to binary rst, then to Hex,
Slide 13
Slide 15
OCTAL Numbers
Slide 14 The OCTAL numbering system has a base of 8, using digits 0-7. Each OCTAL digit can be uniquely represented by 3 binary bits as shown in Table 2-1. Slide 16
Binary Addition and Subtraction

Addition Subtraction
Binary Addition: Example

Slide 18 Like decimal addition, binary addition proceeds from right to left and align the LSB and padding zeros to the left. 10111110 + 10001101= 101001011 see more examples on page 32
Binary Addition Table

cin 0 0 Slide 17 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1 cout 0 0 0 1 0 1 1 1 s 0 1 1 0 1 0 0 1
Binary Subtraction: Example

Slide 20 11100101 - 00101110 = 10110111 see more examples on page 33
Binary Subtraction Table

bin 0 0 Slide 19 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1 bout 0 1 0 0 1 1 0 1 d 0 1 1 0 1 0 0 1
HEX Addition and Subtraction

Addition and subtraction in HEX can be done similarly. Just remember each carry-out or borrow-out has a value of 16. 19B9 + C7E6 = E19F Slide 21 E19F-C7E6 = 19B9 Alternatively, We can convert each HEX digit to binary (decimal) digit and perform operation in binary (decimal), and then convert the result back to HEX. see the examples in page 34.
Representation of Signed Numbers

Slide 22 Signed Magnitude Representation Twos Complement Representation Twos Complement Addition and Subtraction
Twos Complement Representation

Slide 24 To represent a signed number in binary, we use twos complement binary system.
Twos Complement Representation (contd) Signed Magnitude Representation

The MSB is the sign bit, with 0 for positive and 1 for negative number. The decimal value of the number is determined only by the remaining bits. Given n bits, the decimal value ranges from 2n1 1 to 2n1 1. The major problem with this representation is that we have two zeros: +0 and -0. It also has diculty in performing addition and subtraction. According to the twos complement representation, the MSB is the sign bit. A number is positive if the MSB is zero or negative if MSB is 1. The decimal value for a twos complement binary number is determined by all bits including the sign bit. The decimal value is computed the same way as for an unsigned number, except that the weight of the MSB is 2n1 . So in twos complement, binary and decimal conversion is
n1
Slide 23
Slide 25
D=
i=0
di 2i
, where di is -di for the MSB.
2s Complement Representation v. 2s Complementing Operation

2s complement representation is a binary representation scheme to represent signed binary number while 2s complementing operation is a special type of complementing operation that applies only to binary numbers represented in 2s complement. The sum of a binary number (represented in 2s complement) and its 2s complement is 0. For example, 1111 is a twos complement representation of -1 The twos complementing of 1111 is 0001, which represents +1. So, 1111+0001=0000
Twos Complement Number Range

Slide 26 Like for unsigned binary, a N bit twos complement number can represent 2N decimal values ranging from 2n1 to 2n1 1, one extra negative number (2n1 ) that does not have its positive counterpart. Slide 28
Decimal to Twos Complement Twos Complementing

Twos complementing is a binary operation. The twos complementing of a binary number is another binary number which when added to the number yields zero if the MSB of the sum is discarded The twos complementing of a binary number is obtained by complementing each individual bit of the number and then add 1 to the complemented number, ignoring the carry-out of the MSB. For example, see page 37. Determine the number of bits needed to represent the decimal number in twos complement. for positive decimal number, proceed the same way as for unsigned binary number, padding leading zeros if necessary. Slide 29 for negative decimal number, obtain twos complement representation for the corresponding positive number rst, followed by performing twos complementing on the binary number, yielding the twos complement representation of the negative number. For example, for number 10, we need 5 bits, its twos complement is 01010. For -10, its twos complement is obtained by twos complementing 01010, leading to 10110.
Slide 27
Twos Complement Representation (contd)

Convert an n-bit twos complement to a m-bit twos complement, if m > n, pad m n copies of sign bit to the left of the number. For example, to convert a 4-bit twos complement number to a 8-bit complement number, pad 4 zeros. Slide 30 0011 > 00000011 1010 > 11111010 If m < n, discard n m leftmost bits and the result is valid only if the discarded bits are the same as the sign bit. 8-bit to 4 bit 00000011 > 0011 11111010 > 1010 Slide 32
Twos Complement Addition

Overow occurs when the sum of two twos complements exceeds the range of the number system. An addition overows if the signs of the add-ends are the same and the sign of the sum is dierent from the add-ends sign. Another way to detect overow is looking at the carry-in and carry-out of the sign bit. Overow occurs when the carry-in and carry-out of the sign bit is dierent. See examples on page 41. Note overow may also occur if we subtract two numbers of dierent signs.
Twos Complement Subtraction Twos Complement Addition

Slide 31 Twos complement addition can proceed the same as the unsigned binary number addition, ignoring any carries beyond the MSB so long as the sum remains within the range (no overow). see example on page 39 Alternatively, we can convert twos complement subtraction into twos complement addition by converting subtrahend to its twos complement. See examples on page 42. Slide 33 Twos complement subtraction can be performed using the same procedure as for the unsigned binary numbers. Like addition, ignore the MSB borrows. Overow may occur. It can be detected by examining the borrow-in and borrow-out bit for the most signifcant bit. For example, over ow occurs for 0110-1101.
Other Issues
Slide 34 Binary Code for Decimal (BCD) Gray code Character Codes Slide 36
Gray Code
Gray codes are binary numbers that have only one bit change between successive code words. They may be used to represent successive states or positions. On the other hand, the binary codes of successive numbers may have more than one bit change between successive codes. See 3-bit gray code in table 2-10.
Gray Codes Construction

Gray codes of any number of bits can be reconstructed recursively using the three rules: A 1-bit gray code has two codes 0 and 1 Slide 37 The rst 2n1 code words of an n-bit gray code equal the code words of (n-1)-bit gray code, written in order with a leading zero appended. The last 2n1 code words of an n-bit gray code equal the code words of (n-1)-bit gray code, but written in reverse order with a leading 1 appended.
Binary Code for Decimal (BCD)

Slide 35 BCD encodes the digits 0 to 9 by the 4-bit unsigned binary representation 0000 through 1001. The code words 1010 to 1111 are not used. see table 2.9. Packed-BCD allows to to place two BCD digits in one byte, therefore representing values from 0-99.
Character Codes
Slide 38 Character codes are binary numbers used to represent characters. The most commonly used character code is ASCII codes, which represent characters with 7 bit, representing a total of 128 characters. see table 2-11.
Chapter 2 Summary
dierent positional number systems: decimal, binary, hex, and octal. conversion between dierent numbering systems. Binary addition and subtraction Slide 39 Representation of signed decimal number using twos complement binary system twos complement binary number range decimal and twos complement conversion overow twos complement addition and subtraction twos complement representation using dierent bits Gray code
Chapter 3 Digital Circuits

Slide 1 Logic Signals and Gates Transistor Logic Families Slide 3
Logic Signals (contd)

Logical signals are often called low and high. In positive logic, low often corresponds to algebraically lower voltages while high corresponds to higher voltages. So in positive logic, low is 0 and high is 1. It is just opposite for negative logic.
Logic Signals (contd)

Since a binary value represents a wide range of voltage, digital signal is highly immune to voltage variation. For example, for a CMOS gate, its high ranges from 3.5-5.0 v while its low ranges from 0 - 1.5 v.
5.0 V
Logic Signals
Slide 2 Digital logic ignores the analog by mapping real value of innite precision for a physical quantity into discrete values consisting of 0s and 1s. A digit bit can represent only two discrete states. N bits can represent 2N dierent values. See table 1 for physical quantities that can be represented by a bit. Slide 4
Logic 1 (high) 3.5 V invalid or undefined 1.5 V Logic 0 (low) 0.0 V
Truth Table Digital Circuit

A digital circuit consists of inputs and outputs.
Inputs Outputs
Truth table shows the relationship between the input and output of a logic circuit. It lists all combinations of inputs and the output produced by each input combination.
Slide 5 A logic circuit whose outputs depend only on its current inputs is called combinational circuit. A logic circuit whose outputs depend not only on its current inputs but also on past inputs, is called sequential circuit. The three gates AND, OR, and NOT can build any combinational circuits.
Slide 7
Algebraic Representation Digital Circuit (contd)

Slide 6 The operation of a combinational circuit can be described by the truth table while the operation of the sequential circuit can be described by the state diagram. Slide 8 The inputs and outputs can also be represented algebraically using boolean operators, i.e., F=X * Y + X * Y where represents the complement operation, * represent AND operation, and + represent OR operation.
Gates and Their Truth Tables

AND OR Slide 9 NOT NAND (two symbols) NOR (two symbols) NAND and NOR gates are faster than AND, OR, and NOT gates. truth table ? Slide 11
Input
NOR Gate
Input output
output
NAND Gate
Input output
Combinational Circuit
A combinational circuit consists of an arbitrary number of gates connected in series or in parallel but not feedback loop. Slide 12
X Y F
Slide 10
Input
output
truth table ? algebraic expression ? truth table ?
Timing Diagram
Timing diagram is the dynamic representation of the truth table. It represents input and output relationship as a function of the time.
Z= X AND Y
Logic Families
Slide 15 A logic family is a collection of dierent integrated circuit chips that have similar input, output, and internal circuit characteristics, but perform dierent logic functions. Chips from dierent families may not be compatible. Each family is dierent in the technologies used to produce the transistor.
Slide 13
X Y Z
Note signals do not change between 0 and 1 instantaneously and there is a transition period.
Logic Families (contd)

Slide 14 see transistor.ppt
Transistor
Slide 16
Two most common logic families are Transistor-Transistor Logic (TTL) and Complementary Metal-Oxide Semiconductor eld eect transistor (CMOS). They dier in materials, fabrication methods, and electrical behaviors.
CMOS Logic
Slide 17 Section 3.3.2 - 3.3.4 introduce MOS transistors and the construction of gates with MOS transistors.
Electrical Behavior of CMOS Circuits

The electrical behavior of a CMOS gate can be characterized by the following electrical properties: Slide 18 Logic voltage levels Noise margins Fan-in/Fan-out Speed (propagation delay) Power consumption
Logic Families (contd)

TTL gates are built on bipolar junction transistors while CMOS are built on MOS transistors. They operate on dierent voltages. For example, CMOS logic interprets 0-1.5 v as logic 0 and 3.5-5.0 v as logic 1 while TTL logic interprets 0-0.8 v as logic 0 and 2.0-5.0 v as logic 1. By far, most integrated circuits use CMOS.
Fan-in and Fan-out

Fan-in refers to the number of inputs a gate can have in a particular logic family. Slide 21 Fan-out refers to the maximum number of inputs that are connected from the output of a gate. It depends not only on the characteristics of the output, but also depends on the characteristics of the input.
Slide 19
Noise Margin
voltage outputs logic 1 Noise Margin Inputs
Fan-in
Slide 22 The number of inputs that a gate can practically have. Too many inputs for a gate may lead to signicant delay. The inputs to most CMOS gates are limited to 4 to 6. Gates with a large number of inputs can be made faster and ecient by cascading gates with fewer inputs.
Slide 20
11111111111 00000000000 00000000000 logic 1 11111111111 00000000000 11111111111 00000000000 11111111111 00000000 11111111 00000000 11111111 invalid 00000000 11111111 00000000 11111111 000000000 111111111 000000000 111111111 000000000 logic 0 111111111 logic 0 111111111111111111111111 000000000000000000000000
Fan-out
Slide 23 If too many fan-out are connected to an output, the DC noise margin may not be adequate. Fanout may also aect speed.
Data Sheets
The data sheet of a chip or a digital device species the devices logical and electrical characteristics as well as operating conditions. See table 3-3 for CMOS family and table 3-11 for TTL family. To ensure the device work properly, the operating conditions must be satised.
Slide 25
Propagation Delay
Slide 24 There is a lag between an input change and the corresponding output change. Propagation delay refers to the amount of time needed for a change in the input signal to produce a change in the output signal.
Chapter 4 Combinational Logic Design

This chapter is concerned with analysis and synthesis of combinational logical circuit. Slide 1 Analysis-start from a logic diagram of a circuit and proceed to a formal description of the function of the circuit. Synthesis-start with a formal description of the function of a circuit and proceed to a logic diagram that performs the required function. Slide 3 Notations:
Switching Algebra
It is the mathematical foundation for logic design.
+ stands for logic OR operation, e.g., x + y = x OR y stands for logic AND operation, e.g, x y = x AND Y stands for logic NOT operation or complement, e.g., x = NOT x If a logic operation involves all the three operations, the precedence order is: , , and +, e.g. , X + Y Z .
Axioms Table of Contents

Slide 2 Switching algebra (Boolean algebra) Circuit Analysis Circuit Synthesis Slide 4 Axioms are a minimum set of basic mathematic denitions that we assume to be always true and from which we can derive theorems. Let X be a logic variable taking on values 0 or 1. (A1) X =0 if X = 1 (A2) If X =0, X = 1 (A3) 0 0 =0 (A4) 1 1 =1 (A5) 0 1 =0 (A1) X =1 if X = 0 (A2) If X =1, X = 0
(A3) 1 + 1 =1 (A4) 0 + 0 =0 (A5) 0 + 1 = 1+ 0=1
Single Variable Theorems

Let X be a logic variable (T1) X + 0 = X Slide 5 (T2) X + 1 = 1 (T3) X + X = X (T4) (X ) = X (T5) X + X = 1 (T5) X X = 0 (T1) X 1 = X (T2) X 0 = 0 (T3) X X = X Slide 7 (T11) X Y + X Z + Y Z = X Y + X Z (Consensus) (T11) (X + Y ) (X + Z ) (Y + Z ) = (X + Y ) (X + Z ) In all the theorems, it is still true if a logic variable is replaced with a logic expression.
These theorems can be proved using axioms via perfect induction.
Two (Three) Variable Theorems

Let X , Y , Z be three logic variables (T6) X + Y = Y + X (commuative) (T6) X Y = Y X (T7) (X + Y ) + Z = X + (Y + Z ) (associative) (T7) (X Y ) Z = X (Y Z ) Slide 6 (T8) X Y + X Z = X (Y + Z ) (distributive) (T8) (X + Y ) (X + Z ) = X + Y Z (note add out from right to left) (T9) X + X Y = X (covering) (T9) X (X + Y ) = X (T10) X Y + X Y = X (combining) (T10) (X + Y ) (X + Y ) = X Slide 8
Two (Three) Variable Theorems (contd)

Theorem T8 may be used to convert product of sums expression to sum of products expression, for example V (W + X ) (Y + Z ) = V W Y + V W Z + V X Y + V X Z Theorem T8 is often used to convert sum of products expression to product of sums expression, for example (V W Z ) + (Y Z ) = (V + Y ) (W + Y ) (Z + Y ) Z How about ((X + Y ) Z )) + (X Y Z ) Proof of T8 requires X (X+Y)= X + X Y = X
swapping + and and complementing all variables. For example,
Two (Three) Variable Theorems (contd)

Slide 9 Theorems 9, 10, and 11 are often used to minimize (simplify) a logic circuit. They all share the property that there is a reduction in the number of logic gates or the number of logic variables from left to right. We have: Slide 11
F (X, Y, Z ) = X Y + Z Y F (X, Y, Z ) = (X + Y ) (Z + Y ) see more examples on page 192 Like theorem 8, DeMorgans law may be used to convert between sum of products and product of sums.
n Variable Theorems
The two or three variables theorems can be extended to an arbitrary number of variables, n as shown in table 4-3. T12) X + X + ... + X = X T12) X X ... X =X The DeMorgans theorem (T13, T13) Slide 10 T13) (X1 X2 ...Xn ) = X1 + X2 + ... + Xn T13) (X1 + X2 + ... + Xn ) = (X1 X2 ...Xn ) see gure 4-3, 4-4 for the use DeMorgans theorem The Generalized DeMorgans Law T14) F (X1 , X2 , .., Xn , +, ) = F (X1 , X2 , ....Xn , , +) The generalized DeMorgans theorem (T14) states that given any n-variable logic expression, its complement can be obtained by Slide 12
Duality
Principle of Duality: Any theorem or logic equation remains true if 0 and 1 are swapped and and + are swapped throughout. It doubles the usefulness of everything. In general, the dual of a logical expression F can be represented as F D (X1 , X2 , . . . , Xn , +, , , 0, 1) = F (X1 , X2 , . . . , Xn , , +, , 1, 0) where F D is the dual of F . See previous theorems for example.
Logic Functions Representations

Truth table, practical only for a small number of variables. Algebraic sum of minterms (Canonical Sum) minterm : is a product of n distinctive logic variables (or their complements), e.g., X Y Z. Slide 15 the sum of minterms corresponds to the combination of truth-table rows for which the function produces a 1 output. Note for a n variable logic function, each minterm must consist of n variables and within each minterm, each variable is represented by its complement if the variable value is 0. Algebraic product of maxterms (Canonical Product) maxterm : is the sum of n distinctive logic variables or their complements, e.g., X+Y+Z the product of maxterms corresponds to the product of
Duality v.s. DeMorgans Law

F (X1 , X2 , . . . , Xn ) = F D (X1 , X2 , . . . , Xn ) Slide 13 See gures 4-7 and 4-8, where a type-1 gate is an AND gate if positive logic is used or it is a OR gate, a type-2 gate is an OR gate if positive logic is used or it is a AND gate. Simply, by changing the logic convention, the two circuits produce the same output.
Duality v.s. DeMorgans Law

X1 X2 X3
type 2 type 1 type 1 type 2
X4
type 2
X5
type 1
type 1
F(X1, X2, ... , Xn)
Slide 14
type 1
type 2
Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
Xn
X1 X2 X3
Slide 16
type 1
type 2
truth-table rows for which the function produces a 0 output. Note for a n variable logic function, each maxterm must consist of n variables and within each maxterm, each variable is represented by its complement if the variable value is 1.
type 2
X4 X5
type 2
type 1
type 1
type 1
FD(X1, X2, ... , Xn)
Xn
type 1
type 2
Algebraic representations
For the example in table 4-5 and 4-6, we have Algebraic Sum of Minterms
An Example
Given truth table, you should derive its canonical sum and canonical product, and simplify the canonical expression. Given a logical expression, you should be able to Slide 19 derive its truth table canonical sum canonical product For example, given F=X+YZ, derive its truth table, canonical sum and canonical product.
F Slide 17
=
X,Y,Z
(0, 3, 4, 6, 7) = X Y Z + X Y Z + X Y Z +X Y Z +X Y Z
Algebraic Product of MaxTerms F =

X,Y,Z
(1, 2, 5) = (X + Y + Z ) (X + Y + Z ) (X + Y + Z )
Canonical Sum v. Canonical Product

To convert between canonical sum and canonical product, take the set complement. For example, Slide 18
A,B,C
Logic Combinational Circuit Analysis

Given the logic diagram of a circuit, obtain a formal description of its logic function. From the logic function, we can determine Slide 20 circuit behaviors for various input combinations simplify (minimize) the circuit structure to obtain a dierent circuit transform the algebraic description into standard form (e.g., sum of products or product of sums) for easy implementation.
(0, 1, 2, 3) =
A,B,C
(4, 5, 6, 7)
Note 1) both canonical sum and product are not minimal;2) sum of products and product of sums may be minimal and each term may not contain n variables.
Algebraic Expression
For example, gure 4-11,
X Y Z F
Methods for Logic Function Description

Truth table, good for small circuit but not practical for large circuit with many inputs. From a truth table, we can directly produce a logic expression in a standard form such as canonical sum or product (sum of minterms or product of maxterms). Alternatively, given a logic diagram, we can use a simulator to automatically generate the output (or even the intermediate results) for all possible input combinations.
Slide 21
Slide 23
X Y Z X Y
X + Y (X + Y ) Z F = ((X + Y) Z) + (X Y Z) X Y Z
we can obtain its algebraic expression as F = ((X + Y ) Z ) + (X Y Z ) The diagram consists of multiple levels, may cause propagation delay. Algebraic expression Slide 22 We can build an algebraic expression of a circuit by propagating expressions from inputs through gates towards the output. Boolean algebra may be used to simplify the expression to obtain a dierent circuit of the same logic function. Slide 24 Using Boolean algebra (Theorems T8 and T8), we can convert the expression to standard form: sum of products and product of sums. Sum of Products: F = X Z +Y Z +X Y Z
X Y Y Z X X Y Z

XZ
F = X Z + Y Z + X Y Z
W X X
W + X ((W + X) Y)
Product of Sums: F = (X + Y + Z ) (X + Z ) (Y + Z )
Y W (W + X + Y) Y (W + Z) Z F = ((W + X) Y) (W + X + Y) (W + Z)
X Y Z X + Y + Z
Slide 25
X Y Z
X + Z
F = (X + Y + Z) (X + Z) (Y + Z)

Slide 27
Given the same above expression, the circuit can be further simplied by removing redundant NOT gates, leading to a dierent physical circuit as shown in Figure 4-16.
W X Y X W + X (W + X) Y W W + X + Y Y W+Z Z F = ((W + X) Y) (W + X + Y) (W + Z)
Y+Z
They correspond to dierent physical circuits (gures 4-12 and 4-13), each has only two levels.
Algebraic Expression (contd)

For circuits contains NAND and NOR gates, DeMorgans theorem may be used to simplify the algebraic description of the circuit. See example, 4-14 .
W X Y W X (W X) ((W X) Y) F = [((W X) Y) + (W + X + Y) + (W + Z)] (W + X + Y) Y (W + Z) Z
Non-uniqueness in circuit representations

Normally, the algebraic logic expression may be ambiguous in that it may correspond to dierent physical circuits depending on the logic devices used. For example, in gure 4-17, one algebraic expression G=WXY+ YZ Slide 28 corresponds to 3 dierent physical circuits.
(a) W X WXY G (b) W X (W X Y) G Y Z (Y Z)
Slide 26
Simply applying DeMorgans law yields an equivalent algebraic expression. F = ((W + X ) Y )) (W + X + Y ) (W + Z ) whose circuit is shown in Figure 4-16.
Y Z
YZ
(c)
W X
(W X) Y
WXY
Y Z
YZ
Example
Problem Statement: Design a four-bit prime number detector. They, though logically equivalent, may have dierent electrical properties, costs, and sizes. Inputs: Four bits representing decimal numbers from 0 to 15 Slide 31 Output: 1 if input is a prime number or 0. Truth Table Algebraic Sum or Product Expression Logic diagram see gure 4-18
Slide 29
N3
N3 N3 N2 N1 N0 N3 N3 N2 N1 N0
Logic Combinational Circuit Synthesis

Given the informal (verbal) functional description of a circuit, formalize the description with a truth table or an algebraic expression and design a circuit based on the formal description that performs the required logic function. Manipulate the algebraic expression to simplify (minimize) the circuit.
N2
N2 N3 N2 N1 N0 N2 N3 N2 N1 N0 F
N1
N1 N3 N2 N1 N0 N1 N3 N2 N1 N0
Slide 30
Slide 32
N0
N0 N3 N2 N1 N0 N0
After simplication
N3 N3 N2 N2 N1 N1 N0 N0 N3 N2 N3 N0 N3 N2 N1 N0 F N3 N2 N1 N0 N3 N2 N1 N0 N0
Another Example
Slide 35 Design a two-bit odd number detector, which outputs one if the input number is an odd number and 0 otherwise.
Slide 33
N1
Circuit Manipulations Example (contd)

Slide 34 Also see the alarm example. Here, the functionality of a circuit is described using logical connectives, which may be more convenient than truth table. Slide 36 Given an algebraic representation of a logic circuit, we usually manipulate the algebraic representation to convert it to standard forms replace with more ecient gates like NAND or NOR simplify (minimize) the expression
Convert to Standard Forms

Manipulate the expression using Boolean algebra (mostly theorems T8 (multiply out), and T8 (add out) and DeMorgans law) to convert it to sum of products. Slide 37 For example, gure 4-20 represents a sum-of-products version of the original Boolean algebra. A two level logic diagram can be used to represent a standard sum or product.
PANIC ENABLE EXITING WINDOW DOOR GARAGE ALARM
Use NAND and NOR gates

Since NAND and NOR are usually faster than AND, OR, and NOT gates, they are often replaced with NAND and NOR gates. Slide 39 For sum of products circuit, this can be achieved by inserting a pair of inverters between the output of each AND gate and the input of each OR gate. The inserted inverters can then be absorbed by the AND and OR gates, leading to all NAND gates. For example, see gures 4-21 and 4-22. We can conclude that any sum of products circuit can be represented solely by NAND gates.
SECURE
PANIC ENABLE EXITING WINDOW DOOR GARAGE
Slide 38
ALARM = PANIC + ENABLE EXITING WINDOW + ENABLE EXITING DOOR + ENABLE EXITING GARAGE
(b)
(a)
Slide 40
(c)
Use NAND and NOR gates (contd)

For product of sums circuit, this can be achieved by inserting a pair of inverters between the output of each OR gate and the input of each AND gate. The inserted inverters can then be absorbed by the OR and AND gates, leading to all NOR gates. For example, see gure 4-23. We can conclude that any product of sums circuit can be represented solely by NOR gates. Slide 41
Combinational Circuit Minimization

Slide 43 Minimization means to reduce the number of gates of a circuit to a minimal set that are needed to build the circuit.
(c)
(a)
(b)
Algebraic Minimization Procedure

Start with truth table, sum of products or product of sums expressions Slide 44 For expressions not in a standard form, they need be converted to one of the two standard forms before minimization. Apply theorems T9, T9, T10, T10 T11, and T11. see example in gure 4-25.
Slide 42
The same kind of manipulation can be applied to arbitrary logic circuits as shown in Figure 4-24.
Karnaugh Map Construction (contd) Graphical Approach: Karnaugh Map

Slide 45 Karnaugh Map is a graphical representation of the truth table. It was invited by Maurice Karnaugh (a physicist) in 1953. More details on the history of the K-map can be found at http://en.wikipedia.org/wiki/Karnaugh map . Slide 47 Two variable Karnaugh map Three variable Karnaugh map Four variable Karnaugh map see gure 4-26 for example and understand the relationship between the truth and the K-map.
Minimizing SOP with K-Map

The primary purpose of K-map is for minimization. We will show how to use it to minimize algebraic representations in sum of products (SOP).
Karnaugh Map Construction

Slide 46 label each column and row in the order of gray-code bracket each region where the corresponding variable is 1 put the values of 1 or 0 in the corresponding cells, but not both. Slide 48
label each cell in K-map that corresponds to 1 circle the adjacent 1-cells (minterms) and combine them write the sum of new products Note 1) more than 2 1-cells may be combined 2) the number of cells in a circled region must be power of 2. 3) the circled region must be rectangular 4) account for all adjacent relationships 5) consider wrap-around when circling cells in the boundary
Minimal Sum
6) start with the region that includes the most number of 1-cells Slide 49 see gure 4-27 for example. Slide 51 A minimum sum of products of a logic function is the one that has the fewest possible number of product terms and that has fewer or equal number of logic variables than any sum of products expression of the same number of products.
Rule of Combination
Given a K-map with circled regions, the following rules specify how to determine the form of the combined product graphically. If the circled area covers only regions where the variable is 0, then the complement of the variable appears in the combined form. If the circled area covers only regions where the variable is 1, then the variable appears in the combined form. If the circled area covers both regions where the variable is 0 and 1, then the variable does not appear in the combined form. see examples in gure 4-30, 4-31, and 4-32.
Denitions
a prime implicant in a K-map is a circled set of 1-cells that satises combining rules and that will cover one or more 0s if we make it larger a distinguished 1-cell is a 1-cell in a K-map that is covered by only one prime implicant. an essential prime implicant is a prime implicant that covers one or more distinguished cells. Given two prime implicants P and Q in a reduced K-map, P is said to eclipse Q if P covers at least all the 1-cells covered by Q.
Slide 50
Slide 52
In this case, trial and error may be used. For example, gure 4-37.
Minimal Sum Theorem

Slide 53 A sum of essential prime implicants is always minimal. However, a sum of prime implicants may not be minimal. Slide 55
Programs (e.g. Espresso) are available that implement certain algorithms to automatically nd the minimal sum. See more examples in problem 4-14. Also note the minimal sum may not be unique.
Procedure for Finding a Minimal Sum

identify the essential prime implicants and include them in the nal sum. If the identied essential implicants cover all 1-cells, then done. The resulting sum is minimal. If the identied essential implicants do not cover all 1-cells, then remove the 1-cells covered by the essential prime implicants, yielding a reduced map. In the reduced map, select the prime implicant a) that consists of the fewest number of variables (see example in Figure 4-34); or b) that eclipses other prime implicants (see example in gure 4-35); c) select a minimum number of prime implicants that cover all 1-cells. Note the above procedure may not work for complex logic circuit.
Minimizing POS with Karnaugh Map

To minimize the product of sums, we can follow the same procedure for sum of products except for circling and combining regions corresponding to 0s. Note each circled region is represented by a sum term. Within each sum term, a variable is represented by itself if its value is 0 and by its complement if its value is 1. The procedure for identifying the minimal sum remains applicable. The prime implicants consist of circled zeros and look for distinguished 0-cells for essential prime implicants.
Slide 54
Slide 56
Minimizing POS with Karnaugh Map (contd)

Alternatively, given a product of sum F , we rst complement F to obtain F . F is the in the form of sum of products. We then minimize F . Finally, we complement the F that has been minimized using DeMorgans law, obtaining the minimal product for F . In general, we need to compare both the minimal sum and minimal product and choose the less cost one in terms of fewer number of terms and logic variables.
Function with Dont Care

For certain combinational circuit, its output does not matter for certain input combinations. This may be because these input combinations rarely occur or if they do occur, the output is undened. This may be interpreted as given these input combinations, the output can be any value (0 or 1). One example is the 4-bit BCD digit. The BCD has only 10 digits (0-9) but with 4 bit, we can represent 16 numbers. So the minterms from 10-15 should never occur. If they do occur, the output is undened.
Slide 57
Slide 59
Minimizing POS with Karnaugh Map

For example, using K-map minimizing F =
W,X,Y
Function with Dont Care (contd)

The canonical sum for a prime number BCD-digit detector can be expressed as Slide 60 F =
N3 ,N2 ,N1 ,N0 (1, 2, 3, 5, 7) +
(0, 1, 3, 4, 5)
Slide 58
This can be done 1) using F = W,X,Y = (2, 6, 7) but the result is minimal expression in SOP; or 2) direct minimization with the maxterms (corresponding to 0-cells); 3) get F, minimizing F as SOP, and complement the minimal F to get the minimal F. Note 2) and 3) should obtain the same result.
d(10, 11, 12, 13, 14, 15)
where d(.) represents the dont care inputs. In K-map, the dont cares cells may be marked as d or x.
Minimize SOP with Dont Care

while minimizing SOP with dont cares, the procedure should be modied as follows some ds should be included when circling sets of 1s to make the sets as large as possible. Slide 61 Do not circle any sets that contain only ds
Static Race Hazard (section 4.4.1)

A race condition or race hazard changes the desired output of a circuit as a result of the timing of the inputs. They are usually caused by the dierent delays in the inputs as a result of further processing on an input, i.e., adding an inverter to the input. The output will behave dierently (a g. glitch) during the interval when the inputs transition from one state to another. See Figure 4-38. K-map may be used to detect the hazard as shown in Figure 4-40 (a). By adding an extra term as shown in Figure 4-40 (b) and Figure 4-41, the static hazard can be avoided.
Slide 63
N3
(a) N1 N0
N3 N2 00 00 01 11 N1 10
0 1
N3 (b) 01
4 5
N3 N2 N1 N0 N3 N0 00 01 1 1 1 N2 1 1 00 01 11 d d d d
11
12
10
8 9 11
10
N2 N0
d
13
1
3 7
1 1
6
d
15
N0 N1 N2 N1
1
2
d
14
d
10
11 10
d d
N0
1 N2
F = N3,N2,N1,N0(1,2,3,5,7) + d(10,11,12,13,14,15)
F = N3 N0 + N2 N1
How to Go from Expression to Karnaugh Map

if the expression is in sum of products, mark the region in the map that corresponds to a product term as 1s. Each marked region represents the intersection of the variables in the product term. if the expression is in product of sums, nd the cells corresponding to each sum term and mark them as 0s. Alternatively, complement the original expression, yielding a sum of products expression. Mark the region in the map that corresponds to each product term as 0s. For example, F = X Z + XY + XY Z and F = (X + Y ) (X + Z ) (X + Y + Z )
Minimization Using Espresso

Slide 64 see espresso intro.ppt
Slide 62
Combinational Circuit Design Examples

1. Design a unsigned 3-bit input circuit that outputs a binary number that doubles the input binary number. 2. A 4-bit comparator circuit that receives two 2-bit numbers as its input. Design a minimal sum-of-products circuit that produce a 1 output if and only the rst number is larger than the second one. 3. A 4-bit comparator circuit that receives two 2-bit numbers as its input. Design a minimal sum-of-products circuit that produce a 1 output if and only the rst number is larger than the second one. The output is dont care if the two numbers are equal. Note problems 2 and 3 may be done more eciently if we work on the K-map directly instead through the truth table.
Slide 65
Chapter 6 Combinational Logic Design Practices This chapter is concerned with examples of basic combinational circuits including PLA, decoders, encoders, comparators, xor gate and parity circuits, multiplexers, adders, and FPGA. Those basic building circuits frequently appear, as building blocks, in the combinational circuits.
Block Diagrams
Slide 3 Block diagram shows the inputs , outputs, functional modules, internal data paths, and important control signals of a system. See Figure 6.1 for example.
Slide 1
Documentation Standards
Documentation is necessary for correct design and ecient debug and maintenance of digital systems. A documentation should consist of the following items: a specication describes the functionality (e.g., what it does ) of a circuit and its inputs and outputs. Slide 2 a block diagram is an informal pictorial description of the circuits major functional modules and interconnections. a schematic diagram is a formal specication of the electrical components of the system, their interconnections, and details about each IC chips. a timing diagram shows the various logic signals as a function of time. Slide 4
SHIFT-AND-ADD MULTIPLIER
RESET LOAD RUN DISPLAY R/W 4 CONTROL ADDR BYTE EN IN 16-word x 32-bit RAM OUT
INBUS 32 2 direct SEL LDA LDB 32 left 32 32 right
MULTIPLEXER 4 to 1 32
A REGISTER 32
B REGISTER 32
CARRY LOOKAHEAD ADDER 32

OUTBUS
Page 1
Page 2
Page 3
Page 4
Slide 5
Note a bus is a collection of two or more signal lines. It represents interconnection and data ow between two functional modules.
Slide 7
Page 5 Page 6
Timing Diagrams Schematic Diagrams

Figure 6-14 and 6-15 show two dierent schematic structures: at and hierarchical.
Page 1 Page 2 Page 3
A timing diagram illustrates the logical behaviors of signals in a digital circuit as a function of time. The most important information provided by a timing diagram is a specication of delay. See Fig. 6-19. Note a delay is subject to many factors and is often specied by a range between maximum and minimum delay or by a typical delay value. Slide 8
(b) GO READY
Slide 6
Page 4 Page 5 Page 6
tRDY DAT tDAT (a) GO ENB READY READY DAT tRDYmin tRDYmax DAT tDATmin
tRDY
tDAT
(c) GO
tDATmax
Gate Symbols
Dierent gate symbols will appear in schematic diagram of a circuit. Standard gate symbols have been introduced. Figures 6-3 and 6-4 show standard shapes for commonly used gates. Slide 9 Note a buer is a circuit that converts weak logic signals to strong ones.
Active Levels
Slide 11 Each signal has an active level associated with it. A signal is active high if it performs the named action when it is high. A signal is active low if it performs the named action when it is low. A signal is said to be asserted if it is at its active level. A signal is said to be negated if it is not activated.
AND
NAND
OR
NOR
BUFFER (a) (b) (c)
INVERTER
Active Levels (contd)

OR BUFFER NOR INVERTER
Slide 10
AND
Slide 12
NAND
Dierent naming conventions may be used to represent active levels. See table 6-1. Figure 6-5 shows how to represent the active levels of the input and output a logic circuit (as represented by a rectangular box). An inversion bubble to indicate active low while the absence of a bubble to indicate an active high. Alternatively, a logic symbol for a digital circuit may have its pins explicitly labeled as active high or active low.
T a bl e 5 - 1 Each line shows a different naming convention for active levels.
Active Low
READY ERROR.L ADDR15(L) RESET* ENABLE~ ~GO /RECEIVE TRANSMIT_L
Active High
READY+ ERROR.H ADDR15(H) RESET ENABLE GO RECEIVE TRANSMIT
Programmable Logic Arrays (PLA)

Slide 15 PLA is a combinational two level AND-OR device that can be programmed to realize any sum of products expression. A PLA often has a maximum number of inputs, outputs, and the product terms. See gs. 6.21 and 6.22.
Slide 13
DO ENABLE MY ... THING ... ... ... ... (a) (b)
DO ENABLE MY ... THING ... ... ... ...
I1 I2 I3 I4
READY REQUEST (a) GO READY REQUEST (b) GO_L
Slide 14
READY_L REQUEST_L (c)
GO
READY_L REQUEST_L (d)
GO_L
Slide 16
P1
P2
P3
P4
P5
P6 O1 O2 O3
The following is a programmed PLA. Give the output expressions.
I1 I2 I3 I4
Decoders
P1 P2 P3 P4 P5 P6 O1 O2 O3
Slide 17
Slide 19
A decoder is a multiple input and multiple output logic circuit that decodes the coded input. It maps an input code into an output code. The number of inputs is usually fewer than that of output. A decoder usually contains a special input called enable. It must be asserted before the decoder can perform its normal function. It is not counted as an input. See gure 6-31.
See Fig. 6-23 for programmed PLA. Note both the AND and OR gates are programmable. Another programmable logic device is
Decoder input code word

Slide 18 Programmable Array Logic (PAL), which has xed OR gates and only AND gates can be programmed. Slide 20
ma p
output code word enable inputs
T a b le 5 - 4 Truth table for a 2-to-4 binary decoder.
Inputs
EN I1 I0 Y3
Outputs
Y2 Y1 Y0
x 0 0 1 1
x 0 1 0 1
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 1 0 0 0
Binary Decoders
The most common decoder is the binary decoder where the number of output is the power of 2 of the number of input. For example, we have n to 2n binary decoder, where n is the number of input and 2n is the number of output. A binary decoder is used when you need to activate exactly one of 2n outputs based on n inputs. Note the dont care notation in the truth table.
1 1 1 1
Slide 21
Slide 23
Note the truth table will be dierent if the active levels for input/ouput are changed. What are the truth table if the outputs are all active low ? The input and output codes are not limited to consecutive decimal numbers but may represent any consecutive physical entities. For example, see table 6-5.
Binary Decoders (contd)

Table 6-4 gives the truth table of a 2-to-4 binary decoder. The logic symbol and the logic diagram of a 2-to-4 binary decoder are shown in Figure 6-32.
I0 I0 I1 I1 EN I0
Disk Position
I2
I1
I0
Binary Decoder Output

Y0 Y1 Y3 Y2 Y6 Y7 Y5 Y4
Slide 22
2-to-4 decoder I0 I1 EN Y0 Y1 Y2 Y3 I1
Y0
Slide 24
Y1
0 45 90 135 180 225 270 315
0 0 0 0 1 1 1 1
0 0 1 1 1 1 0 0
0 1 1 0 0 1 1 0
Table 5-5 Position encoding for a 3-bit mechanical encoding disk.
Y2
Y3 EN (a) (b)
3-to-8 decoder Y0 Y1 SHAFTI0 SHAFTI1 SHAFTI2 ENABLE I0 I1 I2 EN Y2 Y3 Y4 Y5 Y6 Y7 DEG0 DEG45 DEG135 DEG90 DEG315 DEG270 DEG180 DEG225
Logic Symbols for Decoders

The logic symbol for a decoder is drawn with input pins on the left and output pins on the right of the symbol. The active levels of the input and output pins need be specied. Each pin has two names: one internal and one external name (often left out). For active high, they are the same. For active low, the external name is suxed with L . Also, the pins are arranged from top to bottom in order of LSB to MSB.
1/2 74x139 G A B Y0 Y1 Y2 Y3 G_L A B 1/2 74x139 G A B Y0 Y1 Y2 Y3 Y0_L Y1_L Y2_L Y3_L
Slide 25
Slide 27
(a)
(b)
Also not all outputs of a decoder may be used, e.g., for BCD
Standard Binary Decoder ICs

Slide 26 decoder, it only produces 10 outputs. Slide 28 74 139 74 138
74 139 Dual 2-to-4 Decoder

The 74 139 dual 2-to-4 decoder consists of two independent but identical 2-to-4 decoders, contained in a single MSI (middle size integration) chip. It is designed with active-low at outputs. The gure below gives the logic diagram and logic symbol for the decoder. The truth table for half of the 74 139 dual 2-to-4 decoder is shown in table below. Note for both input and output the top input and the top output bit represent the LSB while the bottom input bit and the bottom output bit represent the MSB.
Table 5-6 Truth table for onehalf of a 74x139 dual 2-to-4 decoder.
Inputs
G_L B A Y3_L
Outputs
Y2_L Y1_L Y0_L
Slide 29
Slide 31
1 0 0 0 0
x 0 0 1 1
x 0 1 0 1
1 1 1 1 0
1 1 1 0 1
1 1 0 1 1
1 0 1 1 1
74 138 MSI 3-to-8 Decoder

(4) (1) (5)
1Y0_L
1
74x139 1G
2
1G_L
1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3
4 5 6 7
1Y1_L
1A 3 1B
15
(6) (2) (7)
1Y2_L
2G 2A 2B
12 11 10 9
It has three enable inputs and its outputs are active low. All the three enable inputs must be asserted before the decoder can perform its function. Its logic diagram and logic symbol are shown in Figure 6-35.
(a)
(15)
1A 1B
14
(3)
1Y3_L
13
Y0_L
(b)
6
74x138 G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7
Slide 30
(a)
(12) (15) (11)
(b) 2Y0_L
Slide 32
G1 G2A_L G2B_L
(6) (4) (5)
(14)
Y1_L
(13)
2G_L
Y2_L
2 3
2Y1_L
1/2 74x139 G Y0 Y1 Y2 Y3
(12)
Y3_L
(10) (14) (9)
2Y2_L
2A 2B
A B
(11)
Y4_L
(10)
(13)
2Y3_L
(c)
(1)
Y5_L
(9)
(2)
Y6_L
(3)
(7)
Y7_L
+5V R
6 4 5
74x138 G1 G2A G2B

1
Truth table is shown in Table 6-6. An output is asserted if only the decoder is enabled and the output is selected (e.g., Y 5L ).
T a b l e 5 - 7 Truth table for a 74x138 3-to-8 decoder.
Inputs
G1 G2A_L G2B_L C B A Y7_L Y6_L Y5_L
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U1
15 14 13 12 11 10 9 7
DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L
Outputs
Y4_L Y3_L Y2_L Y1_L Y0_L
N0 N1 N2 N3 EN_L
A 2 B
3
0 x
x 1 x 0 0 0 0 0 0 0 0
x x 1 0 0 0 0 0 0 0 0
x x x 0 0 0 0 1 1 1 1
x x x 0 0 1 1 0 0 1 1
x x x 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 0 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
Slide 33
x 1 1 1 1 1 1 1 1
Slide 35
74x138
6 4 5
G1 G2A G2B
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U2
15 14 13 12 11 10 9 7
DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L
A 2 B
3
Cascading Binary Decoders

Slide 34 Multiple binary decoders can be combined in cascade to decode larger code words. The gure below shows how to combine two 3-8 decoders into a 4-to-16 decoder. Figure 6-37 shows a 5-to-32 decoder constructed from 5 3-8 decoders.
Logic Expression from Decoders

Slide 36 How to build F =
XY Z (2, 4, 7)
using a 74x138 decoder ?
Multiplexers (contd)
The input of a multiplexer consist of
Multiplexers
A multiplexer is a digital switch that determines which of its n input data should be routed to output. It is a useful device in any application where data must be switched from multiple sources to a destination source. For example , the multiplexer between the processors registers and its arithmetic logic unit (ALU). The data from one of the registers must be routed to ALU for execution.
n input data, each of which is b bit wide. n is usually 2,4,8,16. and b is 1,2, 3.. Slide 39 s selections inputs to determine which of the n sources to select. s = log2 n. an enable input, which must be asserted for the multiplexer to function. Output: one of the n input data see gure 6-59.
Slide 37
(b)
1D0 1D1 1Y 1Dn1
(a) enable s
multiplexer EN SEL b D0 b n data sources b D1 Y Dn1 b data output
2D0 2D1 2Y 2Dn1
Standard Multiplexers ICs

Slide 40 74 151 selects among 8 1-bit inputs. It provides both active high and low output as shown in Figure 6-60.
Slide 38
select
bD0 bD1 bY bDn1
SEL
EN
EN_L
(7)
Standard Multiplexers ICs (contd)

A A B B C C
D0
(4)
See logic symbols and truth tables for 74 157 (2 inputs and 4 bit )
(a) G_L S
(15) (1)
D1
(3)
(b)
15 1 2
74x157 G S 1A 3 1B
5 4
D2
(2)
1Y 2Y 3Y 4Y
D3
(1) (5) (6)
Y Y_L
1A
(2)
6 11 (4)
D4
(15)
2A 2B 3A 3B 4A 4B
1B
(3)
1Y
10 14 13
12
Slide 41
D5
(14)
Slide 43
74x151
2A
(5)
D6
(13)
D7
(12)
4 3 2
D0 D1 D2 D3 D4 D5 D6 D7
Y Y
5 6
3A
(11)
(11)
1 15 14
(9)
3B
(10)
3Y
(10)
13 12
4A
(14)
(12)
(9)
(a)
(b)
4B
(13)
4Y
Its truth table is shown in table 6-42.

Table 5-34 Truth table for a 74x151 8-input, 1-bit multiplexer.
Inputs
EN_L C B A
Outputs
Y Y_L
Inputs
G_L S 1Y
Outputs
2Y 3Y 4Y
1 0 0 0 0 0 0 0 0
x 0 0 0 0 1 1 1 1
x 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
0
D0 D1 D2 D3 D4 D5 D6 D7
1
D0 D1 D2 D3 D4 D5 D6 D7
x 0 1
0
1A 1B
0
2A 2B
0
3A 3B
0
4A 4B
Ta bl e 5 - 3 5 Truth table for a 74x157 2-input, 4-bit multiplexer.
Slide 42
Slide 44
0 0
and 74 153 (4 input 2-bit).
EN 11 A 10 B 9 C
(7)
2B
(6)
2Y
74x151
(a) A
(14)
XA0 XA1 XA2 X0
7 11 10 9 4 3 2 1 15 14 13
EN A B C D0 D1 D2 D3 D4 D5 Y Y
5 6
(2)
X1 X2 X3 X4 X5 X6 X7 1/2 74x139 XEN_L

1 4 EN0_L 5 EN1_L 6 EN2_L 7 EN3_L 7
XO0_L
1G_L
(1)
D6 12 D7
U2
1G
2 3
1Y0 1Y1 1Y2 1Y3 U1
74x151 EN A
1C0
(6)
XA3 XA4
1A 1B
11 10
B 9 C
4 3 2 1
1C1
(5) (7)
X8 X9
D0 D1 D2 D3 D4 D5 D6 D7
Y Y
5 6 XO1_L
1Y
X10 X11 X12 X13 X14 X15
15 14 13 12
1C2
(4)
1/2 74x20
6
Slide 45
1C3
(3)
Slide 47
7 11
U3
2 4
XOUT
74x151 EN A B C D0 D1 D2 D3 D4 D5 D6 D7 Y Y
5 6 XO2_L
U6
2G_L
(15)
(b)
14 2
74x153 A
X16 X17 X18 X19 X20 X21
10 9 4 3 2 1 15 14 13 12
2C0
(10)
1 6
2C1
(11) (9)
B 1G 1C0 5 1C1 4 1C2

3
1Y
X22 X23
U4
2Y
15 10 11 12
2C2
(12)
1C3 2G 2C0 2C1 2C2 2C3
74x151
7 11 10 9
EN A B C D0 D1 D2 D3 D4 Y Y
5 6 XO3_L
2Y
2C3
(13)
13
X24 X25 X26 X27 X28 X29 X30 X31
4 3 2 1 15 14 13
D5 D6 12 D7
U5
Expanding Multiplexers
Slide 46 Smaller multiplexers can be combined to form a larger multiplexer. See Fig. 6-62. Slide 48
Combinational Circuits with Multiplexers

How to build F =
XY Z (2, 4, 7)
using a 74x151 MUX ?
Opposite the operation of a decoder, a binary encoder assumes only one of its inputs is activated at a time and the output corresponds to the asserted input. See the truth table below.
Encoders
Multiple-input/multiple-output device. Slide 49 Performs the inverse function of a Decoder. Outputs ( m ) are less than inputs ( n ). Converts input code words into output code words. It may be applied to handling multiple devices requests But, no simultaneous requests, i.e., only one input can be activated at a time. Slide 51
Binary Encoders
The simplest encoder is the binary encoder, whose number of input is 2n and the number of output is n, such 8-to-3 binary encoder below.
Priority Encoders
To handle multiple requests, i.e., to allow multiple inputs to be asserted at the same time, priority encoder may be used.
Slide 50
Slide 52
74x148 8-input priority encoder (contd) Priority Encoder (contd)

Assign priorities to the inputs When more than one input are asserted, the output generates the code for the input with the highest priority Slide 53 Slide 55
It is clear that the output only corresponds to the input with the highest priority. The low priority inputs are ignored, independent of their states (dont care). Output enable is asserted only when all inputs are not activated. The GS output is asserted if any of of the
74x148 8-input priority encoder
Slide 54
Slide 56
input is asserted.
Three State Buers

Slide 57 A three state buer contains two inputs and one output. One of the inputs is enable input. It must be asserted before the buer can function. The three state buer can be inverting or non-inverting with either active high or low enable input. See gure 6-51 for example. Slide 59
Use of 3 State Buers

Three state buer may be used to allow multiple sources to share a single line, as long as only one can be active at a time. See Fig 6-52, which shows the use of three state buers allow to 8 sources of data to drive a single line at a time.
Standard 3 State Buers ICs

Several independent three state buers may be packaged in a single SSI IC or MSI IC. 74 125 and 74 126 each contains 4 three state buers. 74 541 contains 8 three state buers. Slide 58
74x125
(4) (5) (6) (10) (9) (8)
(1) (2) (3)
(13) (12) (11)
(1) (2) (3)
(13) (12) (11)
Slide 60
74x126
(4) (5) (6) (10) (9) (8)
XOR and XNOR gates

XOR (exclusive-or) is a 2 input gate whose output is 1 if exactly one of its input is 1 (i.e. when the two inputs are dierent). XNOR (exclusive-nor) is a 2 input gate whose output is 1 if its input are the same. Slide 61
X Y XY (XOR) (X Y) (XNOR)
Comparator
A circuit that compares two binary inputs and indicates if they are equal are called comparator. By denition, an XOR gate is a one-bit comparator. Multiple XOR gates can be used to perform multiple bit comparator. For example, 4 XOR gates for a 4-bit comparator is shown in Figure 6-74. Slide 63
(b) A0 B0 A1 B1 (a) A2 B2 1/4 74x86 A0 B0
1 2 3 1 2 4 5
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
Table 5-45 Truth table for XOR and XNOR functions.
74x86
3
DIFF0 74x02
2
U1
6
DIFF1
DF01_L 74x00
1 2 3
U1
9 10 8
U2 DIFF2 74x02
5 6 4
DIFF
DF23_L
U3
U1 DIFF A3 B3
12 13 11
U2 DIFF3
U1
U1
Refer to gure below for logic diagrams and symbols for XOR and XNOR gates.
How to determine if two inputs are equal ?
(a)
(b)
74 86 SSI IC contains 4 XOR gates.

1
Adder
9 10 8
Slide 62
Slide 64
An adder performs arithmetic addition of two operands using the addition table. An adder whose two operands are 1-bit is called half-adder. An adder whose two operands are more than 1 bit are called full adder.
4 5
12 13
11
Full Adder (contd) Half Adder

The inputs and output of a half adder are: Inputs: the two operands X and Y Outputs: 1) sum (S) Slide 65 2) carry out (CO) Slide 67
X Y CIN (b) S X Y CIN
S COU T
= =
X Y CIN X Y + X CIN + Y CIN
see gure 6-83 for its logic diagram and symbol

full adder S COUT
S CO
= X Y = X Y
(a) COUT X COUT (c) S Y CIN
A half adder does not involve carry-in.
Full Adder
A full adder handles more than one bit of binary addition (with carry). While performing bitwise addition, each bitwise addition has the following inputs and outputs: Inputs: Slide 66 input operands X and Y carry in (CIN) Outputs:
s3 s2 s1 s0
Ripple Adder
A ripple adder is a cascade of n full-adders, each of which handles one bit. See Figure 6-84 for 4-bit ripple adder. It can perform 4-bit addition. Slide 68
c4 x3 X COUT S y3 Y CIN c3 x2 X COUT S y2 Y CIN c2 x1 X COUT S y1 Y CIN c1 x0 X COUT S y0 Y CIN c0
sum S carry out (CO)
Ripple Subtractor Full Subtractor

A full subtractor handles 1 bit binary subtraction. Inputs: operands X and Y Slide 69 a borrow in (BIN) Outputs: dierence (D) a borrow out (BOUT)
b_Ln
5
We can similarly build a n bit ripple subtractor by cascading n full subtractors as shown in gure 6-85.
(a)
1 2
(b) X Y 74x999 COUT CIN S

4
(c)
1 2
X
3
Y
5
X Y 74x999 BOUT BIN D

4
BOUT BIN D
(d)
Slide 71
xn1
yn1
1
xn2
yn2
3
x0
y0
13
74x04
2 1 2 1 4 2
74x04
74x04
12 1 2

4
b_Ln1 5

4
b_Ln2
b_L1 5

4
b_L0 1
dn1
dn2
d0
Note a full subtractor can be implemented with a full adder circuit plus inverters.
Full Subtractor (contd)

= X Y BIN = X Y + X BIN + Y BIN
Slide 70
D BOU T
This is very similar to the equations for full adder
Clock Signal Most sequential circuits undergo a state change by a clock signal. For clock signal, it may be active high or active low. Its state my include high, low, rising edge, and falling edge. Its parameters include period, frequency, and duty cycle. See gure 7-1.
(a) CLK state changes occur here
Chapter 7 Sequential Logic Design Principles A sequential circuit is one whose output depends not only on its current input but also on its previous inputs. This implies that sequential circuit has memory that can remember previous inputs. Examples of sequential circuits: TV channel controller, elevator controller, etc.. This chapter introduces two types of sequential circuits: feedback sequential circuit and clock synchronous state machine.
Slide 1
Slide 3
tH tper
tL
period = tper frequency = 1 / tper duty cycle = tH / tper
(b) CLK_L
state changes occur here
tL tper
tH duty cycle = tL / tper
State In addition to input, another important attribute of a sequential circuit is its state. The state of a circuit determines the internal condition of the circuit. For a sequential circuit, its output is determined not only by the input but also determined by its state. A state can be stable or metastable. Slide 2
Bistable Circuit The simplest sequential circuit is bistable circuit consisting of two inverters. It has no inputs and two outputs as shown in gure 7-2. Its state is characterized by the values of its two outputs. It has only two states (1 ,0) or (0,1). Its output only depends on its previous input through a feedback loop.
metastable
Slide 4
stable
stable
S-R Latch
Vin1
Vout1
An S-R latch consists of two NOR gates as shown in gure 7-5.
S 0 0 1 1 (b)
R 0 1 0 1
QN
last Q last QN 0 1 0 1 0 0
(a)
QN
Slide 5
Vin2
Vout2
Slide 7
Q_L
The circuit has two external inputs, two feedback loops, and two outputs. The circuit remembers its previous state if its two external inputs are 0 (negated). Q=R (LQ +S) QN= S (LQN +R )
S-R Latch (contd) One input (S) sets the output (Q) and the other (R) input clears the output (Q). If both inputs are asserted, both outputs are 0 (metastable state may occur). See truth table in gure 7-5(b) and timing (operation) diagram in gure 7-6.
S
Latches and Flip-Flops Latches and ip-ops are the basic building blocks for most sequential circuits. They each represents a feedback loop made up of logic gates. A latch diers from a ip-op in that the former continuously samples its input , independent of a clock signal while the later samples its input only at times determined by a clock. Flip-ops are also called latches with dynamic clocks.
Slide 6
Slide 8
(a)
R Q QN (b)
Figure 7-7 gives the logic symbol of the S-R latch. A S-R latch may be used as a switch. Note the circuit diagram, S corresponds to QN and R corresponds to Q.
Timing Parameters for S-R Latch propagation delay-the time it takes for a transition from input to produce a transition on an output signal. The output transition can be low to high or high to low. Minimum pulse width-it is the minimum time for an input signal to go from one state to another and then return to its original state. If the time is too short, this may cause metastable state. See g. 7-8.
S (1) R (2) Q
S R
Q QN
S R
Q Q
S R
Q QN
Slide 9
(a) (b) (c)
Slide 11
tpLH(SQ)
tpHL(RQ)
tpw(min)
-R Latch S Avoiding Unstable Behaviors Two undesirable behaviors with a latch are: oscillation and metastable. The former may be induced by changing R and S from 1 to 0 at the same time (see gure 7-6(b)). The latter may be caused if the input signal is changed back and forth too fast (see gure 7-8). The former can be avoided by not allowing R and S to both be 1 at the same time. The latter may be avoided by ensuring the input signals satisfy the minimum-pulse-width (ppw(min) ). -R latch diers from S-R latch in that the two external The S inputs and the two feedback loops are both active low. It consists of two NAND gates. See gure 7-9.
(a)
S_L or S Q
(b)
S_L R_L 0 0 1 1 0 1 0 1
Q 1
QN 1
(c)
S R Q Q
Slide 10
Slide 12
R_L or R
QN
0 1 1 0 last Q last QN
+ LQ R Q=S +S LQN QN = R It is preferred over S-R latch due to the use of NAND gates.
-R Latch (contd) S
S
Ignored since C is 0.
Ignored until C is 1.
Slide 13
Inputs are active low. The output remains the same as S-R latch. corresponds to Q and R corresponds to In the circuit diagram, S NQ. When S and R are both asserted (equal to 0), then the two outputs are 1 instead of 0 as for S-R latch. When both inputs are -R latch, S negated, the latch remembers its previous state. For S clears Q. sets Q and R
R C
Slide 15
Q QN
S-R Latch with Enable (gated SR latch) An enable input is added to the S-R latch, yielding a 3-input S-R latch. The S-R latch behaves like a S-R latch if the enable input is asserted. It, however, assumes its previous state if the enable input is negated. See its truth table in gure 7-10 and timing diagram in gure 7-11. Note the dierence in circuit diagrams between an S-R latch and S-R with enable.
D Latch A D-latch is a special S-R latch with enable. It is useful when you need a device to store (remember) a bit of data. Its R input is generated by inverting its S input, leading to one external input D. see gure 7-12.
D Q C D 1 1 QN (a) (b) 0 0 1 x Q 0 1 QN 1 0
D C Q Q
Slide 14
Slide 16
last Q last QN (c)
(a)
S Q C QN R
(b)
S R C 0 0 1 0 1 1 1 0 1 1 1 1 x x 0
QN
(c)
S C R Q Q
last Q last QN 1 0 0 1 1 1 last Q last QN
If both S and R are 1 when the enable changes from 1 to 0, this circuit output may oscillate (see gure 7-11).
This eliminates the case where both inputs are asserted simultaneously (avoid oscillation). Its output follows its input if the enable input is asserted. If the enable input is negated, its output retains its previous state. See gure 7-13.
Positive Edge-Triggered D Flip-Flop

D C
Slide 17
Slide 19
For a latch without enable, the output continuously samples input. For a latch with enable, the output continuously samples input when the enable is asserted. For a ip-op, the output samples input only at a specic time determined by an external clock signal.
Positive Edge-Triggered D Flip-Flop D Latch (contd) D-latch, however, can not eliminate the metastable problem with S-R latch. The latch may enter a metastable state if the input signal D changes back and forth too fast or it changes during the setup- and hold-time of the enable signal C as shown in gure 7-14.
D
Slide 18
Slide 20
It consists of two D-latches connected in series and a clock signal. The rst one is called master while the second one is called slave latch. The salve always follows the master. While the clock is low, the master latch is enabled and its output follows its D input. When the clock makes a low-to-high change, the master latch is disabled and the last value it saw is stored and transfered to the slave latch. Refer to gure 7-15 (a).
C (1) Q (2) (3) (4) (5)
tpHL(DQ) tpLH(CQ)
tpHL(CQ) tpLH(DQ) tpLH(DQ)
thold tsetup
(a) D
D C Q
(b) QM
D C Q Q
(c) D 0 1 x x 0 1 CLK Q 0 1 QN 1 0
D CLK Q Q
Q QN
CLK
last Q last QN last Q last QN
Positive Edge-Triggered D Flip-Flop(contd) The slave is enabled while the clock is high, its output follows its input. However, its output only changes at the time the clock goes high since its input is connected to the master and the master can not change when the clock is high. This produces the edge-triggered eect. The output follows input only when the clock is at its rising edge. See gure 7-16 and Fig. 7-15 (b). Slide 21
D CLK QM Q QN
Edge-Triggered D Flip-Flop with Enable An enable input is added to the edge-triggered D ip-op to allow it to assume its previous value even at the rising edge of the clock signal. The enable signal does not matter if the clock signal is not at its rising edge. see gure 7-21.
(a) D EN
D CLK Q Q
Slide 23
(b) D EN CLK 0 Q QN 1 x x x 1 1 0 x x 0 1 Q 0 1 QN 1 0
(c)
D EN CLK Q Q
last Q last QN last Q last QN last Q last QN
CLK
See Fig. 7-15(c) for the logic symbol of D-FF. Note the dierence from the that of D latch. Metastable state still occurs if the input
Edge-triggered J-K Flip-Flop signal changes during the setup and hold time of the clock signal. See Fig. 7-17.
D
CLK
Slide 22
tpLH(CQ) tpHL(CQ)
thold tsetup
Slide 24
In summary, the positive edge-triggered D ip-op samples its input only when the clock signal at its rising edge. Its output follows its input only when the clock signal is at its rising edge. Its output assumes its previous state if the clock input is asserted or negated.
It contains an edge-triggered D ip-op. Here the J-K ip-op is triggered by the rising edge of the control signal. The ip op assumes its previous state if the control signal is asserted or negated. At the rising edge of the clock (control) signal, the Q output follows J input while the QN outputs follows K input. While both J and K are asserted at the same time and the clock is at its rising edge, Q assumes previous QN and QN assumes previous Q. See gures 7-28 and 7-29
(a)
(b) J J
D Q Q
(c) K CLK x x 0 1 0 1 0 1 Q QN
J CLK K Q Q
x Q QN x 0 0
last Q last QN last Q last QN last Q last QN 0 1 1 0
K CLK
CLK
1 1
last QN last Q
EN T
J K CLK
D CLK
Q Q
Q QN (b)
EN T
J CLK K
Q Q
Q QN
(a)
Slide 25
Slide 27
(a)
(b) EN
EN T Q Q
T Q
Positive Edge Triggered T Flip-Flop

A T (toggle) ip-op changes state on every tick of the clock. It can be constructed from a D ip-op or from a J-K ip-op as shown in Figure 7-31 and F-32.
(a)
D Q Q
(b) Q T T
CLK
Clocked Synchronous State Machine Analysis

1
J CLK K Q Q
Q QN
QN
Slide 26
Slide 28
Its output follows the clock signal at half the frequency of the input.
Q T Q
State machine is a generic name given to a sequential circuit. clocked refers to the ip-ops of the sequential circuit are controlled by a clock signal. Synchronous all ip-ops use the same clock signal,which causes the op-ips to change states at each tick (rising/falling edge) of the clock.
T Q (b)
(a)
Figure 7-33 shows a T FF with enable.
State Machine Structure A state machine consists of three components: state memory, next-state logic, and output logic as shown in gure 7-35.
inputs inputs Next-state Logic F excitation State Memory clock input current state Output Logic G
Next-state Logic F
excitation
State Memory
current state
Output Logic G
outputs
outputs
clock input
Slide 29
clock signal
Slide 31
clock signal
Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
state memory is a set of ip-ops that store current state. Given n ip-ops, it can store 2n states. Its inputs include an excitation signal and a clock signal (which connects to all ip-ops). Its output is current state.
An Example of a State Machine State Machine Structure (contd) The next-state logic determines the next state of the state machine. It is a function of input and current state. The output logic determines the output of the state machine. It is a function of input and current state. Both the next-state logic and output logic are combinational circuits. Sequential circuit whose output depends on both its input and current state is called Mealy machine. Sequential circuit whose output depends only on current state is called Moore machine (see gure 7-36).
input EN EN EN D0
D CLK Q Q
Next-state Logic F
State Memory
Output Logic G output
excitation Q0
MAX
Slide 30
Slide 32
Q0 Q0 D1
D CLK Q Q
Q1
Q1 Q1
clock signal CLK
current state
Characteristic Equations The characteristic equation of a latch or ip-op species the ip-ops next state as a function of its current state and inputs when the the enable is asserted (for latch) or when the clock is at its rising edge (for FFs). See table 7-1.
Device Type Characteristic Equation
Q = S + R Q Q = D Q = D Q = EN D + EN Q Q = S + R Q Q = J Q + K Q
Slide 33
S-R latch D latch
Ta bl e 7 - 1 Latch and flip-flop characteristic equations.
Analysis of State Machine Slide 35 The goal of analysis of state machine is to characterize the behavior of sequential circuit in terms of relationship between its input, current state, next state, and output (note how this diers from combinational circuit analysis).
Edge-triggered D flip-flop
D flip-flop with enable
Master/slave S-R flip-flop Master/slave J-K flip-flop
Edge-triggered J-K flip-flop Q = J Q + K Q T flip-flop Q = Q

T flip-flop with enable Q = EN Q + EN Q
Note characteristic equation only describes functional response to
Analysis of State Machine Three steps in state machine analysis: the control inputs when output samples input, e.g., during a clock tick for FF and when the enable is asserted for latch. 1. Determine the next state function F and output function G Slide 36 2. Use F and G to construct state/output table that completely species the next state and the output of the circuit for every possible combination of current state and input. 3. Draw a state diagram
Slide 34
Analysis of State Machine: Example determine excitation equation identify the FF, the state variables, and give the characteristic equation construct transition equations Slide 37 build transition table build state table Derive the output equation build state/output table draw state diagram Analysis of an example state machine Slide 39
(a)
Q1 Q0 0
EN 1
(b)
S
A B C D
EN 0
A B C D S
(c)
1
B C D A
EN S
A B C D
0
A, 0 B, 0 C, 0 D, 0
1
B, 0 C, 0 D, 0 A, 1
00 01 10 11
00 01 10 11
01 10 11 00
Table 7-2 Transition, state, and state/output tables for the state machine in Figure 7-38.
Q1 Q0
S, MAX
state diagram in gure 7-39.
Next-state Logic F
State Memory
Output Logic G output
EN = 0
(MAX = 0)
EN = 0 A EN = 1
(MAX = 0) (MAX = 0)
input EN EN EN D0
excitation Q0
MAX
D CLK
Q Q
EN = 1
(MAX = 1)
EN = 1
(MAX = 0)
Q0 Q0 D1
D CLK Q Q
Q1
Slide 38
Q1 Q1
Slide 40
EN = 0
(MAX = 0)
EN = 1
(MAX = 0)
C EN = 0
(MAX = 0)
clock signal CLK
current state
See g. 7-41 for a redrawn state machine Transition, state, and state/output table (Table 7-2) see the analysis of the state machine shown in g. 7-43
EN = 0 A
MAXS=0
EN = 0 EN = 1 B
MAXS=0
MAX
EN = 1
D0
EN = 1
Slide 41
EN CLK
D CLK
Q Q
Q0
D1
D CLK
Q Q
Q1
Slide 43
D
MAXS=1
EN = 1
C
MAXS=0
EN = 0
EN = 0
Analysis of Moore Machine Unlike Mealy state machine, the output of a Moore machine depends only on its current states . This dierence leads to dierent (simpler) state/output table and state diagram. For the state machine in Fig. 7-38, if the EN input to the output logic is removed, it becomes a moore machine. See table 7-3 and gure 7-40 for the state/output table and the state diagram. Slide 42
Table 7-3 State/output table for a Moore machine.
EN S
A B C D
Another Example of State Machine Analysis

Q1 X Q0 X Q2 Q2 Q0 X Q1 X Q2 Q1
D0
D CLK
Q Q
Q0
D1
D CLK
Q Q
Q1
Slide 44
1
B C D A
Z2
Q2 Q0 Q0 X CLK Q
D2
Q2 Z1
0
A B C D S
MAXS
0 0 0 1
CLK
Excitation equations Characteristic Equations
Table 7-5 Transition/output and state/output tables for the state machine in Figure 7-45.
(a)
Q1 Q0 00 01
XY 10 11
(b)
S
A B C D
XY 00
A, 0 B, 0 C, 0 D, 0 S
01
C, 1 D, 0 A, 0 C, 0
10
B, 0 C, 0 D, 0 A, 1
11
C, 1 D, 0 A, 0 C, 1
00 01 10 11
00, 0 01, 0 10, 0 11, 0
10, 1 11, 0 00, 0 10, 0
01, 0 10, 0 11, 0 00, 1
10, 1 11, 0 00, 0 10, 1
Q1 Q0, Z
, Z
Transition equations Slide 45 Transition, state/output table State diagram Slide 47
State Diagram
X Y A
Z = 0 unless otherwise indicated
X Y B
X Y
X Y Y Y
(Z = 1)
Y X Y X Y
(Z = 1)
C X Y
X Y X Y
(Z = 1)
D X Y
Analysis of State Machine with J-K FF

X Y Y Q1
J0 K0
J CLK K
Q Q
Q0
X Q0 Y X
X
Y
J1 K1
Q0 J CLK K Q Q
Q1
Q1 Q0 Q1 Y
Q0 X Y Q0
State Machine Design and Synthesis Slide 48 Like combinational design, design of state machine involves formalization of the problem description and the development of a sequential circuit to solve for the stated problem. It represents the reverse of state machine analysis.
Slide 46
CLK
Excitation equations Characteristic Equations Transition equations Transition, state/output table
State Machine Design Steps 1. Formalize the problem description with a state/output table or with a state diagram identify inputs, outputs, and possible states represent the identied inputs, outputs,and states with mnemonic names Slide 49 construct the state/output template instantiate the template based on the problem description using the named inputs, output,and states. 2. Assign binary combinations to the named states 3. Substitute the state-variable combinations into the state/output table to create a transition/output table. 4. Determine the number of FFs and identify a ip-op (D or J-K) 5. Derive an excitation table that shows the output of the next Slide 51
State Machine Design Example Problem Description Design a clocked synchronous (Moore) state machine with two inputs A and B, a single output Z that is 1 if : A had the same value at each of the two previous clock ticks, or B has been 1 since the last time that the rst condition was true Otherwise, the output should be 0. Since we are dealing with Moore machine, the second condition can be alternatively interpreted as the state of the machine stays the same if B has been 1 since last time condition 1 is true. See g. 7-45 for the timing diagram. Note a clock tick represents the rising edge of the clock signal. Between two neighboring clock ticks,
logic circuit as a function of inputs and current states. 6. Derive the excitation equations from the excitation table Slide 50 Minimize the excitation equation using K-map 7. Derive the output equation from the transition/output table. 8. Draw the logic diagram Slide 52
output stays the same.

CLOCK A B Z
Build state/output table Identify inputs,outputs,and possible states and name them Inputs: A,B Output: Z Slide 53 States: A1, A0, OK0 (A00), OK1(A11), INIT Construct the state/output template Instantiate the template based on the problem description using the named inputs, output,and states. See gures 7-46 and 7-47. Slide 55 State/output table
Ta bl e 7 - 6 State and output table for example problem.
AB S
INIT A0 A1 OK0 OK1
00
A0 OK0 A0 OK0 A0
01
A0 OK0 A0 OK0 OK0
11
A1 A1 OK1 OK1 OK1 S
10
A1 A1 OK1 A1 OK1
0 0 0 1 1
(a) Meaning
Initial state
AB
(b) 11 10
Z
AB
S
INIT ... ... ...
00
01
Meaning
Initial state Got a 0 on A Got a 1 on A
S
INIT A0 A1
00
A0
01
A0
11
A1
10
A1
0 0 0
(c) Meaning
Initial state Got a 0 on A Got a 1 on A Got two equal A inputs
AB
(d) 11
A1 A1
AB
S
INIT A0 A1 OK
00
A0 OK
01
A0 OK
10
A1 A1
Meaning
S
INIT A0 A1 OK
00
A0 OK A0
01
A0 OK A0
11
A1 A1 OK
10
A1 A1 OK
0 0 0 1
0 0 0 1
State Assignment Slide 56 Determine the number of binary variables needed to represent the named states and assign a specic binary combination to each state. For ve states, we need 3 binary state variables Q1 , Q2 , and Q3 . This means we need 3 ip-ops.
S
Slide 54
(a)
AB
Meaning
S
INIT A0 A1 OK
00
A0 OK A0 ?
01
A0 OK A0 OK
11
A1 A1 OK OK
10
A1 A1 OK ?
(b)
AB
Meaning
Initial state Got a 0 on A Got a 1 on A Two equal, A=0 last Two equal, A=1 last
S
INIT A0 A1 OK0 OK1
00
A0 OK0 A0
01
A0 OK0 A0
11
A1 A1 OK1
10
A1 A1 OK1
0 0 0 1
0 0 0 1 1
(c)
AB
Meaning
S
INIT A0 A1 OK0 OK1
00
A0 OK0 A0 OK0
01
A0 OK0 A0 OK0
11
A1 A1 OK1 OK1
10
A1 A1 OK1 A1
(d)
AB
Meaning
S
INIT A0 A1 OK0 OK1
00
A0 OK0 A0 OK0 A0
01
A0 OK0 A0 OK0 OK0
11
A1 A1 OK1 OK1 OK1
10
A1 A1 OK1 A1 OK1
0 0 0 1 1
0 0 0 1 1
S
State Assignment (contd) State assignment aects the complexity, eciency, and cost of the circuit. It may also aect the choice of the storage elements. State assignment needs experience. But some rules may apply. For example, select the initial state that the circuit can easily be set to and minimize the number of state variable changes at each transition. Slide 57 See table 7-6 for possible state assignment. Pay attention to the decomposed scheme, where Q1 indicates if it is INIT or not, Q2 indicates the value of output, and Q3 indicate the value of A.
Assignment State Name
INIT A0 A1 OK0 OK1
Excitation Table Assuming we use D ip-op, the transition table is the same as excitation table as shown in table 7-8 except that Q1,Q2, and Q3 are replaced by D1, D2, and D3 respectively. Slide 59
Ta bl e 7 - 9 Excitation and output table for Table 7-8 using D flip-flops.
AB Q1 Q2 Q3 00 01 11 10 Z
000 100 101 110 111
100 110 100 110 100
100 110 100 110 110
101 101 111 111 111
101 101 111 101 111
0 0 0 1 1
Simplest Q1Q3
Decomposed Q1Q3
One-hot Q1Q5
Almost One-hot Q1Q4
000 001 010 011 100
000 100 101 110 111
00001 00010 00100 01000 10000
0000 0001 0010 0100 1000
Table 7-7 Possible state assignments for the state machine in Table 7-6.
D1 D2 D3
Excitation Equation Transition Table Substituting the assigned binary states to the state table to obtain the transition table as shown in table 7-7.
AB
Slide 58
Q1 Q2 Q3
00
01
11
10
000 100 101 110 111
100 110 100 110 100
100 110 100 110 110
101 101 111 111 111
101 101 111 101 111
0 0 0 1 1
Ta bl e 7 - 8 Transition and output table for example problem.
Derive the excitation equations and minimize them using K-map assuming the output for the unused states are either 0 or dont care. see gure 7-50. Note how to create a 5-variable K-map from 2 4-variable K-maps. For the 2 4-variable K-maps, cells in the same position are considered adjacent. Ignore Dont cares Slide 60
D1 Q2 Q3 00 01 11 Q2 10 Q1=0 0 0 B Q2 Q3 A D2 Q2 Q3 00 01 11 Q2 10 Q1=0 0 0 B 0 0 AB 00 0 0 0 01 0 0 0 11 0 0 0 A 10 0 0 Q3 0 Q2 10 Q1=1 1 1 B 1 0 11 0 1 1 1 Q1 Q3 A Q1 Q2 B Q1=0 B Q1=1 B Q2 10 0 0 0 0 Q2 Q3 00 01 AB 00 1 0 01 1 0 11 0 1 A 10 0 1 Q3 11 0 0 0 0 Q2 10 0 0 1 1 Q1 Q3 A D3 Q2 Q3 00 01 AB 00 0 0 01 0 0 11 1 0 A 10 1 0 Q3 11 0 0 1 1 Q2 Q3 00 01 0 0 AB 00 1 0 0 01 1 0 0 11 1 0 0 A 10 1 0 Q3 0 Q2 10 Q1=1 1 1 B 1 1 Q1 11 1 1 1 1 Q2 Q3 Q2 Q3 00 01 AB 00 1 1 01 1 1 11 1 1 A 10 1 1 Q3
Q1 A AB 00 0 0 01 0 0 11 1 1 A 10 1 1 Q3
Q1 Q2 Q3
Output Equation D1=Q1+ Q2Q3 Slide 61 D2=Q1Q3A+Q1Q3A+Q1Q2B D3=Q1A + Q2Q3A Slide 63 Derive the output equation from the excitation and output table. If do not consider dont cares, Z= Q1Q2 If include dont cares, Z=Q2
Excitation Equation (contd) Account for Dont cares

D1 Q2 Q3 00 01 11 Q2 10 Q1=0 d d B d d AB 00 1 d d 01 1 d d 11 1 d d A 10 1 d Q3 d Q2 10 Q1=1 1 1 B 1 1 11 1 1 1 1 Q2 Q3 1 00 01 AB 00 1 1 01 1 1 11 1 1 A 10 1 1 Q3
Logic Diagram draw the logic diagram based on the minimal excitation equation, the output equation, and the D ip-ops. See the logic diagram below (note here the unused states are assumed to be dont-cares).
D1
Q1
CLK Q CLR Q1
A
D2
AB 00 00 01 11 0 d d d 01 0 d d d B 11 0 d d d
A 10 0 d Q3 d Q2 d Q2 Q3
AB 00 01 00 01 11 10 Q1=1 1 0 0 1 1 0 1 1 B 11 0 1 1 1
A 10 0 1 Q3 1 0 Q3 A Q2 B Q1 Q3 A
D3 Q2 Q3
AB 00 00 01 11 0 d d d 01 0 d d d B 11 1 d d d
A 10 1 d Q3 d Q2 d A Q2 Q3
AB 00 00 01 11 10 Q1=1 0 0 0 0 01 0 0 0 0 B 11 1 1 1 1
Slide 62
Q2 Q3
10 1 1 Q3 1 1
Slide 64
A B
Q3 A Q3 A Q2 B
D2
Q2
CLK Q CLR
Q2 10 Q1=0
Q2 10 Q1=0
D3
D
Q3
CLK Q CLR
RESET_L
D1=1 D2=Q1Q3A+Q3A+Q2B D3=A
CLK
Can we design a Mealy machine to achieve the same ? or the same Moore machine with a dierent FF such as with a T FF or with a
Excitation table for J-K FFs Take the J-K FFs for example, from its characteristic equation, we can derive its characteristic table as follows. Then from the above characteristic table we can derive its excitation table as follows.
Slide 65
JK FF ?
Slide 67
Excitation table for T FFs with Enable State Machine Design with T and J-K FFs For D FF, the excitation table for D FF can be easily derived from the transition table. But for T and J-K FF, the excitation table is not that straightforward. Slide 66 From the characteristic of a FF, we can derive its excitation table. The excitation table species the inputs of a FF as a function of its current and next states. Specically, given we know the current state as well as what we desire about the next state of the FF, we want to decide what inputs we should provide to the FF in order to achieve the transition from current state to the desired next state. Slide 68 Similarly, for T FFs, its excitation table can be derived similarly from its characteristic function as follows
Excitation Table for D, T with EN, and JK FF
Slide 69
Slide 71
Note such a format of excitation table applies to all FFs.
Given the excitation table, show how to construct a T FF (or T FF with enable from a D FF or JK FF)?
Excitation Table with J-K FF Change the transition table (table 7-8) to the following format Sequential Circuit Design Example Problem: Design a Moore state machine that accepts an input binary sequence such as 001010011101 .... Its output is zero except when the number of 1s that have been input is a multiple of three. Implement the machine using as few as ip-ops as possible. Steps: state/output table, transition table, excitation table, minimized excitation equations, minimized output equations, and diagram.
Slide 70
Slide 72
Complete the excitation table using the transition table by transferring the numbers in table 7-8 to and the J-K excitation table. We can then easily derive the excitation equations from the table.
Input, output, States Input: X Output: Z States: Slide 73 INIT-inital state S0-the number of 1s is multiple of 3 S1-the number of 1s is 1 in excess of multiple of 3 S2-the number of 1s is 2 in excess of multiple of 3 Implement this state machine using D, T, and J-K FFs respectively. Slide 75 Word Problem 1 Design a circuit that detects an input sequence of 101 and that allows overlaps. The circuit can be a Moore or a Mealy machine. Steps: state diagram, state/output table, transition table, excitation table, minimized excitation equations, minimized output equations, and diagram. Implement it using one D FF and one JK FF.
Word Problem 2 State Machine Design using State Diagrams Slide 74 State machine design with state diagram presents a graphical design approach. It is more intuitively appealing. Caution, however, must be exercised while using state diagrams since the constructed state diagram may be ambiguous. Slide 76 Design a sequential circuit that has one input (X) and one output (Z). The circuit examines groups of three consecutive inputs and produces an output. The output is Z=1 if the input sequence 1011 occurs. Draw the state diagram Give the state/output table design it as a Moore and Mealy machine ? what is the dierence ?
Counter Design (section 8.4-8.4.4) A counter increments at each clock tick. Input is a clock tick and output is the current state. Its state diagram is a single circle. A counter with m states is called a modulo-m counter or divide-by-m counter. A counter can be constructed with dierent types of FFs. But the most convenient FF for counter is T FF. Asynchronous Ripple Counter Slide 79 The simplest counter is a ripple counter constructed by cascading T FFs. See Fig. 8-24 below.
Slide 77
Q0
CLK
T Q
Q T
Q1
Counter Design Slide 78 Design a 3-bit up counter, that counts from 0 to 7 at each clock pulse and wraps around to 0 after it reaches 7. Do the design using 2 D FF and one T FF. Slide 80
T
Q Q
Q2
Q T Q
Q3
Synchronous Serial Counter

CNTEN CLK
EN T
Q0
EN
Q1
Slide 81
It is slow because of CLK propagation from the least signicant output (Q0) to the most signicant output (Q3).
Slide 83
EN T Q
Q2
EN T
Q3
All FFs share the same clock and they hence change state at the same time. But this requires using TTs with Enable. The output
Synchronous Counters Slide 82 Two examples of synchronous (unlike series ripple counter) counter are shown in Figures 8-25 and 8-26 below. Slide 84
toggles when the master enable CNTEN is asserted. Since the master enable still needs to propagate through FFs, it remains slow and it is called synchronous serial counter.
Synchronous Parallel Counter

CNTEN CLK
EN T Q
Q0
EN T
Q1
Slide 85
EN T
Q2
Slide 87
It is a 4-bit up counter, with clear (CLR) and load (LD) inputs, two enable inputs (ENP,ENT), and ripper carry-output (RCO).
EN T
Q3
All FF share the same CLK and Enable. There are no delay. It is the fastest binary counter.
MSI Counter Chip The most popular MSI counter is 74 x 163.

74x163
2 1 9 7
MSI Counter Chip (contd)

Ta bl e 8 - 1 1 State table for a 74x163 4-bit binary counter.
Inputs CLR_L LD_L ENT ENP Current State QD QC QB QA QD Next State QC QB QA
CLK CLR LD ENP ENT QA

14 13
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x x 0 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x x x 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x x x x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
x x x x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
x x x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
D QD QD
0
C QC QC
0
B QB QB
0
A QA QA
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Slide 86
10 3 4
Slide 88
QB 12 QC QD RCO
11 15
A B 5 C
6
MSI Counter Chip (contd) Slide 89 The output is 0 if CLR is asserted. The output is A,B,C,D if LD is asserted. If either ENP os ENT is asserted, the output stays the same as the last state. RCO is asserted if all four outputs are 1. Slide 91 values A,B,C,and D (they are 1100) are loaded into the output.
Module-11 Counter 74x163 can be used to build dierent counters (see Fig. 8-29). The following is an module-11 decimal counter (i.e., count up to 11 and wrap around) built with 74x163
74x163 CLOCK
1 2
CLK
More State Machine Design Example Slide 92

QA 13 QB 12 QC 11 QD RCO U1
15 1 2 14
Slide 90
+5 V R RPU
CLR 9 LD 7 ENP 10 ENT

3 4
A B 5 C 6 D
Q0 Q1 Q2 Q3 74x00
3
Design a state machine with two inputs X and Y, and output Z. The output is 1 if the number of 1 inputs on X and Y since reset is a multiple of 4. See section 7.4.6 for details.
S11XX_L
U2
When Q2=Q3=1, through the NAND gate, LD is asserted, the
State Design: Another Example Design a controller for T-bird tail lights.
Slide 93
CALIFORNIA
Slide 95
on when the Left (Right) input is on and six lights all ash when the HAZ is on. Assume the clock frequency matches the light ash rate.
ZOTTFFS
LC
LB
LA
RA
RB
RC
Problem statement: three lights on each side, and for turn, they operate in sequence to show the turning direction
(a)
LC
LB
LA
(b)
RA
RB
RC
T-bird tail light design Input: left, right, haze
Slide 94
Slide 96
output: six lights: 3 for left (LA, LB, LC) and 3 for right (RA, RB, RC) States: IDLE, L1, L2, L3, R1, R2, R3, LR3 see progressive improvement in state diagrams from Fig. 7.56, 7.57, and 7.58.
It has three inputs: Left, Right, and Haz. The left (right) lights are
L2 HAZ HAZ
HAZ
S
IDLE IDLE
Q2
Q1
Q0
Transition Expression
(LEFT + RIGHT + HAZ) LEFT HAZ RIGHT HAZ + LEFT RIGHT RIGHT HAZ LEFT HAZ HAZ HAZ HAZ
S
IDLE L1 LR3 R1 L2 LR3 L3 LR3 IDLE R2 LR3 R3 LR3 IDLE IDLE
Q2
Q1
Q0
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 0 0 0 1 1 1 0 0 1 1 1 0
0 0 0 0 1 1 1 1 0 1 1 1 1 0 0
0 0 1 1 0 1 0 1 0 1 1 1 1 0 0
0 0 0 0 1 0 1 0 0 1 0 1 0 0 0
0 1 0 1 1 0 0 0 0 1 0 0 0 0 0
Table 7-17 Transition list for T-bird tail-lights state machine.
L3 LEFT HAZ RIGHT 1 (LEFT + RIGHT + HAZ)
L1
IDLE IDLE
HAZ
L1
1 IDLE HAZ + LEFT RIGHT LR3
L1 L2
Slide 97
1 R3
Slide 99
L2 L3 R1 R1
1
HAZ HAZ HAZ HAZ
HAZ RIGHT HAZ LEFT R1
R2 R2 R3
1 1
HAZ
HAZ
HAZ
LR3
R2
Transition List From the constructed state diagram, we can build a transition list table as shown in Table 7-14. Transition equations can be directly derived from the transition list. The transition equation for a next state is the sum of transition expression for which the next state variable has a value of 1. Transition equation can then be simplied algebraically or using K-map. Excitation equations can be derived from transition equations.
Slide 98
1D
(4) D CLK CLR Q Q
(2) (3)
1Q 1Q_L (a)
2D
(5) D CLK CLR Q Q
(7) (6)
2Q 2Q_L 74x175 (b)

9 1
CLK CLR 1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q
2 3 7 6 10 11 15 14
Chapter 8 Sequential Logic Design Practices Slide 1 Registers (section 8.2.5) Shift Registers (section 8.5.1-8.5.2) Counters (section 8.4) Slide 3
3D
(12) D CLK CLR Q Q
(10) (11)
3Q 3Q_L
4
1D 2D 3D 4D
12
4D CLK CLR_L
(13) D (9) CLK CLR (1) Q Q
(15) (14)
4Q 4Q_L
13
The data inputs (1D-4D) are transferred to the D FFs (transferring to Q1-Q4) at each clock tick. It includes a synchronous clear input, which clears the FFs (i.e., set the Qs to zero) if asserted. 74x374 is a 8-bit register. See Figure 8-10.
Shift Registers Registers Slide 2 A register is a storage device, consisting of a collection of D FFs with a common clock input. Each D FF can store 1 bit of data. 74x175 is a 4-bit register. Slide 4 A shift register shifts its stored data by one bit position at each clock tick. There are four types of shift registers: serial-in, serial out; serial-in, parallel-out; parallel-in, serial-out, and and parallel-in, parallel-out. Go to Wikipedia at http://en.wikipedia.org/wiki/Shift register for a demo of each register.
Serial-in Serial-Out Shift Registers Slide 5 The input data SERIN is applied sequentially to the D input of the rst FF. During each clock pulse, one bit is transmitted from current FF to next FF. The output is read one bit at a time from the last FF. Slide 7
Serial-in Parallel-Out Shift Registers The input data SERIN is applied sequentially to the D input of the rst FF. During each clock pulse, one bit is transmitted from current FF to next FF. The output is read simultaneously from all FFs.
SERIN
SERIN CLOCK
D CK Q
D CK
1Q
CLOCK
D
D CK Q
Q CK
2Q
Slide 6
Slide 8
D CK
SEROUT
D CK
NQ
Parallel-in Serial-Out Shift Registers At each clock tick, depending on the control input LOAD/SHIFT, it could load new data (1D-ND) to the FFs or shift the existing content of the FFs right one bit at a time. The output is read one bit at a time from the last FF.
CLOCK LOAD/SHIFT SERIN
D Q CK
CLOCK LOAD/SHIFT SERIN

D Q CK
1Q
1D
Q CK
2Q
2D
Slide 9
1D
Slide 11
D Q CK
NQ
Q CK
2D
ND
Q CK
SEROUT
ND
This is the most general shift register and can replace other types of registers.
MSI Shift Registers 74x164 8-bit serial-in, parallel-out shift register, consisting two serial inputs (SERA and SERB). Internally, they are ANDed. Both must be 1 for 1 to be shifted into the register. it also includes an synchronous clear input. 74x166 8-bit parallel-in, serial-out shift register. The device shifts when SH/LD is 1. Otherwise, it loads new data from its input (A-H) into the register. it also includes an synchronous clear input. 74x194 parallel-in, parallel-out shift register, its output depend on the two control inputs S1 and S0. Note these MSI parts are seldom used nowadays, because any desired, customized shift-register function can be provided in a PLD or FPGA.
Parallel-in Parallel-Out Shift Registers At each clock tick, depending on the control input LOAD/SHIFT, it could loads new data (1D-ND) to the FFs or shift the existing content of the FFs right one bit at a time. The output is read simultaneously from all FFs. Parallel-in Parallel-Out Shift registers are called universal shift registers.
Slide 10
Slide 12
Slide 13
Slide 14
Table 8-18 Function table for the 74x194 4-bit universal shift register.
Inputs Function S1 S0 QA
Next state QB QC QD
Hold Shift right Shift left Load
0 0 1 1
0 1 0 1
QA RIN QB A
QB QA QC B
QC QB QD C
QD QC LIN D
2 b ROM A0 A1 A2 address inputs D0 D1 data outputs An2 An1 Db1
Chapter 9 Memory Slide 1 Read-Only Memory (section 9.1-9.1.1) Static RAM (section 9.3-9.3.2, 9.3.4) Slide 3
The data is hard-wired in the ROM. ROM memory is usually non-volatile, i.e., its content does not disappear when power is o.
Inputs A2 A1 A0 D3
Outputs D2 D1 D0
Read Only Memory (ROM) Slide 2 A ROM is a combinational circuit with n address inputs and b data outputs. It stores a truth table of the size 2n x b, where n is the number of input and b is the number of output. Slide 4
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 1 1 0 0 0 0 1
1 1 0 1 0 0 1 0
1 0 1 1 0 1 0 0
0 1 1 1 1 0 0 0
Ta bl e 1 0 - 1 Truth table for a 3-input, 4-output combinational logic function.
Static Random Access Memory (RAM) Slide 5 A static RAM is a sequential circuit with n address inputs and b data outputs. A RAM also has b data inputs and a set of control inputs. One of the control input is Write-Enable (WE). When WE is asserted, the data inputs are written into the memory. Slide 7
READthe data stored in the location specied by address input are transfered to the output. For this to happen, the eanbles CS and OE (output enable) need be asserted. WRITE-the data in the data input (DIN0-DINb-1) are written to the memory location specied by the address inputs. For this to happen, CS and WE need be enabled.
2n b RAM A0 address inputs A1
Standard Static RAMs HM6284 (8k x 8) HM628128 (128k x 8)
An1 DIN0 data inputs DIN1
HM628512 (512k x 8)
DOUT0 DOUT1 data outputs
Slide 6
Slide 8
control inputs
DINb1 CS OE WE
DOUTb1
A static RAM usually performs two operations.
Advanced Topics
Register
Basic Building Blocks (1)
Buses
A shared collection of wires for exchanging data, with some defined rules
Data Lines (two-way) N M Address Lines (one-way)
3 Registers Sharing a Bus
Fundamentals in Computer
Data In (N bits) N N Register Load Output Enable (we have Tri-state outputs) Data Out (N bits)
Organization Introduction to VHDL
Control Lines (mix of 1 and 2-way lines)
Only one of these OEs can be true at once Rule 1: Only one device can write to a bus at any time Rule 2: Multiple devices can read the bus at any time Rule 3: There is usually a bus protocol that is followed strictly by all devices sharing the bus
OE1
OE2
OE3
Only one can
Register 1
Register 2
Register 3
OEs and LOADs generally determined by the control lines
write to the data LOAD1 line
LOAD2
LOAD3
To write, OE must be enabled. To read, 5
LOAD must be enabled.
Several of these can be true at once for input

Shift Register

Arithmetic-Logic Unit N N A B
Register-to-Register Data Transfer

Register 1 Register 3
N M C
Buses & Registers to RAM
Memory Address Register (store address here)
M A R
Data In N Shift Register Output Enable N Load
Data Out
Memory Control Signals
Request (Chip Select)
Read/Write Wait
Random Access Memory
Operation
ALU N
Keep in mind: The ALU is a combinational circuit. Flags Result (carry out, overflow, etc.)
OE1
OE2
OE3
Register 1
Register 2
Register 3
Slow RAMs usually ask Processor to wait LOAD1 LOAD2 LOAD3 Only one can write to the data line, but more than one 3 4 registers can receive inputs at the same time 7
M B R
Shift Controls (left/right/no shift)
Memory Buffer Register (exchange data here)
I want to build a computer!

Basic Idea #1: The Stored Program Computer Concept
This is an instruction-controlled digital system with a memory A sequence of instructions are stored in memory This set of instructions constitute the program that defines the machines behavior The same memory also holds the data needed to execute the program The same memory also holds the outputs produced by the program, as well as any intermediate results Step 3. Fetch any operands needed Step 4. Execute the instruction Step 5. Do internal housekeeping, and Go to Step 1 One important chore is to change the address in the PC to point to the next instruction.
10
The Cycle of Life

Basic Idea #2: The Instruction Cycle
The processor executes the following infinite loop forever: Step 1. Fetch the next instruction from memory to a register The register is usually called the instruction register (IR). The address of the next instruction is usually stored in a register called the program counter (PC). So, Fetch does the following: 1) get the instruction address from PC; 2) read the instruction from the memory; 3) transfer the instruction to IR. Step 2. Decode the instruction
Register Transfer Operations

Single Bus Design
BUS
Memory Address Bus Memory Data Bus
More Realistic Datapath Unit

M A R A P C I R A C M B R B
Three Bus Design Supports more parallelism
Address Bus
Result Bus
Memory Address Bus
M A R
P C
I R
A C
Register transfer operations: PC BUS IR BUS AC BUS MBR BUS ALU Result BUS BUS PC BUS IR BUS AC BUS MBR BUS ALU B BUS MAR They all share one bus. AC ALU A (hardwired)
M B R
Memory Data Bus
Memory Bus
The memory is large (ideally, infinite)
Note: This is not the only way to build a computer, but is the most common one.
9
Single bus replaced by three busses: Note, the BUS is treated just like a register 13
Memory Bus (MBUS) Result Bus (RBUS) Address Bus (ABUS)
14
Structure of a Computer
Address
Put Them Together!

Single Bus Design The Datapath Unit
Memory Address Bus
Add Memory
RBUS
Add Control
BUS
AC
Memory Data Bus
Central Processing Unit (CPU)

Processor
Data Read/Write
Memory System
The Processor consists of two major parts:

Control Signals
Control
Data Inputs
Datapath
In its simplest form, a computer consists of a processor (CPU) and a memory system.
RBUS MBUS
The control unit is a finite state machine (FSM).

M A R A P C I R A C M B R B
A B
Memory Address
MBUS
AC
ALU
Memory N bits wide 2M words
ALU
S
MAR ABUS IR PC
The Datapath Unit, also called the execution unit, consisting of Registers for temporary data storage and functional unit to perform operation on the data. Main parts: Registers, Shifter, ALU, Buses. The Control Unit, also called the instruction unit. It provides instruction as to what operation to perform Main parts: Finite-State Machine update PC (since inputs
11
The BUS is like a highway for transferring data from one point to any other point Program Counter (Holds address of NEXT instruction)
MBUS
Every bit of the Instruction Register (IR), every other registers OE and LOAD signals, every control input and flag output of the ALU, and every memory control signal is either an input or an output of the control unit. (Shown in red) Accumulator Involved in most instructions Instruction Register (Holds the fetched instruction) Note that this one has two outputs 12
FSM
ALU
Memory Address
MAR
Opcode
ABUS
IR
PC
MBUS
We simplified our datapath further by assuming that MBR is inside the memory system itself and MBUS has two branches. Every device in this diagram has control signals that must be operated. 15
3 for ALU, 1 each for, MAR, and PC.
Control Flow Data Flow
Reality Note #1:The control unit FSM is huge compared to the FSM examples that weve seen thus far!!
Reality Note #2: The diagram above is extremely simplified compared to a real processor
16
How does it work? (1)

Let's trace an instruction: AC AC + Mem<address>
AC A FSM MAR
Opcode
How does it work? (2)

Let us trace an instruction: AC AC + Mem<address>
AC A FSM MAR PC Instruction Path S IR ALU
Memory Address
Micro-Operations
Instruction Fetch
Instruction fetch: PC ABUS; ABUS MAR; 1 Read/Write*; MBR MBUS; MBUS IR; Instruction Decode: IF IR<OpCode> = LOAD_FROM_MEMORY THEN Operand fetch: IR-> ABUS ABUS->MAR 1 Read/Write*; Instruction Execution: MBR MBUS; MBUS ALU B; ALU PASS B; ALU Result RBUS; RBUS AC; 18 Housekeeping: PC+1 PC; 21
Micro-operations
Store Path Load Path B ALU S PC Instruction Path

Memory Address
Store Path Load Path B Memory N bits wide 2M words
One register transfer operation may be several micro-operations
1. Instruction Fetch: Move PC to MAR Initiate a memory read sequence Move data from memory to IR
Opcode
IR
2. Instruction Decode: Opcode bits of IR are input to control FSM Rest of IR bits encode the operand address (see Fig 11.4) OPCODE 3. Operand Fetch: Move operand address from IR to MAR Initiate a memory read sequence Instruction Format Instruction Format 17 OPERAND SPECIFIER OPCODE 5. Housekeeping: Update PC to point at next instruction OPERAND SPECIFIER
4. Instruction Execute: Data available on load path Move data to ALU input Configure ALU to perform ADD operation Move result S to AC
Some operations are directly implemented by functional units:
e.g., ADD, Pass B, 0 PC, PC + 1 PC
Some others require multiple control operations:
e.g., PC MAR implemented as PC ABUS and ABUS MAR
See page 588
22
The Control Unit

What the Control unit is doing: Transfers data from one register to another Asserts appropriate control signals We can think about the control unit most easily in terms of a series of register transfers and microoperations, using a programming-like notation Register transfer notation - A way to represent the detailed implementation of register transfer operations Micro-operations-detailed operations for each register transfer Notation.
19
Register Transfer Notation

Register to Register moves Instruction fetch: PC MAR; Memory Read; Memory IR; -- move PC to MAR -- assert Memory READ signal -- load IR from Memory
Example Task
Read the output of the 4-bit data source every time the push button is pressed, and display the result.
Instruction Decode: IF IR<op code> = ADD_FROM_MEMORY THEN Operand fetch: IR<addr> MAR; Memory Read; Instruction Execution: Memory ALU B; AC ALU A; ALU ADD; ALU S AC; Assert Control Signal Housekeeping: PC+1 PC; Repeat the five steps ! -- move operand addr to MAR -- assert Memory READ signal -- gate Memory to ALU B -- gate AC to ALU A -- instruct ALU to perform ADD -- gate ALU result to AC -- increment PC
Interrupts, Resets
4-bit Data Source
Computer (HC11 chip)
Display
Push Button
20
23
24
One Method...
4-bit Data Source Computer (HC11 chip) Display
Is Polling Bad?
Eats up a lot of CPU cycles doing nothing! Were repeatedly checking the button Each time the button is pressed, we delay by 1 ms by going around in a loop, wasting time This is also called busy wait We could do better if only we could somehow grab the CPUs attention momentarily whenever the button is pressed! We could do even better if the 1 ms delay could be achieved without a delay loop!
25 26
Interrupt Method
Suppose that the computer is doing something... useful or otherwise....
START
Interrupt Method
START
The CPU is temporarily interrupted. An Interrupt Service Routine is entered
Push Button
BUTTON PRESSED? YES 1 ms delay
NO
START
START INTERRUPT SERVICE ROUTINE INITIALIZE
INITIALIZE
Key Pressed
Why do we have this?

Software switch debouncing
READ THE 4-BIT INPUT UPDATE THE DISPLAY DO SOMETHING USEFUL Key Pressed
4-bit Data Source
This style of computer input/output is called Polled I/O because were constantly polling the pushbutton
BUTTON PRESSED? YES READ 4-BIT INPUT UPDATE DISPLAY NO
Computer (HC11 chip)
Display
DO SOMETHING USEFUL
Push Button
RETURN FROM INTERRUPT
The CPU now resumes where it left off!

29
30
Introducing Interrupts
A mechanism to interrupt the CPU, i.e., steal it for a little while to service the interrupting device (a button in our example)
An interrupt is an unusual event that requires the CPU to stop normal program and perform some service related to the unusual event. It can be external or internal. External interrupts can be generated by asserting an interrupt signal to CPU. Internal interrupts can be hardware components in CPU such as timer, I/O interface function. Interrupts can also be caused by software errors (overflow, abnormal operations, ..) 27
Why are Interrupts Important?

They allow multiple processes to run on a computer They allow the CPU to be shared, especiall when I/O is busy, greatly extending its ability Provide a graceful to exit an application when software errors occur. Reminding CPU to perform routine tasks For example, the CPU can be doing something else when waiting for the button to be pressed
Interrupts are Transparent

The program that was interrupted does not have a clue that it was interrupted!! Interrupt Service Routines need to leave registers untouched Interrupt Service Routines need to be extremely short and quick
Interrupt Sources
Interrupts can come from several sources
Hardware Sources External Pushbuttons Internal Timers I/O interface Serial Communication Systems ...
Software Sources SWI instruction-halt a program STOP-cause the system to halt
28
31
32
Interrupt priority: - The order in which the CPU will service interrupts when all of them occur (pending) at the same time.
Interrupt Maskability: - Interrupts that can be ignored by the CPU are called maskable interrupts. A maskable interrupt must be enabled before it can interrupt the CPU. Masking can change priority. An interrupt is enabled by setting an enable flag. Interrupts that cant be ignored by the CPU are called non-maskable interrupts.
Managing Interrupts
Different Sources can have different priorities
The 68HC11 timer produces an interrupt once every 216 CPU cycles.
At 9600 bits/sec, the RS-232 port on your PC produces an interrupt about once every 2000 CPU cycles.
For example, sources requiring a more timely response get higher priority.
The timer has higher priority in this case.
Chapter 5.3 VHDL

VHDL-Very high speed Hardware Description Language Using VHDL, you can design, simulate, and synthesize a digital circuit. The VHDL design ow includes: block diagram, coding, compilation, simulation, and synthesis. Synthesis is concerned with loading the compiled codes into the chip such as a PLA and verifying the performance of the design in an actual circuit in term of functional and timing performance. Through a synthesis tool, the schematic diagram of a circuit can be produced from the VHDL code. See http://esd.cs.ucr.edu/labs/tutorial/ for example VHDL code and the corresponding schematic diagrams produced by the synthesis tool.
Why do we need to use masking and priority to manage interrupts ?

35
Interrupt Priority
VHDL was designed with structured programming in mind Borrowed concepts from Pascal and ADA Slide 3 Actually VHDL is almost object-oriented Has separate interface and implementation parts! But, doesnt have classes with which to instantiate new objects with. Needs an update!
33
Functions of Interrupts: - Coordinating I/O activities and preventing CPU from being tied up - Providing a graceful way to exit from errors - Reminding the CPU to perform routine tasks
34
VHDL Program Structure
A special event that requires the CPU to stop normal program execution and perform some service related to the event. E.g.: I/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0 etc.
What is an interrupt?
Interrupts: Recap
Slide 1
VHDL: Features
Designs can be decomposed hierarchically Each design element has: A well-dened interface for connecting with other elements Slide 2 Precise functional description (for simulation) Functional description may be Behavioral algorithm (direct functional description) Hardware structural description (such as in term of gates and their interconnections) Slide 4
VHDL Program Structure (contd)

It consists of two parts: entity declaration and architecture denition. Entity denes a modules name, its input and output. It is an interface (or a wrapper) to outside modules. Architecture denition describes the modules function or methods (implementations). Each interface may have multiple methods.
VHDL Program Structure: Entity

The syntax for a VHDL entity consists of key words, entity name, input and output variable names, types, modes.
entity declaration
Table 4-27 Syntax of a VHDL entity declaration.
entity entity-name is port s ( ignal-names : mode signal-type; signal-names : mode signal-type; ... signal-names : mode signal-type); end entity-name;
Slide 5
architecture definition
Slide 7
Keywords-entity, is, port, begin, end, etc.. Note they are case insensitive. Entity name and signal name-a string of characters (containing no spaces and hyphens). The key words cannot be used as variable names.
type-for VHDL predened types

Ta bl e 4 - 2 6 entity Inhibit is -- also known as 'BUT-NOT' port (X,Y: in BIT; -- as in 'X but notVHDL Y' program for Z: out BIT); -- (see [Klir, 1972]) an inhibit gate. end Inhibit;
architecture Inhibit_arch of Inhibit is begin Z <= '1' when X='1' and Y='0' else '0'; end Inhibit_arch;
bit bit_vector boolean
character integer real
Table 4-29 severity_level VHDL predefined string time types.
Slide 6
Slide 8
The name of all VHDL programs should end with an extension .vhd such as mydesign.vhd .
Often, we use std logic and std logic vector for bit and bit vector if the IEEE standard library (IEEE.std logic 1164.all) is used
mode-in, out, buer, inout,
VHDL Program Structure: Architecture

The VHDL architecture template
Entity Denition Example:XOR Gate

ENTITY xor gate IS Slide 9 PORT (a,b: IN STD LOGIC; f: OUT STD LOGIC); END xor gate; Slide 11
architecture architecture-name of entity-name is type declarations signal declarations constant declarations function definitions procedure definitions component declarations begin concurrent-statement ... concurrent-statement end architecture-name;
Ta bl e 4 - 2 8 Syntax of a VHDL architecture definition.
A Simple VHDL Program
Entity Denition Example: buzzer
Slide 10
Slide 12
Note:
1)use two hyphens to indicate the start of comments. Slide 13 2)reserved words such as entity, port, is, in, out, bit are not case sensitive. Slide 15 2)<= can also be used as the assignment operator.
VHDL operators
Table 4-30 Predefined operators for VHDL's integer and boolean types.
Operators integer Operators boolean
+ * / mod rem abs **
Slide 14
addition subtraction multiplication division modulo division modulo remainder absolute value exponentiation
and or nand nor xor xnor not
AND OR NAND NOR Exclusive OR Exclusive NOR
VHDL WHEN statement

Syntax Slide 16 statement WHEN boolean-expression ELSE statement; An example z <= 0 WHEN x / = 1 else z <= 1;
complementation
In addition, there are also relational operators: =, / =, <, <=, >, and >=. Note: 1) results of Boolean and Relational operations are all Boolean data type.
VHDL IF statement
if boolean-expression then sequential-statement end if; if boolean-expression then sequential-statement else sequential-statement end if;
WITH Statement
Table 4-57 Syntax of a VHDL if statement.
Table 4-52 Syntax of VHDL selected signalassignment statement.
with expression select signal-name <= signal-value when choices, signal-value when choices, ... signal-value when choices;
Slide 17
if boolean-expression then sequential-statement elsif boolean-expression then sequential-statement ... elsif boolean-expression then sequential-statement end if; if boolean-expression then sequential-statement elsif boolean-expression then sequential-statement ... elsif boolean-expression then sequential-statement else sequential-statement end if;
Slide 19
An example
Table 4-53 Prime-number detector architecture using selected signal assignment.
architecture prime4_arch of prime is begin with N select F <= '1' when "0001", '1' when "0010", '1' when "0011" | "0101" | "0111", '1' when "1011" | "1101", '0' when others; end prime4_arch;
CASE Statement
Syntax: CASE expression IS An example
Table 4-58 architecture prime7_arch of prime is Prime-numberbegin detector architecture process(N) using an if statement. variable NI: INTEGER; begin NI := CONV_INTEGER(N); if NI=1 or NI=2 then F <= '1'; elsif NI=3 or NI=5 or NI=7 or NI=11 or NI=13 then F <= '1'; else F <= '0'; end if; end process; end prime7_arch;
WHEN choices => statements; WHEN choices => statements; WHEN OTHERS => statements; Slide 20 END CASE; Example: CASE state IS WHEN S1 => Z <= 1; WHEN S2 => Z <= 2; WHEN OTHERS => Z <= 0; END CASE;
Slide 18
VHDL Loop
for identifier in range loop sequential-statement ... sequential-statement end loop;
Table 4-62 Syntax of a VHDL for loop.
VHDL representation of bit vectors

X: bit vector (2 downto 0); Slide 23 means X is an array of 3 bits. its element is indexed from 2 to 0, with X[2] for the MSB and X[0] for the LSB. X: bit vector (0 to 2); means X is an array of 3 bits. its element is indexed from 0 to 2, with X[0] for the MSB and X[2] for the LSB.
Slide 21
An example
VHDL Implementation of Decoders

T a b l e 5 - 1 5 Dataflow-style VHDL program for a 74x138-like 3-to-8 binary decoder.
library IEEE; use IEEE.std_logic_1164.all; entity V74x138 is port (G1, G2A_L, G2B_L: in STD_LOGIC; A: in STD_LOGIC_VECTOR (2 downto 0); Y_L: out STD_LOGIC_VECTOR (0 to 7) ); end V74x138;
-- enable inputs -- select inputs -- decoded outputs
Slide 22
Note: always include ieee.std logic 1164.all in the beginning of a VHDL program.
Slide 24
architecture V74x138_a of V74x138 is signal Y_L_i: STD_LOGIC_VECTOR (0 to 7); begin with A select Y_L_i <= "01111111" when "000", "10111111" when "001", "11011111" when "010", "11101111" when "011", "11110111" when "100", "11111011" when "101", "11111101" when "110", "11111110" when "111", "11111111" when others; Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else "11111111"; end V74x138_a;
Multiplexers in VHDL
Ta bl e 5 - 4 2 Dataflow VHDL program for a 4-input, 8-bit multiplexer.
library IEEE; use IEEE.std_logic_1164.all; entity mux4in8b is port ( S: in STD_LOGIC_VECTOR (1 downto 0); -- Select inputs, 0-3 ==> A-D A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Data bus input Y: out STD_LOGIC_VECTOR (1 to 8) -- Data bus output Slide ); end mux4in8b; architecture mux4in8b of mux4in8b is begin with S select Y <= A when "00", B when "01", C when "10", D when "11", (others => 'U') when others; -- this creates an 8-bit vector of 'U' end mux4in8b;
SUBTYPE Statement
Syntax: SUBTYPE subtype-name IS type-name (start to end); CONSTANT constant-name: subtype-name : = value Example: SUBTYPE state IS STD LOGIC VECTOR (1 to 3); 27 CONSTANT S0: state :=000; CONSTANT S1: state :=001; CONSTANT S2: state :=011; CONSTANT S3: state :=010; CONSTANT S4: state :=110; These statements can be used to relate the statess mnemonic names to their binary assignment.
Slide 25
VHDL Functions
Like functions for high level programming language (e.g. C++), a VHDL function has its input arguments and returns a result of certain type. Syntax for VHDL functions
architecture Inhibit_archf of Inhibit is
Ta bl e 5 - 4 3 Behavioral architecture for a 4-input, 8-bit multiplexer.

architecture mux4in8p of mux4in8b is begin process(S, A, B, C, D) begin case S is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when "11" => Y <= D; when others => Y <= (others => 'U'); end case; end process; end mux4in8p;
Slide 26
Slide 28
-- 8-bit vector of 'U'
function ButNot (A, B: bit) return bit is begin if B = '0' then return A; else return '0'; end if; end ButNot; begin Z <= ButNot(X,Y); end Inhibit_archf;
Ta bl e 4 - 3 6 VHDL program for an inhibit function.
PROCESS Statement
Syntax: process is a collection of statements dened in an enclosing architecture. A process statement is introduced by the keyword process. Statements in a process are executed sequentially instead of concurrently. Multiple processes can be dened in an architecture and they are processed simultaneously. PROCESS (signal-name, signal-name, signal-name) Slide 29 type declarations; variable declarations; constant declarations; BEGIN statements; statements; ... END PROCESS; Slide 31
Dierences Between Process and Function

Function has a name, while Process does not have Function can call each other, while Process cannot Processes are executed simultaneously, while Function is executed when it is called.
PROCESS Example VHDL for State Machine

Table 4-63 library IEEE; Prime-numberuse IEEE.std_logic_1164.all; detector architecture using a forstatement. entity prime9 is port ( N: in STD_LOGIC_VECTOR (15 downto 0); F: out STD_LOGIC ); end prime9;
architecture prime9_arch of prime9 is begin process(N) variable NI: INTEGER; variable prime: boolean; begin NI := CONV_INTEGER(N); prime := true; if NI=1 or NI=2 then null; -- take care of boundary cases else for i in 2 to 253 loop if NI mod i = 0 then prime := false; exit; end if; end loop; end if; if prime then F <= '1'; else F <= '0'; end if; end process; end prime9_arch;
Table 7-36 Dataflow VHDL for an S-R latch.
library IEEE; use IEEE.std_logic_1164.all; entity Vsrlatch is port (S, R: in STD_LOGIC; Q, QN: buffer STD_LOGIC ); end Vsrlatch; architecture Vsrlatch_arch of Vsrlatch is begin QN <= S nor Q; Q <= R nor QN; end Vsrlatch_arch;
Slide 30
Slide 32
VHDL for State Machine

library IEEE; use IEEE.std_logic_1164.all; entity VposDff is port (CLK, CLR, D: in STD_LOGIC; Q, QN: out STD_LOGIC ); end VposDff;
Table 7-37 Behavioral VHDL for a positive-edgetriggered D flip-flop.
END CASE; END IF; Slide 35 END PROCESS; END vending arch;
Slide 33
architecture VposDff_arch of VposDff is begin process (CLK, CLR) begin if CLR=?1? then Q <= ?0?; QN <= ?1?; elsif CLK?event and CLK=?1? then Q <= D; QN <= not D; end if; end process; end VposDff_arch;
VHDL for State Machine (contd)

ENTITY vending machine IS port (CLOCK,A,B: in std logic; Z: OUT std logic); END; ARCHITECTURE vending arch OF vending machine IS Slide 34 PROCESS (CLOCK) BEGIN IF CLOCK event and CLOCK=1 then CASE state IS WHEN S1 => Z<=1; WHEN S2 => Z <=2; WHEN OTHERS => Z <= 0; Slide 36
VHDL for State Machine

Design a clocked synchronous state machine with Two inputs, A and B, and a single output Z that is 1 if: A had the same value at each of the two previous clock ticks, or B has been 1 since the last time that the rst condition was true. Otherwise, Z is 0 1) derive the transition/output table 2) implement the table in VHDL (see section 7.12)
Slide 37
more VHDL examples may be found at http://esd.cs.ucr.edu/labs/tutorial/ or from the le http://www.ecse.rpi.edu/homepages/qji/VHDLSampleCodes.doc
VHDL v.s. Verlog

Verilog is easier to understand and use, has long been the language of choice for industrial applications. But it lacks constructs needed for system level specications. VHDL is more complex, thus dicult to learn and use. However it oers a lot more exibility of the coding styles and is suitable for handling very complex designs.
Slide 38
ECSE 2610 Final Exam, Spring, 2008 Duration 11:30 am - 2:30 pm

Student Name Section Number Student ID Number Email Address
Exam Rules:
This is a 3 hours exam. It includes all materials covered during this semester. This is an Open Book and Notes exam. You are not allowed to consult with other students. You may not use a calculator, laptop, palmtop, PDA, or such computer. If you need more space, continue on the back sides of pages, but make sure to indicate the continuation.
1. Mark each of the following statement TRUE or FALSE 10 points, 1 point each a The largest number a BCD can represent is 9. b Over ow applies only to arithmetic operations on signed numbers. c The canonical sum and canonical product representation of a digital circuit are logically the same. d The state of a Moore machine will change only at the rising edge of the clock signal. e The number of outputs a gate can have is arbitrary. f For a NOR gate in positive logic, it would become a NAND gate if the negative logic were applied instead. g The 7-bit binary representation for 8 as a unsigned number, signed number, or a ASCII character are all the same. h The data bus is bidirectional. i The control unit in a computer controls the operations of every register, the ALU, and the memory. j MBR and MAR use di erent types of bus.
1 2 3 4 5 6 7 8 9 10 Total 10 points 10 points 10 points 10 points 10 points 10 points 10 points 10 points 10 points 10 points
2. Complete the following table by lling in all the blanks 10 points use 6-bit binary representations if there are multiple answers for a particular blank, then give all of them if there are no answers for a blank, then mark it with X" in that space
4. Do the following Draw the gate-level implementation of a 2:1 multiplexer. Clearly label all control, input, and output signals 5 points
Show how you can construct a 4:1 mux using 2:1 multiplexers only. Clearly label all control, input, and output signals. Clearly show all the connections between multiplexers. Using the 2:1 mux logic symbol below 5 points. 3. Perform the following calculation using 2's complement and indicate if an over ow occurs. First convert the decimal number to 6-bit long 2's complement numbers and then do the addition. Show the result of the conversion and addition. z = -20 + -13 10 pts
5. Give the state diagram for the logic diagram below, where FA=full adder. Identify the inputs, outputs, and states explicitly 10 points.
6. A combinational logic circuit accepts a 4-bit unsigned number A3A2A1A0 and generates a binary output Pn Pn 1 P2P1P0 equal to the eight times the input. Find the simpli ed sum of products for P3 and P2 only 10 points
7. An AB-type" ip- op has two inputs A and B. If A=1, then Q*=B if A=0, then Q*=B' 10 points . Using a D ip- op, design an AB ip- op. Show how you derived the schematic and draw the schematic.
8. Given the following timing chart for a negatively edge-triggered sequential network, where X1 and X2 are inputs, Q1 and Q2 are state variables, and Z1 and Z2 represent two outputs. Is this a Moore or Mealy or Moore machine and why ? Construct as much of the state diagram as possible 10 points.
Using an AB ip- op, design a T ip- op. Explain how you derived the schematic.
9. Design a sequence detector with one input X and one output Z. Every time the input sequence "101" is detected the output Z=1. However, the output detector needs to be rst activated with a key, i.e. it has to receive at least three consecutive 0's before it will start detecting the desired sequence "101". Once the key has been received, the sequence detector keeps looking for the desired sequence. Identify the possible states and give the state diagram 10 points .
10. Do the following 10 points Complete the state diagram below for a Mealy machine that implements a full adder. The state machine has two inputs X and Y, representing the two addends respectively, an output S representing the sum, and a state variable C representing the carry 5 points
Based on the above state diagram, complete the following VHDL implementation of the full adder Mealy machine by replacing the questions marks with the correct entries 5 points.
10
ECSE 2610 Mid-Term Exam, Fall, 2013 Duration 10 - 11:50 am

Student Name Section Number Student ID Number Email Address
1. Do the following Complete the following table by lling in all of the blanks [5 points] Use 6-bit binary representation If there is no answer for a particular blank, then write an x in the space.
decimal
unsigned binary
signed magnitude 101101
signed 2s complement
Exam Rules:
This is an Open Book and Notes exam. You are not allowed to consult with other students. You may not use a calculator, laptop, palmtop, PDA, or such computer. If you need more space, continue on the back sides of pages, but make sure to indicate the continuation.
Perform the following [10 points] (a) Given A=10101 B=11001 A and B are positive numbers. Represent A and B in 8-bit 2s complement. Let C=-B, perform the operations A+B, and A+C, where all the numbers are in 2s complement representation. Give your answers in decimal. Does overow occur in each case ?
1 2 3 4 5 Total 15 points 15 points 10 points 15 points 15 points
2. Given the logic expression below, do the following (15 points). F= (ab+ (a + (bc))) + (a + (b +ac)) Use Boolean theorems to minimize F (5 pts).
3. Consider the function F =
X,Y,Z,W (1, 3, 4, 6, 9)
+ d(0, 5, 7, 11, 12)
Give the minimized SOP expression of F using K-map [5 pts].
Give the canonical sum of F (5 pts).
Implement the function F using a 74 138 decoder and label the decoder pins appropriately [5 pts]
74 x 138
G1 G2A G2B y0 y1 y2 y3
Give the canonical product of F (5 pts).
A B C
y4 y5 y6 y7
4. The following logic circuit consists of a 2-4 decoder and a 4-1 multiplexer. Its inputs are X, Y, S0, and S1 (where S1 is MSB and and S0 is LSB), and its output is F (15 points).
D0 4-1 2-4 Y X decoder D1 mux D2 D3
5. Consider a 2-bit binary subtracter dened as follows. The inputs A, B and C, D form the two 2-bit numbers N1 and N2 . The circuit will compute the dierence N1 N2 on the output bits F (most signicant) and G(least signicant). Assume the circuit never sees an input combination in which N1 is less than N2 , The output bits are dont care in these cases (15 points). (a) Fill in the 4-variable truth table for F and G (5 pts).
A B C D F G
S1
S0
Derive the truth table of the logic diagram (7 pts).

X Y S1 S0 F
(b) Derive the minimum SOP for F and G using K-map (5 pts).
F AB CD CD G AB
Find the minimal sum of products expression for the diagram using K-map (8 pts).
XY S1S0
(c) Implement the sum of products expression from (b) using two 8:1 mux for both F and G. Draw the schematics and clearly label the inputs and outputs of each pin of the mux (5 pts).
8:1 MUX En 8:1 MUX En
I0 I1 I2 I3 I4 I5 I6 I7 s2 s1 s0 Y
I0 I1 I2 I3 I4 I5 I6 I7 s2 s1 s0 Y

SolutionProblem3: A.
B.
ECSE 2610 Homework Assignment 1

Due date: Sept 6 in Class
For all problems, to receive full credit, you need show the process to obtain your answer. It is NOT enough to just write down your answer.
1. Problems 2.1(a), (f), 2.3 (c), 2.5 (a), 2.5 (f), 2.6(a), (f) (7 points) 2. Problems 2.7 (a), (c), (d), 2.10 (a), (b) (5 points) 3. Problems 2.11 (ignore one's complement representation) (5 points) 4. Problems 2.12 (4 points)
ECSE 2610 Homework Assignment 2

Due September 13 in Class
1. Perform the following additions and subtractions and show the processes Indicate if overflow occurs. Note 2 stands for twos complement (6 points) 110101 2 + 1011 2 11110101 2 - 1011 2 01111111 2 - 1111 2
2. Problem 3.1 (a,h), (2 pts), 3.5 (2 pts), 3.10 (2pts)
Due date Feb
Due date September 20 in class 1. Problem 4.6, 4.10 (a), (b), (e), and (f) 2. Using DeMorgan's law to find the complement of the following expressions and obtain the dual of each expression directly from its complement. a) F=X'Y + X'Y'Z b) F=(A'+B'+CD)(B+C'+D'E') c) F=(((A+B)'+C')'+D)' d) F=AB(C'+D')+A'B'C'+CD'(A+C') 3. Prove the equality of the following equations and then using the principle of duality to obtain their duals. a) AB + AB'C= AB + AC b) XY' + X'Z + Y'Z= XY' + X'Z c) (B'+C)(B'+D)=B'+CD
hw3fall13.htm[12/12/2013 10:43:19 PM]
COCO 2610 Homework 4 due date: Sept. 27 in class
1) 4-14 (c)-(f) 2) 4-15 (a) and (f) 3) Given F=X+YZ a) give its truth table b) give its canonical sum c) give its canonical product d) explain the difference between the original expression (F=X+YZ) and the canonical sum 4) Design a combinational circuit that takes 2 inputs and outputs its two's complement. a) specify the input and output, how many outputs ? b) produce the truth table c) give the canonical sum for each output d) minimize each output expression if necessary using K-map
COCO 2610 Homework 5, due date: Feb
COCO 2610
Homework 5, due date: October 4 in class
1) 4.18 (c), (d), and (e) 2) Find the minimal product of sums for the problems in 1) 3) 4.58 (c), (d), and (e) 4) Design a combinational circuit that has three inputs A, B, and C (one bit for each) and two outputs D0 and D1. The output should be the product of A and B if C is false, else the output is the sum of A and B a) produce the truth table for both outputs b) give the canonical sum for each output c) minimize each output expression independently if necessary using K-map d) draw the logic diagram for the combinational circuit.
HW5Fall13.htm[12/12/2013 10:43:20 PM]
COCO HW6 Due date: October 11 in class
1) 6.20 (a), (d), and (e) 2) Implement Table X 6.41 (page 512) with one 74 x 138 plus other gates. 3) Given F=
xyzw
(0,10,12,14) ,
implement it using 74x151 mux. Label the chip inputs
appropriately and assert its enables.
COCO 2610 Homework 7
Due date: Oct. 25th in class
Problems:
1. Given the following logic diagram
Write the Boolean expression for Q
Construct its truth table
Sketch the output (Q) waveform given the input waveforms S and R as follows
2. For the D FF shown in Fig. 7.15 (a), remove the rst inverter that is connected to the CLK, producing a new FF. Give the functional (truth) table of the new FF and its output Q waveform for the same input D and CLK wave forms shown in gure 7-16. What kind of FF is this ? And how is it dierent from the positive edge triggered FF ?
ECSE 2610 HW #9 Due Nov 8th in class
Design a synchronous Mealey machine with input X and output Y. The output Y should be asserted for one clock cycle whenever the sequence 011 or 100 has been observed in the input X. Note the pattern may be overlapping. The machine should start assuming that a 0 has already been input.
1) Identify the possible states and complete the state diagram 2) Produce the state/output table 3) Produce the transition table, assuming the state binary assignments based on gray code 4) Assume the use of D FFs, derive the excitation table 5) Derive the minimum excitation equations using K-map 6) Derive the minimum output equation using K-map 7) Draw the circuit diagram for the state machine
Homework 9 Solution Total 35 points. 1.
3.
4.
2.
5.
COCO HW#10, Due Nov 15 in class 2) Use the 74x163 and any additional logic that you need to implement a modulo-11 counter that counts the sequence 5,6, .., 15, 15, 5, 6 ... Note RCO output in 74x163 is the carry-out from the most significant bit. It is 1 when all outputs are 1. 3) Design a counter that counts from 0, 1, 3, 5, 0 1, ... Implement the counter using T (with enable). Show the state table, transition table, and the schematic diagrams.
6.
7.
HW 10 Solution (Total 20 points) 1.
3.
2. 4.
Rensselaer Polytechnic Institute, ECSE-2610 Computer Components & Operations Studio Exercise 2, Jan. 31, 2006
Rensselaer Polytechnic Institute, ECSE-2610 Computer Components & Operations Studio Exercise 2, Jan. 31, 2006
Studio Exercise 2 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute Sept. 4, 2011 Put your name etc on all sheets you hand in. (It's not necessary to list your blood type :-)) This exercise is due at the end of the this studio .
a. A=(X*Y)'+(X+Z')' b. B=(X'*Y')+(X*Z) c. C=(X'+Y')*(X'*Z) d. D=[(X+Y)*(X'+Z')*(Y+Z')]'
1. [8] Perform the following conversions (all numbers are unsigned). I know that your calculators are programmed to do this. However, please do these by hand. (Pretend that you've been hired by MS to design a new calculator; so you have to know how this is done.) (8 points) a. 45610=__________? 2 =__________? 8 c. 73910=__________? 16=__________? 8
(Note: to make the typing easier, we often use an apostrophe for the NOT function.) For the Z,Y,X input variable, consider Z the most significant and X the least significant bit. Go to Simulation IO.clf and use the Hex Keyboard wo/STB to generate the Truth Table inputs. Use the LogicWorks connect by name feature for all inputs. Go to Simulation Gates.clf and use AND-n, OR-n and NOT- gates to simulate each function, where n is the number of gate inputs. Use A,B,C,D for the output function names. Fill in Truth Tables for each of the functions given. Identify which functions have identical Truth Tables. Hand in a sheet with the Truth Tables for each function. 5. [2] Which functions have identical truth tables?
b. 10101112 =__________? 10=__________? 8 d. DEAD 16=__________? 10=__________? 2 2. [10 ] a. Give the unsigned binary representation of 23410, 2348 , and 23416 respectively.
b. Let A=110101002 and B=011010012 , compute A+B and A-B in unsigned binary. Show the results and the process.
Total: 40
3. [10] Remember the oversimplified Boolean formula for whether you will graduate: G = you will graduate C = you've taken all the required courses P = you've passed them T = you've transferred in the courses you didn't take here. M = you owe money to the Bursar G = ((C * P) + T) * M' where *, +, and ' represent logical AND, OR, and complement operations respectively. Design this in LogicWorks. Put switches on the inputs and a display module on the output. Put a text field in LogicWorks showing your name. Set some reasonable values and get a printout showing your name, the circuit, and the output. Your name must be part of the LogicWorks circuit. It cannot be handwritten on the paper after it is printed. 4. [10] Using LogicWorks to compute truth tables (a table that lists each input combination and the corresponding output): Here are 4 Boolean functions:
Lab2Fall13.html[12/12/2013 10:13:28 PM]
Lab2Fall13.html[12/12/2013 10:13:28 PM]

Studio 3, Feb. 7, 2007, ECSE-2610 COCO, RPI
Studio Exercise 3 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute September 11, 2013
Put your name etc on all sheets you hand in. Studio due at the beginning of the next session. 1. Two's complement arithmetic: 1. [6 points] Find all the decimal numbers that are NOT representable numbers for 6-bit two's complement representation. E.g, 30 is representable, but 40 is not. a. -30; b. 32; c. -32; d. -40; e. -16; f. 50 2. [8] Convert the following 4-bit 2s complement binary numbers into decimal. E.g., 1001 would be -7. 0000, 0001, 0010, 0100, 1000, 1100, 1110, 1111 3. [8] 2s complement the above 8 numbers. E.g., 1001 would complement to 0111. 4. [8] Now, consider that the above 8 numbers as unsigned 4-bit binary numbers. Convert them to decimal. 5. [8] Convert them to hexadecimal corresponding to the unsigned binary. 6. [8] Convert the following pairs of decimal number into 5-bit two's complement representations: a. -3, -7; b. -1, 1; c. 5, -12; d. -5, 12 7. [8] Add each pair 5-bit two's complement numbers obtained in last step, and show the answer in both 2s complement binary and decimal. 8. [8] Convert those 8 decimal numbers into sign-magnitude binary form. E.g., -6 would be 1100. 1. [5 points] Assume that you have only AND gates with exactly 4 inputs. However you want to compute A * B * C, where '*" represents AND operation, that is, take the AND of only 3 variables. Draw a LogicWorks circuit that does this. Hand in a printout of the circuit. 2. [5] Assume that you have only AND gates with exactly 4 inputs. However you want to compute A*B*D*E*F*G*H, that is, take the AND of 8 variables. Draw a LogicWorks circuit that does this Hand in a printout of the circuit.
COCO Studio 3 Solution 1. Twos complement arithmetic: 1. [6 points]: representable a. is representable b. is not representable c. is representable d. is not representable e. is representable f. is not representable 2. [8 points] a. b. c. d. e. f. g. h.
Fall 2013

3. [8 points] a.

b. c. d. e. f. g. h.
Lab3Fall13.html[12/12/2013 10:13:28 PM]
COCO Studio 3 Solution 4. [8 points] a. b. c. d. e. f. g. h. 5. [8 points] a. b. c. d. e. f. g. h. 6. [8 points] a. b. c. d.
Fall 2013
COCO Studio 3 Solution 7. [8 points] a. b. c. d. 8. [8 points] a. b. c. d. 1. [5 points]
Fall 2013

COCO Studio 3 Solution 2. [5 points]
Fall 2013
Studio Exercise 4 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute September 18, 2013
Put your name etc etc on all sheets you hand in. Studio due at the end of this session. 1. [10] Given the circuit diagram below for a combinational circuit,
a. Using LogicWorks, produce another logically equivalent diagram consisting of only NAND gates
b. Using LogicWorks, produce another logically equivalent diagram consisting of only NOR gates
COCO Studio 4 Solution

c. Using truth table, verify the new logic diagrams are logically equivalent to the original one, and point out the benefits of the alternative diagrams over the original one.
Fall 2013
1. [10 points] a. NAND Circuit
2. [3]Use axioms and theorems of switching logic to prove X + X' Y + X' Y Z = X + Y
b. NOR Circuit
3. [3]Use deMorgan's theorem again and again on this expression, until every negation is over only one term. ((A H + B') F' (C' D' + E)' G')'
4. [4 pts] Apply Theorem T8 and T8 to convert expression (X+Y') Z+XYZ to sum of products and products of sums respectively.
c. NAND and NOR gates are functionally complete (universal gates). Any Boolean function can be constructed from them. Using a single gate makes is more cost efficient and simpler when laying out a circuit.
X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Original 0 1 0 0 0 0 1 1 NAND 0 1 0 0 0 0 1 1 NOR 0 1 0 0 0 0 1 1
ECSE-2610 Computer Components & Operations
COCO Studio 4 Solution 2. [3 points] 3. [3 points]
Fall 2013
Rensselaer Polytechnic Institute ECSE-2610 Computer Components & Operations Studio Exercise 5 September 24, 2013
Put your name etc etc on all sheets you hand in. The Lab is due at the end of the studio 1. For the function F = W'Y'Z' + WX'YZ' + WYZ + WX'Y'Z a. [5 points] Convert to a canonical product of sums form.
4. [4 points] SOP: POS:
b. [5] Implement F in Logicworks, both as originally given, and in the canonical product of sums form. c. [5] Using the Karnaugh map, obtain the minimum sum of products form for F. 1. Design a combinational circuit that consists of four inputs A1,A0,B1,B0 and one output F. The output is 1 if A1A0 is larger or equal to B1B0. a. [5] Give the canonical sum of products of F b. [5] Implement the canonical sum of products of F using Logicworks c. [7] Use K-map to minimize the canonical sum of products of F, producing a minimal sum of product d. [5] Implement the minimal sum of product using logic works e. [3] Compare the canonical sum of products with the minimal sum of products and find out how many gates have been saved. f. [5] Implement the minimal sum of products in LogicWorks using NAND gates only.
Total: 45
Lab5Fall13.html[12/12/2013 10:13:28 PM]
COCO Studio 5 Solution 1. a. [5 points]

Fall 2013
COCO Studio 5 Solution

W X Y Z' W X Y' Z W X Y' Z' W X' Y Z' W X' Y' Z F W X' Y' Z' W' X Y Z W' Y' Y Z W' X' Y Z' W' X' Y' Z
Fall 2013
b. [5 points] Logicworks
W Y Z W Y X Z F W Y Z W Z X Y
c. [5 points] YZ\WX 00 01 11 10
00 1 0 0 0
01 1 0 0 0
11 0 0 1 0
10 0 1 1 1
COCO Studio 5 Solution 2. a. [5 points]

Fall 2013
COCO Studio 5 Solution c. [7 points] YZ\WX 00 01 11 10 00 1 1 1 1 01 0 1 1 1 11 0 0 1 0 10 0 0 1 1 d. [5 points] Logicworks
B1' B0' A1 A0 A0 B1' A1 B1' A1 B0' F
Fall 2013

b. [5 points] Logicworks
A1' A0' B1' B0' A1' A0 B1' B0' A1' A0 B1' B0' A1 A0' B1' B0' A1 A0' B1' B0 F A1 A0' B1 B0' A1 A0 B1' B0' A1 A0 B1' B0 A1 A0 B1 B0' A1 A0 B1 B0
e. [3 points] Save 7 gates (or 22 gates with inverters) Canonical Form: 13 gates (or 33 gates with inverters) Minimal Form: 6 gates (or 11 gates with inverters) f. [5 points] Logicworks
B1' B0' A1 A0 A0 B1' A1 B1' A1 B0' F
Studio Exercise 6 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute October 2, 2013
Put your name etc etc on all sheets you hand in. Since this studio is longer, it is due at the start of the next studio. lab is to learn the espresso program. Read this intro (http://www.ecse.rpi.edu/~qji/COCO13/espresso_intro.ppt). Download the espresso to your PC from here (http://www.ecse.rpi.edu/~qji/COCO13/espresso.exe) Download the first sample data file test.txt (http://www.ecse.rpi.edu/~qji/COCO13/test.txt). Run espresso in command prompt window as follows
The purpose of this
3. [2] What's the resulting expression after simplification using the Kmap?
4. [2] Create a small input file to correspond to the above truth table with 3 inputs and 2 outputs. You'll have to add the proper header declarations. Include a printout of the file. 5. [2] Run it thru espresso; include the result. 6. [2] What boolean expression does that represent?
espresso test.txt and see if you get the same answer as testOut.txt (http://www.ecse.rpi.edu/~qji/COCO13/testOut.txt). Consider the following truth table with 3 inputs and 2 outputs. Its a full adder, with D being the carry out and S being the sum.
ABC 000 001 010 011 100 101 110 111 DS 00 01 01 10 01 10 10 11
7. [2] Here's a larger example. The goal is to take a 3-bit number from 0 to 4 and increment it, mod 5. That is, 0->1->2->3->4->0. Write the truth table. Call the 3 inputs ABD, and the 3 outputs DEF. Don't write rows for all inputs don't care. 8. [3] What are the boolean expressions for D, E, and F?
9. [2] Simplify the espression for F using Kmap.
10. [2] Now, create the espresso input file (and show us what it is).
1. [5] Write down the unminimized expression (canonical sum) for D.
11. [2] Run espresso. Include your output.
2. [2] Write the corresponding K-map, with the variables in this order.
12. [1] What is the simplified expression for F?
COCO Studio 6 Solution 1.

13. [3] The final example will take a 2-bit number and perhaps rotate it 1 bit. There are 3 inputs: A, B, C. There is a 2-bit output: D, E. If A=0, then D=B and E=C. If A=1, then BC gets rotated 1 bit, so that D=C and E=B. (Rotating right and rotating left do the same thing here.) Write the truth table. Here are a few rows.
ABC 000 001 ... 101 DE 00 01 10
Fall 2013

[5 points] [2 points] C\AB 0 1
2.
00 0 0
01 0 1
11 1 1
10 0 1
3. 4.
[2 points] [2 points]
# Full Adder input .i 3 .o 2 000 00 001 01 010 01 011 10 100 01 101 10 110 10 111 11 .e
14. [2] What's the canonical sum Boolean expression for D?
15. [2] Create the espresso input file.
16. [2] Run it thru espresso. What's your output?
17. [2] What's the boolean expression for D?
5. [2 points]
# Full Adder output .i 3 .o 2 .p 7 100 01 010 01 001 01 111 01 -11 10 1-1 10 11- 10 .e
Note: These small examples do not capture the full power of espresso. It really shines with large inputs, with dozens of variables and hundeds of rows in the truth table.
6.
[2 points]
COCO Studio 6 Solution 7. [2 points] A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Fall 2013
Fall 2013
D 0 0 0 1 0 x x x
E 0 1 1 0 0 x x x
F 1 0 1 0 0 x x x
# Mod 5 Counter Output .i 3 .o 3 .p 4 011 100 001 010 010 010 0-0 001 .e
12. [1 points] AC 13. [3 points] A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
8.
[3 points] [2 points] C\AB 0 1 AC
9.
00 1 0
01 1 x
11 0 x
10 0 x
D 0 0 1 1 0 1 0 1
E 0 1 0 1 0 0 1 1
10. [2 points]
# Mod 5 Counter Input .i 3 .o 3 000 001 001 010 010 011 011 100 100 000 .e
14. [2 points]

# Two bit rotation input .i 3 .o 2 000 00 001 01 010 10 011 11 100 00 101 10 110 01 111 11 .e
Fall 2013
Rensselaer Polytechnic Institute ECSE-2610 Computer Components & Operations Studio Exercise 8 October 16, 2013
Put your name etc etc on all sheets you hand in. Due by the end of the studio. 1. [20 points] Implement the following truth table using decoders and multiplexers. Specifically, the function has three inputs A, B, and C and two outputs D and S. The inputs and outputs are related by the truth table below.
2. 3. ABC 4. 000 5. 001 6. 010 7. 011 8. 100 9. 101 10.110 11.111
16. [2 points]
# Two bit rotation output .i 3 .o 2 .p 4 01- 10 1-1 10 11- 01 0-1 01 .e
DS 00 01 01 10 01 10 10 11
Implement the canonical sum expression for the first output using one 74x 138 decoder plus one NAND gate and the canonical sum expression for the second output using one 74x151 multiplexer only. Both implementations must be done on the breadboard. Experimentally verify your implementation using the truth table above. 12. [10] Pretend that you have lots of 2-4 decoders (74x139). Use 5 of them to design a 4-16 decoder. Build it in LogicWorks. Put a hex keyboard on the inputs, and 16 1-bit probes on the outputs. Try setting various hex input numbers, and see that the correct single output is set each time. Hand in a printout of the circuit.
17. [2 points]
4
Lab8Fall13.html[12/12/2013 10:13:29 PM]
Studio 8 Solution 1. [20 points] Hardware Implementation

+5V
COCO Fall 2013
Studio 8 Solution 2. [10 points] LogicWorks Implementation

1 1 1
COCO Fall 2013
0 Y7 4 G2A Y6 5 G2B Y5 138 Y4 3 C Y3 2 Y2 B 1 A Y1 Y0

6 G1 7 9 10 11 12 13 14 15 1 2 4 5 9 10 12 13
Y3
20
6
3 B a Y1 2 A Y0
139 Y2
7 6 5 4
D
15
1 0 1 0 1 0
1 G Y3
C B A
8
0 4 8 C 1 5 9 D 2 6 A E 3 7 B F A B C D
Y3
3 B a Y1 2 A Y0
139 Y2
7 6 5 4
13 B b Y1 14 A Y0
139 Y2
9 10 11 12
1 0 1
1
15
+5V
Y3
13 B b Y1 14 A Y0
139 Y2
9 10 11 12
1 1 1
7 12 13 14 15 1 2 3 4
EN 7 6 5 4 3 2 1 0
151
Y W
5 6
0
15
1 Y3 139 Y2 13 B b Y1 14 A Y0 G
9 10 11 12
1 1 1
C B A
9 C 10 B 11 A
and A2=1, then B1B0=10. If A3=A2=0 and A1=1, then B1B0=01. If A3=A2=A1=0, then B1B0=00. NAME:__________________________________, RCS Id: ____________ Section:_____________ 1. Write the truth table. 2. Minimize it using any legal technique.
Studio Exercise 9 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute Oct. 23 , 2013
IMPORTANT: Keep the lab neat. Scraps of wire or insulation may fall on the floor. Collect them as you go and put them in the trash when you are done. You are not finished until the lab is clean and your protoboard is put away.
3. Design a circuit. Be sure that your design uses chips that are available in the lab. 4. Simulate it in LogicWorks. Print out the circuit showing what the output is for the input A3A2A1=011. 5. Build it on the protoboard. 6. Demo it to the TA and have him/her sign off. 7. Put everything away and have the TA sign off. TA sign off, circuit works: ____________. Everything cleaned up and put away: ____________
Design a 3-to-2 priority encoder using any available 74xx chips (except a priority encoder chip itself). A priority encode has several inputs that each may be true or false. It reports the number of highest true input. The most significant bit of the input has the highest priority while the least significant bit has the lowest priority. One application would be a computer's I/O bus. If several devices simultaneously want service, the priority encoder would pick the highest one.
Your circuit will have 3 inputs: A3, A2, and A1, where A3 is the MSB, and 2 outputs, B1 and B0, where B1 is the MSB. If A3=1, then B1B0=11. If A3=0
http://www.ecse.rpi.edu/~qji/COCO13/Lab9Fall13.html[12/12/2013 10:20:44 PM] http://www.ecse.rpi.edu/~qji/COCO13/Lab9Fall13.html[12/12/2013 10:20:44 PM]
COCO Studio 9 Solution 1. [5 points] Truth Table A3 A2 A1 B 1 B 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1
Fall 2013
COCO Studio 9 Solution 4. [5 points] LogicWorks

02
2 3 1
Fall 2013
08
1 2 3
5 6
8 9
10
4 5
1 0
11 12
13
A3
04
A2 A1
13 11 9 5 3 1 12 10 8 6 4 2
2.
[5 points] Minimization A1 \ A3 A2 00 01 11 10 0 0 1 1 1 1 0 1 1 1 B 1 = A2 + A3 A1 \ A3 A2 00 01 11 10 0 0 0 1 1 1 1 0 1 1 B0 = A2A1 + A3 5.
1 0 1 0
9 10
12 13
11
1 B1 0 B0
[10 points] Hardware
Lab 9, S05, ECSE-2610 Computer Components & Operations, RPI
NAME:__________________________________, RCS Id: ____________ Section:_____________
Studio Exercise 11 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute October 30, 2013
IMPORTANT: Keep the lab neat. Scraps of wire or insulation may fall on the floor. Collect them as you go and put them in the trash when you are done. You are not finished until the lab is clean and your protoboard is put away. You have until the start of next studio to hand this in.
Part 1 (3 points)
Q Q* U V
Write its Excitation Table. (This shows what the 2 inputs have to be to make the F/F change from one particular state to another particular state.) Use 'x' for don't care. I filled in the first row.
U V Q Q*
Consider a new (non-existent) type of flip-flop, the U-V F/F. Here is the Next State Table. (The next state, Q*, is a function of 3 variables: the current state and the 2 F/F inputs.)
Part 2 (4 points)
Use a K-map to find its Characteristic Equation (a Boolean function giving the next state Q* from the current state Q and inputs U and V).
http://www.ecse.rpi.edu/~qji/COCO13/Lab10Fall13.html[12/12/2013 10:21:19 PM]
UV Q 0 00 01 11 10
F/F next state table.)

Q Q* J K
1
The J-K excitation table tells you what J and K have to be to change Q that way. Write down that table to remind yourself. Hint: construct the J-K excitation table based on the J-K characteristic equation the same way as you did for part 1. 0 1
Q* = __________________________________________
Part 3 (7 points)
Your boss wants you to use a U-V F/F. Since it doesn't exist, you'll have to create one from a J-K F/F. So, design the input (excitation) network to make the U-V flip-flop from a J-K flip-flop.
U V
That is, you'll design a box with inputs U and V, and outputs Q and not Q. It will act like a U-V F/F. Inside will be a J-K F/F and some combinational logic providing inputs to J and K.
Q*
Now combine the U-V next state table with the J-K excitation table, to find what J and K have to be for each value of U and V. I filled in 2 rows.
This will take some serious thinking:

1 0 0 0
You know how Q should change depending on U and V (that's the U-V
http://www.ecse.rpi.edu/~qji/COCO13/Lab10Fall13.html[12/12/2013 10:21:19 PM] http://www.ecse.rpi.edu/~qji/COCO13/Lab10Fall13.html[12/12/2013 10:21:19 PM]
Draw circuits for them inside the earlier figure.
Part 4 (3 points)
Simulate your circuit in LogicWorks. Demo it to the TA.
x 0
Part 5 (3 points)
You have to calculate J and K from U, V, and Q. Fill in K-maps for J and K and find simplified expressions.
UV
Build it on the proto-board. Demo it. Put everything away. TA sign off, circuit works: ____________. Everything cleaned up and put away: ____________
00
01
11
10 J = ___________________
Qiang Ji
UV
00
01
11
10 K = ______________________
Studio 10 Solution 1. U-V Flip Flop Excitation Table (3 points) Q 0 0 1 1 Q* 0 1 0 1 U X X 0 1 V 0 1 X X
COCO Fall 2013
Studio 10 Solution Q\UV 00 01 11 10 0 0 1 1 0 1 X X X X Q\UV 00 01 11 10 0 X X X X 1 1 1 0 0 4. LogicWorks (3 points)
COCO Fall 2013
2. U-V Characteristic Equation (4 points) Q\UV 00 01 11 10 0 0 1 1 0 1 0 0 1 1
04
3. U-V from J-K (7 points) Q 0 0 1 1 U 0 0 0 0 1 1 1 1 Q* 0 1 0 1 V 0 0 1 1 0 0 1 1 J 0 1 X X Q 0 1 0 1 0 1 0 1 K X X 1 0 Q* 0 0 1 0 0 1 1 1 J 0 X 1 X 0 X 1 X K X 1 X 1 X 0 X 0
1 0 1 0
U V
13 11 9 5 3 1
12 U' 10 8 6
0 +5V V U'
3 J 2 K
112
4 2
15 4 1
Q5 Q 6
CLR PRE CLK
5. Hardware (3 points)
Q2 Q1 Q0 Q2* Q1* Q0*
NAME:__________________________________, RCS Id: ____________ Section:_____________

Use D FF (or pick another type of F/F ) to implement the counter Given the transition table above and the characteristic function of the D FF, produce the excitation table below, which relates next state logic output (input to FF) as a function of current state Q2 Q1 Q0 D2 D1 D0
Studio Exercise 11 ECSE-2610 Computer Components & Operations Rensselaer Polytechnic Institute Nov 6, 2013
IMPORTANT: Keep the lab neat. Scraps of wire or insulation may fall on the floor. Collect them as you go and put them in the trash when you are done. You are not finished until the lab is clean and your protoboard is put away. Design and build a modulo-8 counter with the counting sequence 0,1,2...7,0,1 and display the output. The state table is given below. Using three states variables Q2, Q1, Q0, with the state assignment S0=000, S1=001, ..., S7=111.
S S0 S1 S2 S3 S4 S5 S7 S* S1 S2 S3 S4 S5 S6 S0
Using the excitation table, find minimized expressions for the F/F excitations, as functions of the current states. Use LogicWorks to develop/implement the circuit and verify its output using only basic gates and FFs. Implement the circuit on the prototype board using 74x163 (see table 8-13 (p713) for its state table. The table is available at http://www.ecse.rpi.edu/~qji/COCO08/page696.jpg), 74x00 and the 7 segment. display/driver board. Use a Timer board to generate clock signal with 1Hz (note simulate the implementation using Logicworks first). Check and verify as you build. Have the non-builder check wiring. Remember: extra wires are harder to find than missing wires. Check all power and ground connections. Use a "Divide and Conquer": Start with what you "know" is working, such as the input, or independently test the output or other sections. Use the logic probe to see what youve got. TA sign off, Logicwork circuit works:_______ Prototype board circuit works: ____________. Everything cleaned up and put away: ____________
Note that there is no input and no output. Based on the state table above and state assignments, produce the transition table below, which relates next state as a function of current state

Notes Final Mid HW Studio Quizes 4 1

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Analog Versus Digital Chapter 1 Introduction

Examples What is Digital Design ?

Advantages of Digital Systems

Digital Devices: Gates

Characteristics of 2-Input AND gate

Characteristics of 2-Input OR gate

Digital Abstraction Flip-Flop

Invalid 1.5 V Logic 0 Logic 0 Low

Software for Digital Design Digital Abstraction

Integrated Circuits (contd)

Integrated Circuits (contd)

Programmable Logic Devices

Printed Circuit Boards

Chapter 2 Number Systems and Codes

Positional Number Systems

Positional Number Systems (contd)

Positional Number Systems (contd)

Binary and Decimal Number Conversion

HEX and Binary Conversion

Refer to Table 2-2 for a summary of conversion methods.

OCTAL Numbers (contd) Binary to Decimal

Binary Addition and Subtraction

Binary Addition: Example

Binary Addition Table

Binary Subtraction: Example

Binary Subtraction Table

HEX Addition and Subtraction

Representation of Signed Numbers

Twos Complement Representation

Twos Complement Representation (contd) Signed Magnitude Representation

, where di is -di for the MSB.

2s Complement Representation v. 2s Complementing Operation

Twos Complement Number Range

Decimal to Twos Complement Twos Complementing

Twos Complement Representation (contd)

Twos Complement Addition

Twos Complement Subtraction Twos Complement Addition

Gray Codes Construction

Binary Code for Decimal (BCD)

Chapter 3 Digital Circuits

Logic Signals (contd)

Logic Signals (contd)

Logic 1 (high) 3.5 V invalid or undefined 1.5 V Logic 0 (low) 0.0 V

Truth Table Digital Circuit

Algebraic Representation Digital Circuit (contd)

Gates and Their Truth Tables

truth table ? algebraic expression ? truth table ?

Logic Families (contd)

Electrical Behavior of CMOS Circuits

Logic Families (contd)

Fan-in and Fan-out

Chapter 4 Combinational Logic Design

Axioms Table of Contents

(A3) 1 + 1 =1 (A4) 0 + 0 =0 (A5) 0 + 1 = 1+ 0=1

Single Variable Theorems

These theorems can be proved using axioms via perfect induction.

Two (Three) Variable Theorems

Two (Three) Variable Theorems (contd)

swapping + and and complementing all variables. For example,

Two (Three) Variable Theorems (contd)

Logic Functions Representations

Duality v.s. DeMorgans Law

Duality v.s. DeMorgans Law