Beruflich Dokumente
Kultur Dokumente
DDR Overview
Receiver
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SSTL_2
Chipset
North Bridge
SSTL_2
Address / Command
Data/Strobe/Mask
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SSTL_2
Chipset
North Bridge
SSTL_2
Address/Command
Data/Strobe/Mask
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TT V TT V TT
Processor Processor
NB NB
CLK CLK
V /REF active VTT TT/REF active termination termination voltage voltage switching regulator switching regulator V TT V TTvoltage voltageisland island de-couple de-couplethoroughly thoroughly to VSS V DD and VSS
Four-layer motherboard
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VTT/VREF Implementation
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10
VREF Requirements
m Track 50% of (VDDQ-VSSQ) over
Voltage Temperature Noise
m Supplies minimal DC current (input leakage only) and only small transient currents
Input to NFET gates of a differential pair
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C C
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VREF Recommendations
m Use global VREF distribution scheme
Eliminates variation and tracking of multiple generators Best performance if kept clean
due to trimming
Minimizes DC error caused by the load current of multiple device input leakage
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VREF Generation
m Example of VREF generation using a resistor divider
VDD
VDDQ
VDDQ
VDDQ
R VREF
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VTT Requirements
m Track 50% of (VDDQ-VSSQ) over
Voltage Temperature Noise
m Maintain <40mV offset from VREF over these conditions m Source and sink DC current for signal termination
Absolute maximum current is 2.6-2.9A for a 64/72-bit channel
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VTT Recommendations
m Several solutions exist that are tradeoffs of cost, integration, and performance
Standard analog components (Motorola, National, Fairchild, etc.)
High current output, good accuracy
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VTT Recommendations
(continued)
m Use global VREF as input reference to minimize tracking error and offset m Use high-quality filter components
Low Rs on filter inductor Low ESR and ESL on filter capacitor to minimize DC and dynamic offset
Recommend the use of multiple parallel capacitors and/or Sanyo OS-CONs to minimize ESR and ESL
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ML6554 Regulator
Termination Resistors
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Voltage Margining
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VREF/VTT Margining
m Use the V REF In pin on the ML6554 to margin V REF and VTT
VTT and VREF out follow VREF In
m VREF specification is 0.49*VDD to 0.51*VDD m VTT specification is V REF +/- 40mV m Use simple resistor divider below connected to VREF In pin on ML6554
VREF In On ML6554 1K 1K
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VDD Margining
m VDD specification is 2.3 to 2.7 volts m To margin VDD change LTC1530-2.5 to LTC1530-ADJ m Adjust VDD with resistor divider R1/R2.
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VDD Margining
+5 volts input
R1 R2
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Board Implementation
29
CK/CK#
VTT/VREF Generator
Chipset
North Bridge
SSTL_2
PC266 PC266 PC266 A A SDRAM SDRAM SDRAM A Reg. Reg. Reg. DIMM DIMM DIMM
Data/Strobe/Mask
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30
Chipset
North Bridge
Add/Comnd A
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31
PCB Considerations
m PC2100 DDR can be implemented in a low-cost PCB (standard PC100 motherboard technology) m Standard pad, anti-pad and via sizes can be used m No additional PCB test requirements relative to PC100
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PCB Routing
m DDR channel can be implemented in a 2S 2P board
Controller BGA ballout determines whether a four-layer board can be used, not the memory channel Two signal layers to get from controller to series resistor The channel can be routed on one signal layer from the series termination resistor out, with the exception of point-to-point signals
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m Routing Rules
5 mil trace/15 mil space on all in group SSTL nets Connector rules: 5 mil trace, 2 mil space from antipad, 7 mils from trace
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m Length matching from last DIMM pad to parallel termination resistor is less critical
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LR-D1
RS RT
LC-R2 LBGA2
LR-D2
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