001 - INTRODUCTION (Compatibility Mode)

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7/12/2012
THE ARCHITECTURE OF 8086
Baiju Karun
8086 Features
16-bit Arithmetic Logic Unit 16-bit data bus (8088 has 8-bit data bus) 20-bit address bus - 220 = 1,048,576 = 1 Mega
The address refers to a byte in memory. In the 8088, these bytes come in on the 8-bit data bus. In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper half of the data bus (bits 8-15).
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8086 Features
The 8086 can read a 16-bit word at an even address in one operation and at an odd address in two operations. The 8088 needs two operations in either case. The least significant byte of a word on an 8086 family microprocessor is at the lower address
8086: INTERNAL BLOCK DIAGRAM
BIU &EU
The BIU fetches instructions, reads and writes data, and computes the 20-bit address. The EU decodes and executes the instructions using the 16-bit ALU
The 8086 microprocessor has

The execution unit The bus interface unit
THE EXECUTION UNIT
Has the internal registers, ALU and the control unit
Registers
The scratch pad registers

AX (16 bits) -- AH and AL (each 8 bit) BX (16 bits) -- BH and BL (each 8 bit) CX (16 bits) -- CH and CL (each 8 bit) DX (16 bits) -- DH and DL (each 8 bit)
Data Registers are general purpose registers but they also perform special functions AX

Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations Must also be used in I/O operation
BX

Base Register Also serves as an address register Count register Used as a loop counter Used in shift and rotate operations Data register Used in multiplication and division Also used in I/O operations
CX

DX

Pointer and Index Registers

DI destination index for string operations SI source index for string operations SP stack pointer for accessing stack top BP base pointer for accessing any location in stack IP instruction pointer-points to the next instruction to be executed
Flag Register
SP: Stack pointer
Used with SS to access the stack segment Primarily used to access data on the stack Can be used to access data in other segments is required for some string operations When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations
BP: Base Pointer
SI: Source Index register

DI: Destination Index register

is also required for some string operations. When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations
FLAGS

CONDITIONAL FLAGS OF = Overflow flag SF = Sign Flag ZF = Zero Flag AF = Auxiliary carry Flag PF = Parity Flag CF = Carry Flag
CONTROL FLAGS DF = Direction Flag IF = Interrupt Flag TF = Trap Flag
Registers

Registers are in the CPU and are referred to by specific names Data registers
Hold data for an operation to be performed There are 4 data registers (AX, BX, CX, DX) Address registers Hold the address of an instruction or data element Segment registers (CS, DS, ES, SS) Pointer registers (SP, BP, IP) Index registers (SI, DI) Status register Keeps the current status of the processor On an IBM PC the status register is called the FLAGS register In total there are fourteen 16-bit registers in an 8086/8088

THE BUS INTERFACE UNIT

is responsible for address calculations pre-fetching instructions for the queue and sequencing instructions one by one
The BIU fetches instructions using the CS and IP, written CS:IP, to contract the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
THE INSTRUCTION QUEUE
There is a queue which fetches instructions ahead of the execution time and places them in a six byte first in first out (FIFO) queue Pre-fetching belongs to a class of ideas called pipelining, which means that both execution and fetching take place at the same time.
MEMORY SEGMENTATION
Each address is 20 bit But address registers are only 16 bits long There are four types of memory segments They cater to data, code, stack and another data segment called the extra segment
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Segment Registers (16 bits long)

CS code segment register DS data segment register SS stack segment register ES extra segment register
Calculation of a physical address from the logical address for a data segment
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Segment registers and corresponding segments
Segments and corresponding registers

Code segment ---- Instruction pointer (IP) Stack segment . Stack pointer (SP)
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Arithmetic Logic Unit
performs all arithmetic and logic computations. is the most important unit of the processor instructions that are fetched and decoded, are executed in the ALU. the ALU has direct access to the general purpose registers and flags.
Stack and physical address of the top of stack
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Segments and Corresponding Registers Used for Specifying Off Sets
Example
The content of DS is 345BH. The amount of data that is to be stored in the data segment is 12K bytes. Where in memory, will this segment be located?
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Solution

The base address of the segment is 345B0H The last address will have an offset of 12K from the base address . 1K = 1024 bytes 12 K = 12 1024 = 12288 = 3000H The last address of the segment = 345B0H + 3000H = 375B0H
Advantages of Segmentation
All address registers are only 16 bit long, though the physical address is 20 bits All addresses are re-locatable
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Memory Organization Little Endian
In the case of a word of data stored in memory if the lower byte is in the lower address and the higher byte is in the higher address it is called the little endian format
Little Endian Format

34E6H
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ADDRESSING MODES
The way in which operands are specified in an assembly language instruction is called its addressing mode For a move instruction, the format is MOV destination, source
Addressing modes basic assumptions
The operands can be in registers, in memory, or may be in the instruction itself. But the 8086 does not have an addressing mode in which both operands are in memory locations In the case of two operands, one of them can be in memory, but the other will have to be placed in a register . Data types should match i.e., the source and destination should both be either bytes or words
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Register Addressing
Here both the source and destination are registers MOV AL, AH MOV CH, BL MOV SI, BX MOV ES,AX
Immediate Addressing

Here, the source will be a constant data MOV AL, 45H MOV BX, 34E3H MOV CL,Q MOV PRICE,40 MOV NUMS, 0FC6H PRICE and NUMS are labels for memory addresses
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Direct Addressing

Here either the source or the destination will be a memory address MOV AX,[2345H] MOV [1089H],AL MOV AX , PRICE MOV COST,AL PRICE and COST are labels for memory addresses
Register Indirect Addressing
In this mode, the address of the data is held in a register Effective address EA = EA = { [BX] / [DI] /[SI]} MOV AL,[BX] MOV [SI], CL MOV [DI],AX
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Register Relative Addressing

In relative addressing mode, a number or displacement is part of the effective address EA = {[BX] /[DI] /[SI] /[BP]} + 8 bit or 16 bit displacement The displacement can be a 16 bit signed/unsigned number or an 8 bit sign extended number MOV CL, 10[BX] Thus the effective address is [BX + 10 ].
Based Indexed Mode
In this mode, an index register and a base register together carry the effective address . The content of these two registers are added and called the effective address. MOV AL,[BX][SI] MOV [BX][DI],CX
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Relative Based Indexed Mode
The effective address is the sum of the two registers and a displacement . MOV DL ,5[BX][DI] MOV 5[BP][SI], AX MOV CL,COST[BX[[SI]
Effective Address and Referred Segments for Various Memory Based Addressing Modes
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001 - INTRODUCTION (Compatibility Mode)

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001 - INTRODUCTION (Compatibility Mode)

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Generated by Foxit PDF Creator Foxit Software http://www.foxitsoftware.com For evaluation only.

THE ARCHITECTURE OF 8086

8086: INTERNAL BLOCK DIAGRAM

The 8086 microprocessor has

The execution unit The bus interface unit

THE EXECUTION UNIT

Has the internal registers, ALU and the control unit

The scratch pad registers

Pointer and Index Registers

SP: Stack pointer

BP: Base Pointer

SI: Source Index register

DI: Destination Index register

CONTROL FLAGS DF = Direction Flag IF = Interrupt Flag TF = Trap Flag

THE BUS INTERFACE UNIT

THE INSTRUCTION QUEUE

Segment Registers (16 bits long)

Segment registers and corresponding segments

Segments and corresponding registers

Arithmetic Logic Unit

Stack and physical address of the top of stack

Segments and Corresponding Registers Used for Specifying Off Sets

Memory Organization Little Endian

Little Endian Format

Addressing modes basic assumptions

Register Indirect Addressing

Register Relative Addressing

Based Indexed Mode

Relative Based Indexed Mode

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