Poster Paper Proc. of Int. Conf.

on Advances in Information Technology and Mobile Communication 2013

Data Converters in SDR Platforms

Shireesha C., 1Ravi Kishore Kodali and Dr. Lakshmi B
Department of Electronics and Communications Engineering National Institute of Technology, Warangal, Andhra Pradesh E-mail: 1 ravikkodali@gmail.com
Abstract For effective implementation of Software Defined Radio (SDR) in any RF application, a proper choice of data converter is an essential requirement. This paper describes the requirement of data converters in SDR, their key specificati ons that impact the SDR performance and a comparison of various data converters from leading vendors, which are suitable in an SDR application. Index Terms SDR, ADC, DAC

discussed below: [1] A. Analog input bandwidth Analog input bandwidth is the most important specification in high sampling rate wide band applications. ADCs input bandwidth depends on the shape of the input signal. Most of the common input signals are band-limited while wider bandwidths are required for signals such as transient events. As SDR implements many functions of different operating frequencies wider input bandwidth is required. Wider input bandwidth provides better slew rate performance and accurate sampling of input signal. [2] Wider bandwidth allows more noise into ADC. On sampling this signal the noise is widely spread and by filtering the excess noise is removed. But bandwidth parameter of an ADC needs some more improvement until then analog mixing to translate RF signal to IF band is used before ADC process. Today there are many commercially available high speed, high resolution ADCs which eliminate 2nd IF stage in SDR technology. ADCs with input bandwidth of 1GHz are offered by leading vendors and production of even high speed ADCs improves every year. B. Signal to noise ratio When the received input power from RF antenna is low the SNR of ADC becomes an important parameter of the receiver. The noise in an ADC is caused due to quantization noise, internal noise and aperture jitter. This noise is uniformly spread throughout the frequency band. The digital filter selects frequency band of interest where the signal energy is present and passes only portion of ADC noise thus improving the SNR of ADC. By increasing the number of encoded bits the effect of quantization noise can be minimized. But oversampling technique introduces improvement in SNR of ADC. The SNR with oversampling improvement effect is given by [7]

I. INTRODUCTION The entire signal processing in SDRs is performed in digital domain. With the emergence of powerful DSP processors development in SDR has accelerated. These SDRs provide high degree of flexibility and high performance. But the output from RF antennas is an analog RF signal, which needs to be converted into digital signal before applying digital signal processing techniques. Many wireless technologies like GSM,CDMA, WiMax, WiFi, 3G and 4G have evolved in recent years. End users would like to have various features of all these standards in one single portable device. SDR provides the reconfigurable architecture, which implements many functions that were traditionally implemented using analog circuitry.
TABLE I. O PERATING FREQUENCIES OF D IFFERENT WIRELSS STANDARDS Wireless standard GSM CDMA Bluetooth Wimax Operating Frequency 850MHz,900MHz,1800MHz 824-844MHz, 869889 MHz 2.4GHz 2500MHz, 3500MHz all the way to 5GHz

Table I describes the operating frequencies of various wire-less standards. From the table it is clear that ADCs in SDR that receive RF signal directly need to have a bandwidth up to 5GHz and should operate at sampling frequency of twice the signal bandwidth. As the receiver in SDR is a wideband receiver, the ADC in the receiver must have high resolution in order to detect weak signal in presence of other channels. Leading vendors are offering ADCs operating over 100MSPS at 12+ resolutions with input analog bandwidth up to 1GHz. II. KEY SPECIFICATIONS
OF

SNR 6.02n 1.76 10log(

fs / 2 ), BWSIG

ADC

where n is number of bits, fs is sampling frequency and BWSIG is the bandwidth of the signal. So from the above equation it is clear that instead of increasing n (number of bits) by increasing the sampling rate better SNR can be achieved. This SNR improvement is called Processing gain (PG) and is given by

Many factors determine the performance of ADCs but there are few specifications of interest that impact SDR performance. The contribution of these key specifications is 58 2013 ACEEE DOI: 03.LSCS.2013.2. 93

PG 10log(

BWSIG ) fs / 2

Poster Paper Proc. of Int. Conf. on Advances in Information Technology and Mobile Communication 2013
TABLE II. ADC S AND THEIR SPECIFICATIONS
ADC Maximum Conversion Rate 64 MSPS 105MSPS 150MSPS 125MSPS 105MSPS 105MSPS 105MSPS 80MSPS 125MSPS 130MSPS Resolution Bandwidth SNR & SINAD SFDR Jitter

AD9862(MxFE) AD6645 AD9254 ADS62P45 ADC14DS105 ADC12DS105 LTC2274 ADS5562 ADS5500 LTC2208

12 14 14 14 14 12 16 16 14 16

Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit

140 MHz 270MHz 650MHz 450MHz 1GHz 1GHz 700MHz 300MHz 750MHz 700MHz

64.2dBc & 64.14dBc 75dBc & 74.5dBc 71.8dBc & 71.0dBc 73.6dBFS & 73.2dBFS 72.5dBFS & 72.3dBFS 70dBFS & 69.9dBFS 75.1dBFS & 74.2dBFS 81.4dBFS & 80.2dBFS 72.3dBFS & 71.6dBFS 75.1dBFS & 75dBFS

81.0dBc 98 dBFS(two-tone) -84dBc 86dBc 85dBFS 85dbFS 94dBc 83dBc 83dBc 83dBc

1.2ps rms 0.1ps rms 0.1ps rms 150fs rms 0.1ps ms 0.1ps ms 80fs ms 90fs ms 300fs ms 70fs ms

Figure. 2: Spurious free dynamic range [3] Figure 1 Processing gain vs Signal Bandwidth at fs =500MSPS

and figure 1 gives the relation between processing gain and signal bandwidth. [8] It should be checked while implementing oversampling technique ADC should not reach its sampling rate limit. SigmaDelta ADC provides noise shaping and improves the SNR of an ADC. Time-interleaved ADC systems can also be used to achieve oversampling. C. Clock Jitter Clock jitter and aperture uncertainty represent the same problem. Jitter also affects the SNR of the ADC. As frequency of the signal increases the effect of aperture jitter also increases. This is because the high frequency signals slew more in amplitude during the period of uncertainty. The relation between SNR and jitter is given by

situations where the incident power at the receivers antenna is of substantial power levels. This can happen when the wanted signal is strong which is a desirable situation, or when an in-band interferer is strong which is an undesirable situation. When the interferer is strong it limits the ADC performance. Since the total signal, i.e sum of wanted and interferer, already approaches the full scale range of analog input signal. So the linearity of ADC decides whether the wanted signal can be effectively demodulated or not. The input signal should not saturate. In frequency domain, spurious signals appear as spikes at different discrete frequencies. SFDR depends on the sampling rate, analog input frequency, and analog input amplitude. By reducing the input amplitude of the signal below the full scale value the SFDR can be optimized.
TABLE III. DAC S
Manufacturer Maxim Analog Devices Analog Devices Texas Instruments Texas Instruments Analog Devices Analog Devices Analog Devices Intersil Intersil
AND THEIR SPECIFICATIONS

SNR 20log 10(2 f i n t jtr ) ,

where fin represents the analog input frequency and tjtr the RMS value of the systems jitter. This implies SNR of the system is affected by analog input frequency. D. Spurious Free Dynamic Range Spurious Free Dynamic Range is another key specification of ADC. Figure 2 illustrates the same. It characterizes the linearity of an ADC. It is the ratio of between the amplitude of the analog input signals fundamental frequency and highestamplitude spurious signal. SFDR becomes critical in 2013 ACEEE DOI: 03.LSCS.2013.2. 93 59

DAC MAX5879 AD9778 AD9744 DAC3482 DAC 5672 AD9957 AD9755 AD9739 ISL5961 ISL5929

Resolution 14 bit 14 bit 14 bit 16 bit 14 bit 14 bit 14 bit 14 bit 14 bit 14 bit

Update rate 2.3GSPS 1GSPS 210MSPS 1.2GSPS 275MSPS 1GSPS 300MSPS 2.5GSPS 210MSPS 210MSPS

Poster Paper Proc. of Int. Conf. on Advances in Information Technology and Mobile Communication 2013 III. KEY SPECIFICATIONS OF DAC The key specifications of DAC are Noise power spectral density (NSD), Adjacent-channel leakage ratio (ACLR) or adjacent-channel power ratio (ACPR). DAC must be able to synthesis higher frequencies. In-band and quadrature signals are added and then fed to DAC. So there is a higher bandwidth requirement of DAC for better performance of transmitter. Adjacent Channel Leakage Ratio is defined as the ratio of the power in the desired carrier band to the power in an adjacent carrier band. The specification covers the first two adjacent bands, and is measured on both sides of the desired carrier. For perfect transmission the spurious products need to be about -75dBFS. Noise is a major concern in a DAC. SDR application is wideband in nature. As the signal from DAC is applied to power amplifier, noise from DAC also passes through the power amplifier. This excess noise when passed through antenna gets converted into RF noise. So output noise density from DAC must be as minimal as possible. DACs provided by different vendors have better output density. Spurious Free Dynamic Range of a DAC is the usable dynamic range of a DAC before spurious noise interferes with the fundamental signal. SFDR is the measure of the difference in amplitude between the fundamental and the largest harmonically or non-harmonically related spur from DC to the full Nyquist bandwidth. SFDR over full Nyquist bandwidth and band of interest of application has to be specified. Selecting a low glitch, linear converter helps to significantly reduce spurs. IV. OTHER FEATURES Integration plays a very important role in enhancement of performance. Converters with digital filters, interpolators, decimators, NCOs also help in transceiver action. In recent years the converters with above digital functions are available in the market. An NCO in a DAC with interpolation translates the baseband signal to anywhere in the Nyquist band of interpolated sample rate. Similarly in ADC an on-chip NCO with decimator converts the IF signal to baseband signal. Another Benefit of on-chip decimators in ADCs and interpolators in DACs is it lowers the external interface speed which reduces the switching speed requirements by just allowing to use slower logic families which in turn lowers the overall noise and spurious generated in data converters. So with the evolution of high performance converters with levels of integration improves the performance of SDR systems. V. DATA CONVERTERS IN SDR A. Analog to Digital converters For meeting todays radio requirements 12 or 14 bit ADCs are sufficient and sampling rate > 100 MSPS is preferred. Table II presents the ADCs used in various SDR platforms and their key specifications[3] , [6] . National Semiconductors [9] ADC12Dxx00RF ADCs provide sampling rate from 1.0 to 3.6GSPS. They are 12-bit ADCs 2013 ACEEE DOI: 03.LSCS.2013.2.93 60 with five sampling rates viz., 1.0, 1.6, 2.0, 3.2, and 3.6 G samples/ s. They are dual channel ADCs with completely independent signal chains. It can be operated in interleave mode to implement alternate sample of each channel. The best feature of these ADCs is that they eliminate the requirement of multiple IF stages. By limiting the hardware implementation of these IF stages bill of material cost, board size, weight and power consumption reduces drastically. Elimination of Local oscillators reduces the effect of interference. The 3.6-Gsample/ s device boasts third-order intermodulation distortion (IMD3) of -71 dBc at 2.7 GHz with an amazing noise floor of -152.2 dBm/Hz. To meet the SDR need for superior performance to recover data with very high sensitivity from multiple channel, wideband input RF applications and frequency flexibility Texas Instruments has introduced 1GSPS ADCs, ADC12D1800/ 1600/1000, which are of 12-bit resolution. Texas Instruments [10] also manufactures dual channel 12-bit and 14-bit ADS61xx series. It provides a sampling rate of 250MSPS. Its high dynamic performance and low power consumption makes it suitable for multicarrier, wide bandwidth communications applications like SDR. Linear Technologys [11] 16-bit LTC2208 provides sampling rate of 130MSPS.It digitizes wide range of signals with input bandwidth up to 700MHz. PGA can be used to optimize the input signal. It has 78dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). B. Digital to Analog Converters A 14- bit resolution DAC is preferred to meet the radio requirements. Table III presents some of DACs suitable for SDR design. [5] Maxims MAX5879 RF DAC [12] works with FPGA-based direct digital synthesizer and shifts the analog implementation into digital domain. This eliminates the use of analog local oscillators and in turn the in phase and quadrature phase errors. This simplifies the RF design and improves the transmitter performance. A single MAX5879 RF DAC serves many wireless standards without giving up the dynamic performance. Texas Instruments DAC5688 is dualchannel, 16-bit, 800-MSPS, digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), onboard clock multiplier, IQ compensation, and internal voltage reference. It can be operated in different modes. It allows both complex and real outputs. Input data of DAC5688 can be interpolated by onboard digital interpolator. An additional 32-bit NCO in complex mode provides frequency up conversion and the dual DAC output form the Hilbert transform pair. A digital inverse sinc filter is also present. The digital Quadrature Modulator Correction (QMC) feature permits IQ compensation of phase, gain, and offset to maximize sideband rejection and minimize LO feed through of an external quadrature modulator performing the final single sideband RF up conversion. The DAC5688 provides many different modes of operation. Single-sideband mode provides an alternative interface to the analog

Poster Paper Proc. of Int. Conf. on Advances in Information Technology and Mobile Communication 2013 quadrature modulators. Channel carrier selection is performed at baseband by mixing in the ASIC/DUC. Baseband I and Q from the ASIC/DUC are input to the DAC5688, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of the DAC5688s two DACs. An external RF quadrature modulator then performs the final single-sideband up-conversion. The DAC5-688s complex mixing frequencies are flexibly chosen with the 32-bit programmable NCO. In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex mixing in the ASIC/DUC. Baseband I and Q from the ASIC/FPGA are input to the DAC5688, which interpolates the low data-rate signal to higher data rates. The DAC output from the DAC5688 is the final IF single-sideband spectrum presented to RF. [4] VI. SIMULATION RESULTS In this section the performance characteristics of 14-bit ADC with 250MSPS sampling rate is presented. The simulations are performed in online tool ADI sim ADC. Input signal frequency is taken as 2.23MHz.The characteristics are shown in Figure 3. The simulation in Matlab by considering only quantization noise for 14-bit ADC of 250MSPS sampling rate is as shown in Figure 4. VII. CONCLUSION The selection of suitable data converter is the key aspect in the design of software defined radio. Because of advancement in the field of high speed data converters many wide band ADCs are available in todays market. With the familiarity of latest offerings from different vendors and based on application one can choose correct data converter for accomplishing the design of SDR.

Figure 4: FFT output of 14 bit ADC [Matlab result]

REFERENCES
[1] Y. Papantonopoulos, High-speed adc technology paves the way for software defined radio, 2008. [2] B. Kraemer, Data conversion considerations for software radios, in Spread Spectrum Techniques and Applications, 1998. Proceedings., 1998 IEEE 5th International Symposium on, vol. 2. IEEE, 1998, pp. 546 550. [3] Analog devces website[online], http://www.analog. com/en/ index.html. [4] Texas instruments website[online], http://www.ti.com/ product/ads62p45. [5]Intersil website[online], http://www.intersil.co m/en/products/ data-converters/d-a-converters/d-a-converters/ISL5961.html [6 ]Altera website [online], http://www.altera.com/li terature/wp/wp- 01026.pdf. [7] N. Vun and A. Premkumar, Adc systems for sdr digital frontend, in Consumer Electronics, 2005.(ISCE 2005). Proceedings of the Ninth International Symposium on. IEEE, 2005, pp. 359363. [8] B. Brannon, Converter performance approaches softwar edefined radio requirements, RF DESIGN, vol. 30, no. 4, p. 40, 2007. [9] Website[online],http://www.bdtic.com/DataSheet /NSC/ ADC12DS105.pdf [10] Texas instruments website[online], http://www.ti.com/ solution/software-defined-radio-sd r-diagram. [11] Linear technology website[online], http://cds.linear.com/ docs/Datasheet/2208fc.pdf. [12] P. OSCILLATORS, Wideband rf channel simulator, IEEE Communications Magazine, p. 16, 2012

Figure 3 FFT output of 14 bit ADC. [Data generated from ADIsimADC]

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