UNIT - 2 ADDRESSING METHODS AND INSTRUCTION EXECUTION STRUCTURE

2.0 Introduction 2.1 Objectives 2.2 Main memory addresses and operations 2.3 Machine operations and instruction formats 2.4 Addressing methods 2. !ummary 2." #uestions

2.0 INTRODUCTION
$nit %1 introduced the genera& concepts re&ated to computer organi'ation and the (ay a computer is made operationa&. In this unit) (e sha&& see ho( memory &ocations and *+$ registers are addressed and the (ay in (hich se,uences of instructions are brought from the main memory into the *+$) e-ecuted to perform a given tas. using a genera&/purpose machine.

2.1 OBJECTIVES
At the end of this unit) you shou&d be ab&e to 0efine (ord) (ord &ength) memory address) instruction 1-p&ain instruction fetch and instruction e-ecution Identify various instruction formats) instruction groups $se different addressing techni,ues

2.2 MAIN MEMORY ADDRESSES AND OPERATIONS

2he main memory consists of a &arge number of storage ce&&s) each of (hich can store a binary digit 0 or 1. 2his 1/bit representation of information is too sma&& to be hand&ed by a computer. !o) a group of n bits are used (hi&e storing or retrieving. 1ach group of n bits is referred to as its (ord &ength. 2he (ord &ength can be 3 bits) 1" bits) 32) "4 or 123 bits depending on the si'e of the computer. 2he main memory organi'ation is sho(n in fig 2.1. Figur 2.1 Main memory address Address 0 1 i bn/155..b0 m/1 4ord m/1 n bits 4ord i contents 4ord 0 4ord 1

1ach &ocation in the main memory is given a distinct name or address. 4ith this address it is possib&e to store or retrieve information from the memory &ocation. 2he contents of memory &ocations can represent either instructions or operands. 2he operands can be numbers or characters.

6etch 7or 8ead9 and !tore 7or 4rite9 are the basic operations used for moving the operands and resu&ts bet(een main memory and the *+$. 2he 6etch operation transfers the contents of a specific memory &ocation to the *+$. :ut) the (ord in the main memory remains unchanged. 2he !tore operation transfers a (ord of information from the *+$ to a specific main memory &ocation destroying the origina& contents of that &ocation.

2.! MACHINE OPERATIONS " INSTRUCTION FORMATS

An instruction is nothing but an e-p&icit command to processor to do some specified tas.. A group of instructions that a specific processor can e-ecute is ca&&ed its i#$%ru&%i'# $ %. 2he number of instructions in an instruction set depends on the architecture and the intended use of processors.

C(ASSIFICATION OF INSTRUCTIONS)

D*%* %r*#$+ r i#$%ru&%i'#$

!ome e-amp&es of data transfer instructions inc&ude &oad) store) move) input) output 2hese instructions are used for transferring the data from one &ocation to another. 2he &ocation can be a memory &ocation) registers in the *+$ or I;O sub system.

Ari%,- %i& *#. /'gi& i#$%ru&%i'#$

!ome e-amp&es of arithmetic instructions inc&ude add) subtract) mu&tip&y) divide) increment) decrement 2hese instructions are used for performing arithmetic operations on data.

!ome e-amp&es of &ogic instructions inc&ude A<0) O8) <O2) shift right) shift &eft 2hese instructions are used for performing &ogic operations on data.

Br*#&, i#$%ru&%i'#$
!ome e-amp&es of branch instructions inc&ude branch if 'ero) branch if e,ua&) branch if not e,ua&) unconditiona& branch 2hese instructions are used for program se,uencing and contro&.

Mi$& //*# 'u$ i#$%ru&%i'#$

!ome e-amp&es inc&ude <o operation) +ush) +op) 4ait) =a&t) 1nab&e interrupt) 0isab&e interrupt.

INSTRUCTION FORMATS )
2his specifies the fo&&o(ing (ith respect a machine &i.e the operations to be performed) &ocation of the operands) p&ace to store the resu&t) &ocation or address of the ne-t instruction to be e-ecuted. 2here are si- different types of instruction formats in a computer) name&y 1. 6our / address instruction format 2. 2hree /address instruction format 3. 2(o / address instruction format 4. One / address instruction format . >ero /address instruction format ". One /and/ ha&f address instruction format ?et us consider a hypothetica& machine (ith 24/bit memory addresses and 123 instructions for our discussion@ 1. T, +'ur-*..r $$ i#$%ru&%i'# +'r-*% ) 2his instruction format consists of four addresses a&ong (ith an operation fie&d. 2he four addresses inc&ude the address of the first operand) address of the second operand) address to store the resu&t and the address of the ne-t

instruction. 2he figure 2.2 sho(s the four/address machine operation and instruction format Fig 2.2 the four/address machine operation and instruction format

*+$ O+1Addr@ O+2Addr@ 81!Addr@

O+1 O+2 81!

<e-tiAddr

<e-ti

add) 81!) O+1) O+2) <e-ti

I#$%ru&%i'# +'r-*% :its@ 3 add 24 RESAddr 24 OP1Addr 24 OP2Addr 24 NextiAddr

$sing this machine) a9 the number of bytes re,uired to encode an instruction is 13 bytes. i.e. each address re,uires 24 bits A 3 bytes. !ince there are 4 addresses and one operation code fie&d ) 4 B 3 C 1 A 13 bytes b9 the number of memory access re,uired is 3 (ords i.e. memory. (ords for instruction fetch C 2 (ords for operand fetch C 1 (ord for resu&t to be p&aced bac. in

2. T, %,r

-*..r $$ i#$%ru&%i'# +'r-*% )

2his instruction format consists of three addresses a&ong (ith an operation fie&d. 2he three addresses inc&ude the address of the first operand) address of the second operand) address to store the resu&t . 2he address of the ne-t instruction is he&d in a *+$ register ca&&ed program counter 7+*9. 2he +igur 2.! sho(s the three/address machine operation and instruction format

*+$ O+1Addr@ O+2Addr@ 81!Addr@

O+1 O+2 81! +*

24 bits

<e-tiAddr

<e-ti add) 81!) O+1) O+2

I#$%ru&%i'# +'r-*%) :its 3 add 24 RESAddr 24 OP1Addr 24 OP2Addr

$sing this machine) a9 the number of bytes re,uired to encode an instruction is 10 bytes. i.e. each address re,uires 24 bits A 3 bytes. !ince there are 3 addresses and one operation code fie&d ) 3 B 3 C 1 A 10 bytes b9 the number of memory access re,uired is D (ords i.e. 4 (ords for instruction fetch C 2 (ords for operand fetch C 1 (ord for resu&t to be p&aced bac. in memory.

3. T, %0'-*..r $$ i#$%ru&%i'# +'r-*% ) 2his instruction format consists of t(o addresses a&ong (ith an operation fie&d. 2he t(o addresses inc&ude the address of the first operand) address of the second operand) 7+*9. 2he +igur 2.1 sho(s the t(o/address machine operation and instruction format the resu&t is stored in one of the operand address . 2he address of the ne-t instruction is he&d in a *+$ register ca&&ed program counter

*+$ O+1Addr@ O+2Addr@

O+1 O+2 ) 81!

24 bits

+*

<e-tiAddr

<e-ti add) O+2) O+1

I#$%ru&%i'# +'r-*%) :its 3 add 24 OP2Addr 24 OP1Addr

$sing this machine) a9 the number of bytes re,uired to encode an instruction is D bytes. i.e. each address re,uires 24 bits A 3 bytes. !ince there are 2 addresses and one operation code fie&d ) 2 B 3 C 1 A D bytes

b9 the number of memory access re,uired is " (ords i.e. 3 (ords for instruction fetch C 2 (ords for operand fetch C 1 (ord for resu&t to be p&aced bac. in memory. 4. T, '# -*..r $$ i#$%ru&%i'# +'r-*% ) 2his instruction format consists of one address a&ong (ith an operation fie&d. 2he address is that of the first operand. 2he second operand) and the resu&t are stored in a *+$ register ca&&ed *&&u-u/*%'r . 2he address of the ne-t instruction is he&d in a *+$ register ca&&ed 2r'gr*- &'u#% r 7+*9. :ecause a machine has on&y one accumu&ator) it need not be e-p&icit&y mentioned in the instruction. 2he +igur 2.3 sho(s the one/address machine operation and instruction format

*+$ O+1Addr@

O+1

accumu&ator
<e-tiAddr

<e-ti

+*
24 bits

I#$%ru&%i'# +'r-*%) :its 3 add 24 OP1Addr

add O+1

2his machine re,uires e-tra 2 instructions to &oad and store the accumu&ator contents

$sing this machine) a9 the number of bytes re,uired to encode an instruction is 4 bytes. i.e. each address re,uires 24 bits A 3 bytes. !ince there on&y 1 address and one operation code fie&d ) 1 B 3 C 1 A 4 bytes b9 the number of memory access re,uired is 3 (ords i.e. 2 (ords for instruction fetch C 1 (ords for operand fetch 3. 4 r' -*..r $$ i#$%ru&%i'# +'r-*% ) A $%*&5 is inc&uded in the *+$ for performing arithmetic and &ogic instructions (ith no addresses. 2he operands are pushed onto the stac. from memory and A?$ operations are imp&icit&y performed on the top e&ements of the stac.. . 2he address of the ne-t instruction is he&d in a *+$ register ca&&ed 2r'gr*- &'u#% r 7+*9. I#$%ru&%i'# +'r-*%) :its 3 opcode

1g. add 2op of stac. A top of stac. C second top of stac. $sing this machine) a9 the number of bytes re,uired to encode an instruction is 1 byte. !ince there is on&y 1 operation code fie&d 6. O# *#. ,*/+-*..r $$ i#$%ru&%i'# +'r-*% ) An instruction that specifies one operand in memory and one operand in a *+$ register is referred to as one/and/ha&f address instruction.

$sing registers it is possib&e to increase the speed of processing because) registers are fe( in number in comparison (ith memory &ocations and hence need &ess time to access it. 4e (i&& assume that there are 32 genera&/purpose registers in the machine. so) bits are re,uired to address a register. I#$%ru&%i'# +'r-*%) :its D Opcode 8egAddr 24 O+1Addr

1g. &oad 83) O+1 E $sing this machine)

O+1 contents is moved to register 83

a9 the number of bits re,uired to encode an instruction is 3" bits. i.e. each address re,uires 24 bits. !ince there on&y register address operation code fie&d ) 1 B 24 C C D A 3" bits bits and one

b9 the number of memory access re,uired is 3 (ords i.e. 2 (ords for instruction fetch C 1 (ords for operand fetch NOTE ) machines become faster (ith sma&&er instruction formats.

2.1

ADDRESSING METHODS

2he methods used to provide an access path to operands in memory and *+$ registers is addressing mode. 2he address generated by the *+$ in/order to access the operand in the memory is termed as an ++ &%i7 *..r $$.

ADDRESSING MODES)
direct addressing indirect addressing immediate addressing register direct addressing register indirect addressing inde- addressing re&ative addressing

Dir &% *..r $$i#g ) 2he address of the operand is e-p&icit&y given as a part of the instruction. 1-amp&e@ A00 100 2his instruction causes the *+$ to add the contents of memory &ocation 100 to the contents of the accumu&ator. i.e. A** FA** GC F100G !uppose) accumu&ator contains 10) memory &ocation 100 contains 1 0 then the resu&t of e-ecuting this instruction is 10 C 1 0 A 1"0 stored in the accumu&ator. I#.ir &% *..r $$i#g ) 2he instruction contains address of address of operand. 1-amp&e @ A00 H 100 E H indicates indirect addressing 2his instruction causes the *+$ to add the contents of contents of memory &ocation 100 to the contents of the accumu&ator. i.e. A** FA**G C F F100G G !uppose) accumu&ator contains 10) memory &ocation 100 contains 1 0 ) this va&ue 1 0 is treated as an address that contains operand 10. 2hen the resu&t of e-ecuting this instruction is 20 stored in the accumu&ator. i.e. 710 C F F100G G A 10 C F1 0G A 10 C 10 A 20 9 I-- .i*% *..r $$i#g ) In this mode) the actua& data is a part of the instruction. 1-amp&e @ A00 I 100 E I indicates immediate mode

2his instruction causes the *+$ to add the data 100 to the contents of the accumu&ator. i.e. A** FA**G C 100 !uppose) accumu&ator contains 10) then the resu&t of e-ecuting this instruction is 110 stored in the accumu&ator. 7i.e. 10 C 100 A 110 9 R gi$% r .ir &% *..r $$i#g ) 2his is same as direct addressing e-cept that the address is that of a register instead of a memory &ocation. 1-amp&e @ A00 81 2his instruction causes the *+$ to add the contents of the accumu&ator to the contents of the register 81 i.e. A** FA**G C F 81 G !uppose) accumu&ator contains 10) register 81 contains 0 then the resu&t of e-ecuting this instruction is "0 stored in the accumu&ator. R gi$% r i#.ir &% *..r $$i#g ) 2his is same as indirect addressing e-cept that the address is that of a register instead of a memory &ocation. 1-amp&e @ A00 H 81 2his instruction causes the *+$ to add the contents of the accumu&ator to the contents of contents of the register 81 i.e. A** FA**G C F F 81 G G I#. 8 *..r $$i#g ) 2he effective address of the operand is generated by adding an inde- va&ue to the address given in the instruction. 2he inde- va&ue is he&d a register ca&&ed inde- register. 1-amp&e @ ?oad 4F82G R /*%i7 *..r $$i#g @ 2he effective address of the operand is obtained by adding the contents of the program counter (ith the constant va&ue specified (ith the instruction. 1-amp&e @ ?oadre& 4F+*G

2.3 SUMMARY
2his unit introduced the various instructions) its representation in different formats. 2he emphasis (as on the princip&es of genera& addressing techni,ues. 6urther (ith this) a student can go for a comp&ete and detai&ed description of addressing techni,ues) instruction formats pertaining to any computer.

2.6 9UESTIONS
1. 0efine the fo&&o(ing@ (ord) (ord &ength) memory address) effective address) instruction ) addressing mode 2. =o( is main memory being organi'ed J e-p&ain. 3. =o( are instructions being c&assifiedJ 1-p&ain (ith e-amp&es. 4. *ompare the various instruction formats (ith an e-amp&e. . <ame any t(o addressing modes and high&ight its importance.