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Programming Interfaces
C. Stroud 8/06 FPGAs 1
History
Programmable Logic Arrays ~ 1970
Implement any set of sumsum-of of-products logic equations Incorporated in VLSI devices
AMD 22V10 and Lattice 16V8 Complex PLDs arrays of PLDs with routing network
Programming Technologies
PLAs were mask programmable PALs used fuses for programming Early PLDs & CPLDs used floating gate technology
Erasable Programmable Read Only Memory (EPROM)
Ultra-violet erasable (UVEPROM) UltraElectrically erasable (EEPROM) Flash memory came later and was used for CPLDs
Programming Technologies
RAM
Volatile must configure after powerpower-up InIn -System Re Re-programmable (ISR) RunRun -Time Reconfiguration (RTR)
dynamic reconfiguration while system is operating
Fuse/antiFuse/anti -fuse
Non-volatile but not re Nonre-usable One Time Programmable (OTP)
C. Stroud 8/06 FPGAs 4
PALs
16L8 combinational logic 10 to 16 inputs, each with true and complement signal 2 to 8 outputs, each with
7 product terms can AND any of up to 16 inputs or their complements TriTri-state control product term for inverting output buffer When output in tritri-state, I/O pin can be used as input
High impedance output with no signal driven
C. Stroud 8/06
FPGAs
PALs
16R8 sequential logic 8 inputs, each with true & complement 8 outputs, each with D flipflip-flop
With feedback for FSMs
One clock for all FFs One tritri-state control for all outputs
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PLDs
22V10 replaced all PALs Combinational and/or sequential logic
Macrocell program bits C0, C1
Global
preset & clear PTs clock
C. Stroud 8/06
FPGAs
C. Stroud 8/06
FPGAs
CPLDs
Cypress Semiconductor 374 CPLD Architecture 84-pin package w/~6 Vcc and 8 Gnd pins 36 inputs to AND-plane w/84 PTs and partially programmable OR-plane
C. Stroud 8/06
FPGAs
CPLDs
An array of PLDs
Global routing resources for connections
PLDs to other PLDs PLDs to/from I/O pins
I/O Block I/O Block
GCLK[3:0]
I/O Block
I/O Block
LB LB LB LB
8192 bit RAM
LB LB
PIM
LB LB
8192 bit RAM
LB LB LB LB
8192 bit RAM
LB LB
PIM
LB LB
8192 bit RAM
LB LB LB LB
8192 bit RAM
LB LB
PIM
LB LB
8192 bit RAM
Each Logic Block (LB) similar to a 22V10 Each cluster of 8 LBs has two 8K RAMs & one 4K dualdual-port RAM/FIFO
Programmable Interconnect Modules (PIMs) provide interconnections
GCLK[3:0]
LB LB LB LB
8192 bit RAM
LB
PIM
LB
4096 bit RAM Dual-Port FIFO
LB
PIM
LB
4096 bit RAM Dual-Port FIFO
LB
PIM
LB LB LB
8192 bit RAM
LB LB LB
8192 bit RAM
LB LB LB
8192 bit RAM
LB LB LB
8192 bit RAM
LB LB LB
8192 bit RAM
I/O Block
I/O Block
4 4 PLLs &Clock Mux
I/O Block
GCLK[3:0] CNTL[3:0]
I/O Block
FPGAs
10
I/O Block
I/O Block
Ranges of Resources
FPGA Resource Logic Routing Specialized Cores Other
PLBs per FPGA LUTs and flipflip-flops per PLB Wire segments per PLB PIPs per PLB Bits per memory core Memory cores per FPGA DSP cores Input/output cells Configuration memory bits
Small FPGA Large FPGA 256 1 45 139 128 16 0 62 42,104 25,920 8 406 3,462 36,864 576 512 1,200 79,704,832
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FPGAs
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LUT/ RAM
Flip-flop/ Latch
Output Q output
carry in
FPGAs 12
A Simple PLB
Two 33-input LUTs
Can implement any 4-input combinational logic function
1 flipflip-flop
Programmable:
Active levels Clock edge D2-0 Set/reset
3 LUT C 8x1 LUT S 8x1 CB5 D2-0 LUT
C7
C6
C5
C4
C3
C2
C1
C0
111 110 101 100 011 010 001 000 out Cout
6 controls
CB0CB0 -7
C. Stroud 8/06 CB0 CB1 FPGAs CB2
CB
A S Z B Truth table SAB Z 000 0 001 0 010 1 011 1 100 0 101 1 110 0 111 1
Logic symbol A B 0 S1
0 1
14
Multiplexer 0 0 1 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 1 0 1
A B S
0 1
Z 1
Truth table SAB Z 000 0 001 0 010 1 011 1 100 0 101 1 110 0 111 1
1 B
FPGAs
0 A S
15
0 0 1 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 1 0 1
In0
In1
In2
16
Interconnect Network
Wire segments of varying length
xN = N PLBs in length
1, 2, 4, and 6 are most common
Transmission gate connects to 2 wire segments Controlled by configuration memory bit Wire A
0 = wires disconnected 1 = wires connected
C. Stroud 8/06 FPGAs
PIPs
BreakBreak -point PIP
Connect or isolate 2 wire segments
Multiplexer PIP
Directional and buffered Select 11-of of-N inputs for output
Decoded MUX PIP N config bits select from 2N inputs NonNon -decoded MUX PIP 1 config bit per input
FPGAs
Recent trend - incorporate specialized cores
RAMs single single-port, dual dual-port, FIFOs
128 bits to 36K bits per RAM 4 to 575 per FPGA
FPGA Architectures
4000/Spartan
NxN array of unit cells Unit cell = CLB + routing
Special routing along center axes
Virtex/SpartanVirtex/Spartan -2
MxN array of unit cells Added block 4K RAMs at edges
PC PC
VirtexVirtex -2/Spartan2/Spartan-3
Block 18K RAMs in array Added 18x18 multipliers with each RAM Added PowerPCs in VirtexVirtex-2 Pro
PC
VirtexVirtex -4/Virtex4/Virtex-5
Added 4848-bit DSP cores w/multipliers I/O cells along columns for BGA
C. Stroud 9/07 FPGAs
PC
21
RAMs/multipliers
250 300 350 400 450 100 150 200 50 0
C. Stroud 8/06
Specialized Cores
FPGAs 22
2S15 2S30 2S50 2S100 2S150 2S200 V50 V100 V150 V200 V300 V400 V600 V800 V1000 3S50 3S200 3S400 3S1000 3S1500 3S2000 3S4000 3S5000 2V40 2V80 2V250 2V500 2V1000 2V1500 2V2000 2V3000 2V4000 2V6000 2V8000 2VP2 2VP4 2VP7 2VP20 2VPX20 2VP30 2VP40 2VP50 2VP70 2VPX70 2VP100
Programmable RAMs
18 Kbit dualdual-port RAM Each port independently configurable as
512 words x 36 bits
32 data bits + 4 parity bits
1K words x 18 bits
16 data bits + 2 parity bits
2K words x 9 bits
8 data bits + 1 parity bit
4K words x 4 bits (no parity) 8K words x 2 bits (no parity) 16K words x 1 bit (no parity)
clock edge active levels for write enable, RAM enable, reset
FPGAs
23
Cores
100 200 300 400 500 600 0 4VLX15 4VLX25 4VLX40 4VLX60 4VLX80 4VLX100 4VLX160
C. Stroud 8/06
Specialized Cores
FPGAs
4VLX200
Virtex 4
4VSX25 4VSX35 4VSX55 4VFX12 4VFX20 4VFX40 4VFX60 4VFX100 4VFX140
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Frame addressable
Vertical or horizontal frame Access to all PLBs in frame
Only portion of logic and routing resources accessible in a given frame Many frames to configure PLBs
Major address for column, minor address for frame
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Day #1
Frame Length
26
X C 3 S 4 0 0 0 X C 3 S 5 0 0 0
80
70
60
Number of Frames
50
40
30
20
10
Day #1
27
VirtexVirtex -4 Architectures
PowerPC location
Day #1
28
Tile coordinates
FPGAs
29
Configuration Memory
Frame order
CLBs, IOBs, DSPs, & center column form main portion BRAMs come after
XN+1 XN+2 XN+3 XN+N
Total frames/column
CLBs = 22 frames DSPs = 21 columns Center column = 33 frames IOBs = 30 frames
Left & right cols in LX & SX
(2X+1)N +1
(2X+1)N +2
(2X+1)N +3
(2X+1)N +N
N = # columns X = (# rows/16)rows/16)-1
30
VirtexVirtex -5 Architectures
Similar architecture, frame structure and order
I/O cells not along outside column on right side Center column (Xs) not in center of array
More columns to right side of center column
Similar top/bottom and config row format 41 words (32(32-bit) per frame
Hamming bits in middle word of frame
part #rows 30 80 50 120 85 120 110 160 220 160 330 240 35 50 95 LX & LXT Legend O 4 R2D 8 X 8 R 4 O 4 TC #=#CLBcols O 4 R2D 8 X 8 R 4 O 4 TC D=DSPs O 4 R 10 R 2 D 8 X 12 R 10 R 4 O 4 T C R=RAMs O 4 R 10 R 2 D 8 X 12 R 10 R 4 O 4 T C O=I/O cells O 4 R 22 R 2 D 2 D 2 R 20 X 20 R 6 R 22 R 4 O 4 T C X=IO&DCM O 4 R 22 R 2 D 2 D 2 R 20 X 20 R 6 R 22 R 4 O 4 T C T/C=T only SXT 80 O4R2D2D 2 R2D 2 D2R 2 X 2 R 2 D 2 D 2 R 4O4 TC 120 O4R2D2D 2 R2D 2 D2R 2 X 2 R 2 D 2 D 2 R 4O4 TC O4R2D2D2R2D2D 2 R2D 2 D2R 2 X 2 R 2 D 2 D 2 R 2 D 2D2R4O4TC 160
FPGAs 31
C. Stroud 9/07
VirtexVirtex -5 FX30T
5,120 slices
4 FFs & 66-input LUTs
68 DPRAMs/FIFOs
36Kbits
64 DSPs
24x18 mult & 4848-bit ALU
Frame addressable
Vertical or horizontal frame Access to all PLBs in frame
Only portion of logic and routing resources accessible in a given frame Many frames to configure PLBs
C. Stroud 8/06 FPGAs
Hybrid i.e.: Virtex-4 Virtex-5 Major address for column, minor address for frame Virtex-6
33
Tile coordinates
FPGAs
34
Master FPGA retrieves its own configuration from ROM after powerpower-up
clock CCLK CCLK
Configuration Interfaces
PROM with Configuration Data
data out
CCLK
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FPGAs
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FPGAs
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Master mode
Configuration sequence during powerpower -up of device
Typically from Serial EPROM Master Serial Parallel EPROM Master Parallel 8-bit 3232 -bit
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FPGAs
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FPGAs
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FPGAs
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Configuration Techniques
Full configuration & readback
Simple configuration interface Internal automatic calculation of frame address Long download time for large FPGAs
Configuration Techniques
Compressed configuration
Requires multiple frame write capability
Write identical frames of config data to multiple frame addresses
C. Stroud 9/07
FPGAs
42
FPGAs
Xilinx ASCII Bitstream Created by Bitstream I.32 Design name: s3mod7.ncd Architecture: spartan3 Part: 3s50tq144 Date: Tue Sep 04 15:50:09 2007 Bits: 439264 11111111111111111111111111111111 10101010100110010101010101100110 00110000000000001000000000000001 00000000000000000000000000000111 00110000000000010110000000000001 00000000000000000000000000100100 00110000000000010010000000000001 01000000000000000011111111100101 00110000000000011100000000000001 00000001010000001101000010010011 00110000000000001100000000000001 00000000000000000000000000000000 00110000000000001000000000000001 00000000000000000000000000001001 00110000000000000010000000000001 00000000000000000000000000000000 00110000000000001000000000000001 00000000000000000000000000000001 00110000000000000100000000000000 01010000000000000011010101010101 43 start of actual configuration data