EE241 - Spring 2008

Advanced Digital Integrated Circuits

Lecture 9: Variability, Introduction to SRAM

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Homework 1
Due February 26 Warning: Long!

Agenda
More on variability Intro to SRAM

Design Variability

Sources and Impact on Design

Chip Yield Depends on Inter-Path Correlation

Mean delay increases as K increases for uncorrelated paths
D D

K uncorrelated paths

a1

b2

c1

aP

bP

cP

Normalized PDF

K =1 K =2 K =10000

0 0.8

0.9 1 1.1 1.2 Normalized Critical Path Delay y Max delay of P paths

Yield = Pr (max delay of K paths < clock period) K = 1 gives highest yield
Correlated paths reduce impact of variation
Bowman et al, JSSC, Feb 2002 .

Chip Yield Depends on Inter-Gate Correlation

Variation remains constant with correlated gates, = 1
20%

/mean of total delay

n stages
D D

15%

Variation is reduced with non-correlated gates, = 0

d1

d2

dn

10%

5%

1 / n
0% 0 2 4 6 8 10

Yield = Pr (sum of n delays < clock period) = 0 gives highest yield through increased averaging

Number of stages (n)

Non-correlated gates in a path reduce impact of variation

Corners

Within wafer Within die

Slow

Typical

Fast

Technology Variability
Lithography Dopants Line edge roughness Film thicknesses NBTI

Optical Lithography

i193 (immer.) =193nm

Step-and-Scan Lithography

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Sub-Wavelength Lithography
CD = k1
Decrease
Presently: 193 nm (ArF excimer laser) (Very) Distant Future: EUV

NA

Increase NA
Presently: ~0.92-1.2 Immersion

Result: Shrinking k1
Presently: 0.35 0.4 Theoretical Limit: 0.25
From Strojwas, CMU

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Printability Issues

Source: Liebmann, IBM, ISPD-2003

Sensitive to exposure and defocus Highly neighborhood dependent Strong RETs are necessary @ k1 << 0.5
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Sub-Wavelength Lithography
Depth Of Focus (DOF)
The amount by which the distance between lens and wafer can be varied without adversely affecting image quality

DOF = k 2

(NA)2

Larger DOF desired Affected bandwidth, tilt, movement Aff t d by b laser l b d idth stage t tilt stage t t Stringent requirement on wafer planarity

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Lithography: Density Effects

Isolated Dense Masks

Ldense Liso

Resist exposure threshold

Brunner, ICP2003

Denser features: More accurate line width and less variation. Dense lines are wider than isolated lines.

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Lithography: Optics
Defocus Lens aberrations:
Spherical aberrations Astigmatism Coma

Spherical aberrations - affect the reticle-level features

Stepper dependent

Coma affects individual features

Chip-location dependent 15

Lens Aberrations Coma Effect

Coma effect: optical aberration due to lens imperfection. Causes mirrored structures to display non equivalent properties S t ti shift hift between b t th 2 layouts l t Systematic the
Image of a circular dot shows a tail

prints differently from

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Step-and-Scan Lithography
Slit direction:
Lens aberration in the slit CDs more correlated
Light source Mask Slit of light Mask moved to the right

Scan direction:
Dosage, scan speed and other fluctuations CDs less correlated scan slit

Optics

Wafer

Wafer moved to the left

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Lithography: Flare
Light scattering and reflections More stray light under dark features in the mask
Local flare depends on the density of chrome in the mask
Surface scattering

Intensity CD Resist exposure threshold

Reflections Lens

With flare No flare

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Line-Edge Roughness

Sources of line-edge roughness: Fluctuations in the total dose due to quantization Resist composition Absorption positions Effect: Variation (random) in leakage and power
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Random Dopant Fluctuations

Number of dopants is finite

Frank, IBM J R&D 2002 20

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Random Dopant Fluctuations

Lg = 17nm, VDS = 0.7V

Lg = 11nm, VDS = 0.7V

VT = 23mV

VT = 52mV

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Oxide Thickness
Systematic variations + Roughness in the Si./SiO2 interface S ll effect ff t th Smaller than RDF

Asenov, TED2002
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Negative Bias Temperature Instability

PFET VThs shift in time, at high negative bias and elevated temperatures The mechanism is thought to be the breaking of hydrogen-silicon bonds at the Si/SiO2 interface, creating surface traps and injecting positive hydrogen-related species into the oxide. Also other charge trapping and hotcarrier defect generation Systematic + random shifts

Tsujikawa, IRPS2003

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SRAM

Scaling trends Design for yield

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SRAM Scaling Trends

100

10

SRAM Cell Size (um )

SRAM Cell Size (um )

ITRS Single Cell Reported Individual Cell Reported Cell in Array

ITRS Effective Cell Reported Effective Cell

10

0.5x effective cell area scaling difficult

0.1 300 200 100 90 80 70 60 50 40 30

0.1 700 600 500 400 300 200 100 10090 80 70 60 50 40 30

T h l Technology N Node d ( (nm) )

T h l Technology N Node d ( (nm) )

Individual SRAM cell area able to track ITRS guideline Array area deviates from ITRS guideline at 90nm Memory design no longer sits on the 0.5x area scaling trend!

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Memory Scaling
On-Die L3 Cache siz ze (MB)

Server processors
10

It i Itanium Processors Xeon Processors

1 180 160 140 120 100 80 60

Technology gy Node ( (nm) )

Memory latency demands larger last level cache (LLC) Memory is more energy-efficient than logic LLC approaches 50% chip area for desktop and mobile processors LLC approaches 80% chip area for server processors

Vivek De, Intel 2006

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6-T SRAM Cell

Improve CD control by unidirectional poly Relax critical layer patterning requirements Optimizing design rules is key

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SRAM cell design trends

BL BLB V DD
IEDM 02

0.46x1.24m

GND WL

Cell in 90nm (1m2)

Cell in 65nm (0.57m2)

Improve CD control by unidirectional poly Relax critical layer patterning requirements Optimizing design rules is key Shorter bitline enables better cycle time and/or array efficiency Full metal wordline with wider pitch achieves better RC 28

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SRAM Cell Trends

0.242m2 cell in 45nm from TSMC (IEDM07)

0.346m2 cell in 45nm from Intel (IEDM07)

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More SRAM Trends

0.15m2 cell in 32nm from TSMC (IEDM07)

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Ion/Ioff: Cell Read and Leakage

H. Pilo, IEDM 200631

Agenda
SRAM stability metrics Options for scaling
Column assist techniques Migration away from 6T Technology options Departure from SRAM (eDRAM)

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SRAM Cell/Array
Hold stability Read stability Write stability Read current (access time)
Access Transistor
BL M5 M2 Q M1 WL VDD M4 Q M3 BL M6

Pull down

Pull up

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SRAM Design Hold (Retention) Stability

WL VDD PL 1 NL PR AXR

Load

AXL

0 NR

Access NPD
BL BL

Data Retention Leakage

Scaling trend:
Increased gate leakage + degraded ION/IOFF ratio Lower VDD during standby

PMOS load devices must compensate for leakage

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SRAM Cell Mismatch

VTh

1 Cox WL

Due to RDF

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The Data-Retention Voltage (DRV) of SRAM

VDD 0 VDD M5 V1 M1 M3 V2 M2 M4 0 M6 VDD

DRV Condition:
V1 V2 =
Left inverter

V1 V2

, when VDD = DRV

Right inverter

Leakage current

Leakage current

0.4

VTC of SRAM cell inverters

When Vdd scales down to DRV, the voltage transfer curves (VTC) of the internal inverters degrade to such a level that retention static noise margin (SNM) of the SRAM cell reduces to zero.
Qin, ISQED04

0.3

VDD=0.4V

0.2 V =0.18V DD 0.1

VTC1 VTC2

0 0 0.1 0.2 V1 (V) 0.3 0.4

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Monte-Carlo Simulation of DRV Distribution

300 250

Histogram of cell #

200 150 100 50 0 0

50

100

150

200

250

300
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Simulated DRV of 1500 SRAM cells (mV)

Next Lecture
SRAM design techniques

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