Fabrication of Metal Oxide Semiconductor Field Effect Transistors (MOSFET) using self-aligned silicide (SALICIDE) technology

Amir Hassani

Professor: Dr. Mehmet C. Ozturk

1. Abstract MOSFET transistors are the building blocks in semiconductor industries. They can be found everywhere as in RF microelectronic circuits, amplifiers, and digital circuits. In this lab, we fabricated MOSFET transistors as well as some other structures such as MOS capacitors, gated-diodes, and comb-like structures for sheet resistance measurements. For better contact resistance we formed selfaligned silicide (SALICIDE) contacts of Ti by two different annealing steps using rapid thermal annealing (RTA) for C49 and C54 phase formation. We then characterized our devices using sheet resistance, C-V, and current-voltage measurements. Because of an issue introduced to polysilicon layer during deposition process, we then switched to transistor devices fabricated in previous semester. We then characterized them for different Width to Length ratios and tabulated the results for better comparison.

2. Wafer clean Just like every other Si-based device fabrication, we had to clean our doublesided polished wafers to prepare them for process. <100> oriented Phosphorus doped Si wafers which were about 500-550 micrometers thick were cleaned using standard JTBaker wafer clean. The purpose of this process is to remove native oxide layer and all other organic contaminations.

3. Oxide Growth As the second step towards Module 3 device fabrication (MOSFETs, Ring MOSFETs, Capacitors, etc.) we had to grow a thermal oxide layer on our Si wafers. This time, in contrast to Module 2 oxide growth, we used dry oxidation because the targeted oxide layer required to be as high quality and dense as gate oxide in MOSFET fabrication. Dry oxidation has a lower growth rate but on the other hand a higher quality as well as a higher density oxide will be resulted after oxidation. Cleaned wafers were loaded into dry oxide quartz tube for a target oxide thickness of 30 nm. Six wafers were used for our main purpose of device

fabrication and two other wafers were used for oxide thickness monitoring and wet etch tests. Dry oxidation in general, follows the equation below. + Then monitor wafer were measured using Nanospec Nanometrics and measurements results are listed in the Table. 1 below:

Front Back

345 A 334 A

349 A 336 A

348 A 335 A

350 A 340 A

349 A 337 A

Table 1. Oxide Thickness in units of Angstrom for both front and back side.

Based on the above measurements we can see that the average thickness of the oxide is about 23 nm both on the front and back sides of the wafer.

4. Polysilicon deposition In order to deposit polysilicon we used Low Pressure Chemical Vapor Deposition first which resulted in poor polysilicon properties. This was obvious through some random color changes on the poly-deposited wafers and inconsistency in etch tests. As reported by staff, there had also been pressure fluctuations in LPCVD furnace while they attempted for polysilicon deposition. As another option we decided to use a Physical Vapor Deposition method instead of a Chemical Vapor Deposition one. Staff crushed a Si wafer and put them in a graphite crucible and used 4 ebeam evaporation tool. The output power provided by this system is less than the new 6 ebeam tool and this system provided a two wafer option. For polysilicon deposition ebeam chamber, was pumped down to approximately 1.7 10 Torr. A beam current of 56-80 mA was used for polysilicon evaporation at the above mentioned pressure. The deposition rate, controlled by a crystal quartz monitor, was kept at 0.2-0.6 A/sec for a target polysilicon thickness of 200 nm. Then, nanometrics was used to measure the polysilicon thickness and it was recorded to be 220 nm after polysilicon etch. However, because there was no rotation involved in the process during ebeam

evaporation, there was much more thickness non-uniformity of polysilicon layer in comparison to conventional LPCVD poly.

5. Photo Lithography First step In order to define doping areas, we spun 1813 positive photo resist, using headway spinner, on front side of the wafer which already had grown oxide and deposited polysilicon layers on top. Then we baked the photoresist on a hotplate set to 115C for one minute. To pattern the photoresist we used the mask pattern shown in Fig. 1 using a transparency mask and then we exposed the photoresist to UV light for 3.5sec using MA6/BA6 contact aligner. This contact aligner uses 280350 nm light to expose wafers up to 150mm of diameter. You can find detailed description of zones in Fig. 2, 3, 4, and 5 below.

Fig. 1. First Layer mask artwork for Doping. Inside closed shaped = solid.

0.15mm Ring Width FET Poly 2.85mm Width Cap Poly 1.5mm Height

FET Poly

Fig. 2. Zone 1 of the first layer mask artwork for Doping. Inside closed shaped = solid.

0.51mm Width 0.22mm Height 0.01mm Ring Width Cap Poly

Everything else: FET Poly

Fig. 3. Zone 2 of the first layer mask artwork for Doping. Inside closed shaped = solid.

Poly Areas

Fig. 4. Zone 3 of the first layer mask artwork for Doping. Inside closed shaped = solid.

Poly Border = Poly Poly

Border = Poly
Fig. 5. Zone 4 of the first layer mask artwork for Doping. Inside closed shaped = solid.

The patterned photoresist was then developed in MF-319. Fig. 6 shows the schematic diagram of the structure after oxidation, polysilicon deposition, and photoresist development.

Fig. 6. Device structure after resist development.

6. Polysilicon and oxide wet etch After developing photoresist, we wet etched the polysilicon layer in the defined spots using mixture of Nitric acid, ammonium fluoride, and water. The etch time for polysilicon layer was around 1 min. After rinsing the devices using DI water we put them in Buffered Oxide Etch tank for etching the oxide layer underneath. We used BOE with a 10:1 ratio of ammonium fluoride (NH4F) as the buffering agent, and hydrofluoric acid (HF). Etch time was around 1 minute. Concentrated HF (typically 49% HF in water) etches silicon dioxide too quickly and also peels photoresist used in lithographic patterning. Buffered oxide etch is commonly used for more controllable etching. After etching was accomplished, resist was stripped using NMP for 3 minutes. Fig. 7 show the schematic diagrams of the structure after polysilicon/oxide wet etch and photoresist strip.

Fig. 7. Schematic diagram of our structure after poly/oxide wet etch and stripping photoresist.

7. Doping and dopant diffusion P-doped regions were formed using Boron disk doping. Boron disk doping was achieved using Tylan Furnace D2 and GS-126 solid Boron source disks manufactured by Techneglas. Every two wafers were placed between source disks and doping was accomplished at 950C for 3 hours and in a 4000 sccm flow of Nitrogen gas (N2). Then wafers were put in BOE bath for 2 and half minutes to remove the glass layer, 160 nm thick, formed during Boron doping. Fig. 8 shows the schematic structure of device wafers after Boron diffusion and glass etch.

Fig. 8. Schematic diagram of our device structure after Boron diffusion and glass etch.

8. Deposition of second oxide layer We deposited a second oxide layer to define our reactive areas. Reactive areas were the places which we wanted to react with Ti layer and form our self-aligned titanium silicide, TiSi2, contacts which will be described later. For this purpose we used 6 ebeam evaporator. This system is a high power (6keV) system which is equipped and modified with a cooling chuck to avoid excess baking of photoresist (usually lift-off resist). For oxide deposition, the system was pumped down to 6 10 Torr. This low pressure was achieved using A. Mechanical pump - Down to mTorr range, B. Turbo pump - Quick pump down to 10 Torr range, and C. Cryogenic pump down to 10 Torr. During evaporation a 103mA emission current was kept for a 6 A/sec deposition rate which was controlled by a quartz crystal monitor leveled as the same height as the wafer holder. Deposition was only done on front side of the wafer, aiming at 100 nm which was accurately measured to be 1050 A using one monitor wafer. It is again worth to mention that we had six device wafers and one monitoring wafer for this process. 9. Photo Lithography second step After the deposition of second oxide layer, we did another photolithography step to define areas in which we want to form Self-Aligned Silicide (SALICIDE) contacts which will be described later. We spun 1813 positive photo resist, using headway spinner, on front side of the wafer. Then we baked the photoresist on a hotplate set to 115C for one minute. To pattern the photoresist we used the mask pattern shown in Fig. 9 using a transparency mask and then we exposed the photoresist to UV light for 3.5sec using MA6/BA6 contact aligner.

Fig. 9. Second Layer mask artwork for Silicide. Inside closed shaped = solid.

This mask, just like Fig. 1 is consisted of 4 zones and they both together give us artwork demonstrated in Fig. 10. We will use the comb structures of Zone 3 for sheet resistance measurements and the snake structures represent our diodes. The patterned photoresist was then developed in MF-319. Then oxide layer was wet etched in BOE with a ratio of 10:1 for 30 seconds to remove the oxide layer in places where wanted to form SALICIDE. Then the photoresist was stripped using NMP for 3 minutes. Fig. 11 shows the device structure after A. Photoresist development, B. Oxide etch, and C. Photoresist strip respectively.

Fig. 10. Second Layer mask on top of first layer. Inside closed shaped = solid.

Fig. 11. Schematic structure of devices after 2nd oxide deposition, photolithography, oxide etch, and photoresist strip.

10. DC Sputtering of Titanium After defining the etch holes through the second oxide layer, it was now time to deposit the top Ti layer. For this purpose we used DC sputtering which is extensively used for metals deposition. It is worth to mention that DC sputtering cannot be used for deposition of dielectric materials. RF sputtering is instead used for deposition of both metals and dielectric materials. DC sputtering introduces the advantage of a colder process in comparison to evaporation and is suitable for applications where excess baking of photoresist is not desirable (e.g. lift-off). Sputtering also provides a more conformal deposition. In this process ionic plasma by applying a high voltage to a glow tube is created. Then, Ions bombard the target material at the cathode (Ti target).Target atoms are then ejected (sputtered) from the cathode by energy and momentum transfer. Sputtered atoms from the target are then deposited on to the substrate (anode). In this process, we aimed at a 200 nm thickness of Ti and 30 standard cubic centimeters (sccm) flow of Ar at a pressure of 35 mTorr was used for about 6 minutes to sputter the target atoms. The DC voltage and current measured where 350 V and 0.2 A respectively.

11. Rapid Thermal Anneal (RTA) First step After DC sputtering of Ti, we annealed the deposited Ti at 650C for 30 seconds to form C49 phase TiSi2 where Ti layer sees Si underneath (e.g. Source/Drain junctions, polysilicon gate). Annealing of Ti at this temperature based on Fig. 12 gives us a C49 phase which has a higher resistivity and therefore is not suitable for low resistivity contacts. In Table. 1, you can find the sheet resistance of C49 phase TiSi2 measured using Four-point probe. There were two big squares embedded on the wafers for the purpose of TiSi2 sheet resistance measurements.

Fig. 12. Dependence of TiSi2 phase and sheet resistance on annealing temperature.

Applied Current Right Square Left Square

Measured Voltage

Measured Sheet Resistance

1 mA 1 mA

5.746 mV 5.651 mV

26.05 /sq. 25.6 /sq.

Table. 1. Sheet Resistance measurement after 1st RTA.

12. Unreacted Ti selective wet etch After the first annealing step, we etched the unreacted Ti layer in a mixture of 1500 mL of DI water, 300 mL of Ammonium Hydroxide, and 300 mL of Hydrogen Peroxide which took us about 8 minutes to etch thoroughly the unreacted Ti which was around 200 nm so it gave us an etch rate of about 25 nm/min.

13. Rapid Thermal Anneal Second step After etching the unreacted Ti we rinsed the wafers and put them in spin drier to dry. Then, we did another anneal at 800C for 30 seconds to convert the C49 phase TiSi2 into a much lower resistivity C54 phase (Fig .12). In Table. 2, you can find the values of TiSi2 sheet resistance measured using Four-point probe.
Applied Current Right Square Left Square Measured Voltage Measured Sheet Resistance

1 mA 1 mA

1.132 mV 1.336 mV

5.123 /sq. 6.057 /sq.

Table. 2. Sheet Resistance measurement after 2nd RTA (C54).

Fig. 13 shows the structure after A. Ti deposition; B. TiSi2 formation, and C. Unreacted Ti wet etch.

Fig. 13. Schematic of structure after Ti deposition, annealing, and unreacted Ti wet etch.

14. Back-side Aluminum deposition Finally we deposited a 40 nm thick Al on wafers back side to serve as out substrate contact. Al was deposited using DC Sputtering while 30 sccm of Ar was fed into the chamber (52.3 mTorr) and deposition was achieved at a DC voltage of 425V and a DC current of 0.2A for 12 minutes.

15. Measurements In order to demonstrate the four different stack-ups which existed in our wafers, we have to take another close look at Fig. 10. I have also provided another picture (Fig. 14) which better demonstrates the colors which I will be assigning to each different stack-up. As you see in Fig. 14, after aligning the two layers of mask on top of each other (First Doping, Second Silicide), we will face 4 different colors corresponding to a specific stack-up of layers. The colors of interest are White, Red, Purple, and Green. 4 3 2 1

Fig. 14. Four different colors correspond to four different stack-ups. White, Red, Purple, and Green.

You can find the schematic diagram of these four different stack-ups in Fig. 15 below.

Fig. 15. Four different stack-ups. White, Red, Purple, and Green.

As obviously shown in Fig. 14, there are four different structures that can be used for four-point measurements. Structures 1 and 3 (Fig. 14) can be used for P+ region sheet resistance while structure 1. Structure 1 is preferred over structure 3, because in structure 3 there is TiSi2 layer in parallel with P+ region over all the comb structure and it gives us the resistance of these two layers in parallel. So for accurate P+ resistance measurement it is better to use structure 1.

Same thing is also applicable to structures 2 & 4 which are designed for polysilicon sheet resistance measurement. In structure 4 we have polysilicon in

parallel with TiSi2 all over the comb structure and if we do any measurements, we are measuring the resistance of these two layers in parallel. With the same reasoning, structure 2 is preferred over structure 4 for polysilicon sheet resistance measurement.

A. Sheet Resistance Measurement Data We first measured sheet resistance of P+ region using Structures 1 and 3. As mentioned before we expect a lower resistance from structure 3 due the parallelism of TiSi2 and P+ regions in this comb structure. We used SIGNATONE probe station for our I-V measurement. The middle fingers of these structures were used to measure the voltage and the outer fingers were used to apply a current. We then sketched the V-I curves for 3 different spots on the wafer and measured Resistance value from the curves. We then know that: = + 2

Based on this formula we can form 2 equations with 2 unknowns and then solve for Rsheet and Rcontact. But just because our L/W is always constant (Middle fingers) we are essentially forming the same equation all the time which does not help us to calculate Rsheet and Rcontact. We should have used probe configurations for different L/W ratios instead. Any ways, we can now make an assumption that contact resistance is negligible and we can approximate R with:

Based on the information from artworks each comb structure is consisted of 11 0.5x0.5mm squares. Based on the configuration used for probs (Fig. 16) we can say, =3

L W

V I Fig. 16. Four probe configuration.

You can find the sheet resistance values for structure 1 (P+ region covered by oxide layer) in Table. 3 below. Spot No. Spot 1 Spot 2 Spot 3 R () 48.875 47.79 48.83 Rsheet (/sq.) 16.292 15.93 16.277

Table. 3. R, Resistance, and Sheet resistance for different spots of the same structure 1.

For further information, I have also included the V- I curves in Appendix A. V-I curves are sketched using MATLAB and I have used Data Cursors to measure the slope of the V-I curve for R (See Table. 3) calculations. Although, I mentioned earlier that structure 3 is not a good structure for P+ region resistance measurement (P+ in parallel with TiSi2) but I have included the measurements in Table. 4 below for comparison purposes. As obviously shown Sheet resistance, for P+ region, calculated using this structure is much lower and is caused by parallel TiSi2 layer. Spot No. Spot 1 Spot 2 Spot 3 R () 40 25.57 32.45 Rsheet (/sq.) 13.33 8.52 10.82

Table. 4. R, Resistance, and Sheet resistance for different spots of the same structure 3.

MATLAB plots for structure 3 can be found in Appendix B.

We then attempted to measure the sheet resistance for polysilicon layer from structures 2 and 4 but we were not able to measure the resistance. Al most all of the curves showed a step-like V-I behavior as shown in Fig. 17.

Fig. 17. V vs. I for polysilicon layer using structure 4.

We also attempted to measure the polysilicon layer sheet resistance using a twoprobe configuration and we were only able to measure in a single spot using structure 2. The resulted V-I curve is shown in Fig. 18 below. This gave us an R = 97.44 and a sheet resistance of Rsheet = 32.48 for polysilicon layer. This was the only valid data we obtained for polysilicon layer using a two-probe configuration.

Fig. 18. V vs. I for polysilicon layer using structure 2.

We also measured the I-V curve of gate-controlled snake-shaped diodes at VG = 0 (Fig. 19). As you may have noticed in Fig. 10, we have two snake structures with different area sizes. We expect the bigger snake structure demonstrate a much higher leakage current and our leakage current measurements at -2 V shows 285 A and 27.1 A for big and small diodes respectively. The big snake diode turn-on voltage was found to be around 0.7 V but on the other hand the small snake diode showed a 0.5 V turn-on voltage. Then we attempted to measure I-V curves of snake-shaped diodes for different spots on the wafer but in all other spots the amount of current measured for the diodes were on the order of 1 -10 nA (Fig. 20).

Fig. 19. I-V curves big and small snake-shaped diodes respectively.

Fig. 20. I-V curve for both big and small snake-shaped diodes in another spot.

We then tried to measure C-V characteristics of MOS capacitors but were not successful in obtaining a legitimate C-V curve for all our measurement devices.

B. Transistor Measurement Data For all transistor-related measurements we used fabricated devices from previous semester, in which they had not used SALICIDE for their contacts. Instead, they had used Al contacts through opened holes in oxide layer which results in a higher contact resistance which on the other hand degrades performance of the devices for specially smaller-scale devices. Schematic diagram of their fabricated MOSFET can be found in Fig. 21 below.

Fig. 21. Schematic diagram of MOSFET fabricated previous semesters.

For Threshold voltage extraction, VT, I sketched the vs. VG which was measured at a very high VDS = 4 V. We know that in saturation region,

So where 0 we can say that VGS = VT. For gm,max calculations I have calculated

1 [ ] 2

1 [ ] 2

and then sketched this versus VGS.

The peak of the graph gives us gm,max. I have also sketched ID - VDS for all of the five transistors that we characterized. All calculated data corresponding to each different transistor are tabulated in Table. 5. All these calculated data are based on the graphical data which could be found in Appendix C.

Width (W) m 10 20 80 80 80

Length (L) m 5 5 5 10 3

VT (V) 0.54 0.55 0.55 0.52 0.54

gm,max (S) 24.31 53.62 217.4 111.2 220.3

ID,Sat (VDS = 3.2V, VGS = 2V) (A) 376.7 815.8 3280 1745 3395

Table. 5. Calculated data for different W/L aspect ratio.

As obviously shown in Table. 5, if we keep the L constant and increase W, gm will increase, because gm is proportional to W/L. By the same reasoning, Saturation current will also increase. On the other hand, as we keep W constant and increase L, gm and ID,Sat will decrease.

Subthreshold ID vs. VG for all of the five transistor devices is sketched in Fig. 22. As you can see as L is decreasing, subthreshold voltage decreases which is not at all desirable in switching devices which require a high OFF to ON transition.

Fig. 22. Subthreshold ID vs. VG for all of the transistor devices.

16. Conclusion As we went through the process of MOSFET fabrication, differences of various techniques which lead to the same result became more and more obvious. For example, we deposited the polysilicon layer with ebeam evaporator but the resulted film of polysilicon did not at all provide the uniformity and quality of conventional LPCVD polyilicon which is the common technique used in industry. Also the differences between various metal deposition techniques such as ebeam evaporation, resistive heated evaporation, and sputtering became more and more obvious as went through down the fabrication road. Subthreshold slope which is an important measure of ON-OFF characteristic of a device becomes more important as we shrink the length of our devices. Resistivity measurement structures should be designed for minimal effect of other parallel layer on the layer of interest.

Appendix A
V-I curves for Structure 1.

Note: Negative slope corresponds to negative Voltage reading in the opposite direction of current flow.

Appendix B
V-I curves for Structure 3.

Note: Negative slope corresponds to negative Voltage reading in the opposite direction of current flow.

Appendix C
Graphs for transistor measurements.