Quynh Nguyen ECEN 449 TA: Ehsan Rohani Partner: Ryan Oji Date: February 3, 2014

Introduction
The objective of this lab was to familiarize users with the Xilinx FPGA design flow via ISE and review users with different concepts of Verilog such as clock division and different forms of Verilog programing. In this particular lab, the programs are designed to light up LEDs according to the purpose of the program. The first program is by corresponding DIP switches, the second by using a simple counter, the third as a jackpot game.

Procedure
For the first part of the lab, using DIP switches, the lab manual basically walks the user through the steps as a refreshing on the ISE and Verilog from previous courses. For the second part of the lab, the user is expected to implement a simple counter using the up and down button on the FPGA board to increment or decrement a counter which would be displayed on the LED. The crucial element of this part is correct application of the frequency divider. As the FPGA board runs with a clock frequency of 100 MHz, the clock needs to be slowed down in order for updates to be seen. With this, the up and down button on the board is used, respectively, to increment and decrement the counter. The frequency divider module (freqdiv.v) divides the clock by 50MHz instead of 100MHz by resetting the counter (which increments by the positive edge of the clock) and setting the output clock either by 1 or 0. In the simple counter, the positive edge of the output clock triggers the counter sequence. The third part of the lab requires the user to implement a module that lights one LED at a time in a sequence so that when the user turns on the right DIP switch corresponding with the light, all of the lights would turn on and stay on until the reset button is pressed. In this part, the user cannot do a preset DIP switch to win but has to actually hit the right switch at the right time. In both the second and third part of the lab, the counter and jackpot, the positive edge of RESET is also used to reset the counter or sequence.

Results
The results of those lab objectives were positive. Initially there were some complications with the frequency divider but the solution to that problem was fixed by modifying the counter register to be 26 bits instead of 25. After that, the counter was still having an error, which was fixed by finding the location of the CLOCK in the UCF manual. For the lottery/jackpot module, there was some discrepancy with logic. Originally it was using the counter and if statements to light the LEDs. However, another

alternative solution comprises of implement the next state. For example, an if statement saying that if the first light is on, then the next light will be the second. A flag is used to indicate whether there is a winner or not and initializes at zero. Under these conditions based on which LED is on, there are three cases to be examined for each LED. One is to turn off all of the LEDs when the user picks the wrong switch. Second is to light all the LEDS when the user hits the right DIP and that remains until the reset is hit. The final case is to continue the sequence if none of the switches is on. The only remaining discrepancy with the jackpot/lottery module is that if one presets the first switch, there is an automatic win since the conditions for the first switch is set first. One way to fix this is to take that chunk of code and put it at the bottom of the sequence but it does not really follow good coding conventions.

Conclusion
For the conclusion of this lab, all objectives were meant in terms of implement the programs such as the counter and lottery/jackpot. In addition to this, there was a good refresher on creating a test bench and running a simulation to check and troubleshoot the modules with sample stimulations. a. How are the user push-buttons wired on the XUP board? So whenever the buttons are pushed on the board, the signal is sent from that button which then sends a signal to the corresponding LED. b. What is the purpose of edge detection circuit and how should it have been used in this lab? In this lab, the edge detection is used to trigger the sequence inside of the always block for the positive edge of the RESET and CLOCK inputs. In the second lab, the edge detection is used to slow down the clock as well as implement the counter. In the third lab, it activates the light sequence.