Beruflich Dokumente
Kultur Dokumente
1) AND Gate
Program: module gateand(a, b, c); input a; input b; output c; assign c=a&b;
endmodule
// Outputs wire c;
// Instantiate the Unit Under Test (UUT) gateand uut ( .a(a), .b(b), .c(c) );
// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop;
end
endmodule
Simulation:
2) OR Gate
Program: module orgate(a, b, c); input a; input b; output c;
// Outputs wire c;
// Instantiate the Unit Under Test (UUT) orgate uut ( .a(a), .b(b), .c(c) );
#2 a=1;b=1; #2 $stop;
end
endmodule
Simulation:
3) NOT Gate:
// Inputs reg a;
// Outputs wire b;
// Instantiate the Unit Under Test (UUT) notgate uut ( .a(a), .b(b) );
a = 0;
end
endmodule
Simulation:
4) NOR gate:
Program: module norgate(a, b, c); input a; input b; output c;
// Outputs wire c;
// Instantiate the Unit Under Test (UUT) norgate uut ( .a(a), .b(b),
.c(c) );
// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop; // Add stimulus here
end
endmodule
Simulation:
5) NAND gate:
Program: module nandgate(a, b, c); input a; input b; output c; assign c=~(a&b);
endmodule
Test bench:
module nandgatetb_v;
// Outputs wire c;
// Instantiate the Unit Under Test (UUT) nandgate uut ( .a(a), .b(b), .c(c) );
#2 $stop;
end
endmodule
Simulation:
6) XOR gate:
Program:
endmodule
// Outputs wire c;
// Instantiate the Unit Under Test (UUT) xorgate uut ( .a(a), .b(b), .c(c) );
// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop;
end
endmodule
Simulation:
7) XNOR gate:
Program: module xnorgate(a, b, c); input a; input b; output c; assign c=~(a^b);
endmodule
// Outputs wire c;
// Instantiate the Unit Under Test (UUT) xnorgate uut ( .a(a), .b(b), .c(c) );
// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop;
end
endmodule
Simulation: