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Lecture 3
I
SSTEM YOLU
8255, 8256 8253 (8254) 8251 8257 8259 8279, ...
ROM
RWM
Giri
(Temel) 3-durumlu buffer
k
(Temel) Latch, FF
A collection of addressable registers: Those registers reside within the microprocessor are internal registers, and those exist in the ROM, RWM, and I/O ports are external registers.
CPU Saklayclar
ip-zeri yollar
ALU
Hafza
I/O
I/O
Giri Cihaz
Latch E
3-Durumlu Buffer
D0 D1 Dm
Giri Cihaz Seme Darbesi
k Cihaz
Latch
D0 D1 Dm
k Cihaz Seme Darbesi
A0 A1 An
A0 A1 An
IO / M RD
IO / M WR
Internal Architecture
1. Basic Microprocessor System Concepts
R0 R1 R2 R3
ALU
(Arithmetic Logic Unit)
R3 SR (Status Register) IR (Instruction Register) IP (Instruction Pointer) SP (Stack Pointer) MAR (Memory Address Register) MBR (Memory Buffer Register) (FPU, hafza ynetim birimi, cache, ...) Teknolojinin gelimesiyle eklenen dier donanm ve yazlm
Kontrol Birimi
1. Control Unit
Harici Veri Yolu MBR
It controls and synchronizes all data transfers and transformations in the microprocessor system.
Dahili Veri Yolu
Komut Saklaycs
IR
Yrtme (Execute)
Komut Kod zc
The output of the IR is decoded and used by the control unit to develop a sequence of microoperations (microistructions) and register transfers that execute the instruction.
RESET
Locate and obtain operand data Compute result value or status Write results to memory for later use
X86 registers
Temp. Reg
BP SP
X86 registers
Internal Bus
ALU
ALU
Flags
Flags
Arithmetic and logic operations on one or two 8-bit, 16-bit (x86), and 32-bit (x86) operands are performed in this unit.
Halk Gmkaya
External Architecture
Address Bus Data Bus Control Bus 1. Bus control 2. Bus status 3. Interrupts 4. Bus arbitration 5. Coprocessor signaling 6. Misc
Control Bus
Address Bus: Common address bus widths are 16, 20, 32, and 64 Data Bus: Common widths are 8, 16, 32, and 64. Control Bus: The control pins regulate the flow and timing of data to and from the CPU and have other miscellaneous uses. Control pins can be roughly grouped into the following major categories: Bus Control Interrupts Bus Arbitration Coprocessor Signalling Status Miscellaneous
Bus Control: Mostly outputs from the CPU to the bus telling whether the CPU wants to read or write memory or do something else. The CPU uses these pins to control the rest of the system. Status: They show the status (i.e. bus operation, MEMR, IOW) of CPU. Interrupts: They are inputs from I/O devices to the CPU. Bus Arbitration: These pins regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time. Coprocessor Signalling: Some CPU chips are designed to operate with coprocessors such as floating point chips, graphics or other chips. Miscellaneous: CLK, XTAL, reset, power,
ALU
Komut Kod zc
Zamanlama ve Kontrol
Durum DMA RESET MAR MAR / MBR
RD WR ALE
A15 - A8
74LS373
A15 - A8
8085A
32 31 30 29 28 27 26 25 24 23 22 21
8085A
AD7 - AD0
C OE
ALE
(a)
(b)
There are 7 different types of machine cycles in the 8085: Opcode fetch Memory read MEMR Memory write MEMW I/O Read IOR I/O Write IOW Interrupt acknowledge Bus idle
3 status signals generated at the beginning of each machine cycle identify each type and remain valid for the duration of the cycle.
Bus Status Machine Cycle Opcode fetch Memory read Memory write I/O read I/O write Interrupt Ack. Bus idle HLT DAD Ack. of RST, TRAP IO/M 0 0 0 1 1 1 0 1 3-state S1 1 1 0 1 0 1 1 1 0 S0 1 0 1 0 1 1 0 1 0 RD 0 0 1 0 1 1 1 1 3-state
STA (Store Accumulator Direct) transfers the contents of ACC to an external register (a memory register or a memory mapped output register) whose address is specified in the instruction. The opcode for STA is 32h. This register can be located anywhere in the 64 K memory space that the 8085 can directly address, 16-bits are required for the address. LDA (Load Accumulator Direct) does the reverse operation. It reads from an external register to the ACC. The opcode is 3Ah.
Each machine cycle is divided by system clock into a number of state transitions, or T states, which correspond to the period between two negative going transition of that clock.
T1
A memory or I/O device address is placed on the address/data bus (AD7-AD0) and address bus (A15-A0). An address latch enable, ALE, pulse is generated to facilitate latching the low order address bits on AD7-AD0. Status information is placed on IO/M, S1, and S0 to define the type of machine cycle. The halt flag is check. Ready and hold inputs are sampled. PC is incremented if machine cycle is part of an instruction fetch. In all machine cycles except BUS IDLE, one of the control strobes RD, WR, or INTAmakes a 1 to 0 transition. (optional) This state is entered if the ready line is low. The states of the address, data and control signals remain the same as at the end of T2. An instruction byte or data byte is transfered to/from memory the microprocessor. The active control strobe makes a 0 to 1 transition. The contents of instruction register (IR) are decoded. These states are used to complete the execution of some instructions.
T2
Tw T3 T4 T5 - T6
Machine Cycles 1. Opcode fetch 2. Memory read 3. Memory write 4. Memory write (STA) or read (LDA) Total T-states for 4 machine cycles
T-States 4 3 3 3 13
For STA and LDA instructions, the number of T-states required for the execution is 13. If the 8085 is operating at a 325.5 nS state time, the STA/LDA instruction cycle is executed in 4.23 S.
System Memory
The 8085 system has ROM and RWM memory modules, one input port (a simple 8-bit three-state buffer 74LS244) for reading switches, and one output port (74LS374) for driving a LED display. Use the memory system example given in the first lecture. 4K8 EPROM ve 2K8 RWM EPROM starts from 0000h, after EPROM RWM starts.
0000h ROM 0FFFh 1000h 17FFh 1800h 4K
0000h 0FFFh A15 A 12 A11 A8 A7 A4 A3 A0
A13 A12 A11
2732 4K x 8 EPROM CE OE
74LS138 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
07FFh-0000h 0FFFh-0800h 17FFh-1000h
RD
0 0 0 0 0 0 0 0
lk 4K'lk blou seer
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
4K ROM iinde bir hafza hcresini seer
0 0 0 0 1 1 1 1
A15 A14 G2A G2B G1
A10 - A0 11
A11 - A0
D7 - D0
RWM
2K
1000h 17FFh 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1
IO / M
6116 2K x 8 RWM CS OE WE
FFFFh
Bo
0 0 0 0 1 1 1 1
2K RWM iinde bir hafza hcresini seer
0 0 0 0 1 1 1 1
58K
nc 2K'lk blou seer
RD WR
Memory Map
+5V
+5V
D7
D0
+5V RD IO / M A7 A6 A5 A4
S7
D7
D7
74LS374 Octal FF
D0
+5V WR IO / M A7 A6 A5 A4 A0
D0
CLK OE
S0
ADRES
Program Assembly and Machine Code Address 0000 0002 0003 0006 0009 000B Machine Code DB F0 2F 32 00 10 3A 00 10 D3 F1 76 Assembly Code IN CMA STA 1000h LDA 1000h OUT F1h HLT F0h
VER
DBh F0h 2Fh 32h 00h 10h 3Ah 00h 10h D3h F1h 76h
0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh
LDA 1000h
Registers
MEMR
An 8-input NAND gate is used as an input decoder. The input device is located at F000h. When IN F000h is executed by CPU, at the last machine cycle, F000h is placed onto the address bus, IO/M becomes 0. Finally RD is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the 3-state buffer of the input device is activated, and data at this device is read to ACC by CPU.
To write to an output port, use a memory access instruction, like STA. The output decoder monitors memory related control lines and addresses. An example: An output device is located at a memory address F001h. Use partial address decoding, use just 5 address lines from the address bus: A15, A14, A13, A12, and A0.
+5V IO / M WR A15 A14 A13 A12 A0 MEMW
An 8-input NAND gate is used as an output decoder. The output device is located at F001h. When OUT F001h is executed by CPU, at the last machine cycle, F001h is placed onto the address bus, IO/M becomes 0. Finally WR is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the input device is activated, and 8-bit data at ACC is written to the output device by CPU.
processors may not have such separate IN and OUT instructions for I/O in their instruction set. Using IN and OUT, you can only read from or write to an I/O device. If you want to do some other operations, like OR, AND, ADD, ) directly on I/O devices, the memory mapped I/O technique can be used. If the number of I/O devices is larger than 512 (for 8085) use the memory mapped I/O.
Programmable I/O
In our previous simple example, we had very simple I/O devices. In general microprocessor based systems, like PCs, have programmable I/O devices. These devices have programmable I/O ports. In addition to simple reading and writing data, they have also some build-in additional features, like timers/counters, interrupts, bit-addressable ports,
D7-D0 PA7-PA0
D0 - D7 PA
Data Bus (bidirectional) Port A Port B Port C Chip Select Port Address Read Control Write Control Reset Input +5 Volt 0 Volt
8255A
32 31 30 29 28 27 26 25 24 23 22 21
8255A
CS A1 A0 RD WR RESET (b)
PC
Some examples: Basic and handshake parallel I/O (8255, 8256) Timer/counter (8253/8254) Interrupt controller (8259) Serial/parallel data communication (8250, 8251, 8256) 1-bit data I/O (bit addressable) (8256) Keyboard/display interface (8279) Block data transfer between memory and external world (DMA) (8257)
PB
(a)
8255A Chip and Port Select Signals CS 0 0 0 0 1 A1 0 0 1 1 X A1 0 1 0 1 X Selected Port Port A Port B Port C Control Register 8255A not selected
D2
D2
D0
D7
D6
D5
D4
D3
D2
D1
D0 Grup B Port C (Dk PC 3 - PC0) 1 = Giri 0 = k Port B 1 = Giri 0 = k Mod Seimi 1 = Mod 0 0 = Mod 1 Grup A Port C (Yksek PC 7 - PC4) 1 = Giri 0 = k Port A 1 = Giri 0 = k Mod Seimi 00 = Mode 0 01 = Mod 1 1X = Mod 2 1 = I/O Modu 0 = BSR modu
Kontrol Kelimesi
PB
PB = C1h
Mod 1 A ve (veya) B port'lar iin el skmal (handshake) alma C port'u el skma sinyalleri iin kullanlr
Mod 2 A port'u iin iki ynl veri yolu Port B: Mod 0 veya 1 de alr C port'unun bit'leri el skma sinyalleri olarak kullanlr
PC
PC = C2h
CS = 0 A7 A6 A5 A4 A3 A2 1 1 0 0 0 0 A1 A0 0 0 0 1 1 0 1 1
of using a 3-state buffer and a latch for I/O devices, this time use an 8255 for the 8085 based system example. 8255 base address is F0h, that is the address of PA. PA will be used to read switches. PB (at F1h) will be used to drive the LED display. PC (at F2h) will not be used. Control register is at F3h. Control word = 1 0 0 1 0 0 0 0 = 90h.
D0 - D7 PA
CS A1 A0 A1 A0
S0
PB
RD WR RD WR RESET D0
PC
A simple I/O example using a 8255 located at F0h. MVI A, 90h OUT F3h IN F0h; OUT F1h ; (ACC) 90h, Load ACC with 90h (A: input, B: output) ; (F3) (ACC), write the contents of ACC (90h) to control register, 8255 is programmed. ; read switches (ACC) (F0h) ; drive LEDs (F1) (ACC)
References