Tutorial4: Synthesis of Verilog in Leonardo Spectrum

http://www.swarthmore.edu/NatSci/tali/E77/Mentor_Tutorials/tutorial4.htm

Mentor Graphics Tutorial 4 Synthesis of Verilog code with Leonardo Spectrum and simulation with ModelSim Estimated Time: 45 minutes In this tutorial we will be synthesizing Verilog code using Leonardo Spectrum from Mentor Graphics. We will then simulate the synthesized Verilog Netlist that we export from Leonardo, using ModelSim. Synthesis (Leonardo Spectrum) Sadly Leonardo Spectrum is not available for Linux and so we will have to switch between Linux and Windows. 1. The Verilog code used for this tutorial can be downloaded here, increment.v, or you can use your favorite text editor to make it.

module increment(in, out); input [1:0] in; output [1:0] out; assign out = in + 1'b1; endmodule
2. Open Leonardo Spectrum. ( Start>All Programs>Leonardo Spectrum LS2007a_37> Leonardo Spectrum LS2007a_37) 3. Choose Level 3.

Fig: Starting Leonardo Spectrum. 4. Click on the 'Toggle Advanced FlowTabs' icon in the toolbar near the top of the window to enter the Advanced mode. 5. Type the command set exclude_gates {PadOut PadInC} in the command window in the bottom right panel. This command excludes the gates PadInC and PadOut from being imported when we load the library in the next step. 6. The Technology tab should be selected. Choose AMI 0.5u (typ) library and load it.

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Tutorial4: Synthesis of Verilog in Leonardo Spectrum

http://www.swarthmore.edu/NatSci/tali/E77/Mentor_Tutorials/tutorial4.htm

Fig: AMI 0.5u (typ) is under ASIC>Mentor Graphics. 7. Click the Input tab. Set the working directory to the directory with the Verilog file, and then click on Open Files button to open the increment.v file. Load the file by clicking the Read button. 8. Move on to the Optimize tab, and click optimize. 9. Go to the Output tab, specify the name of the output file as syn_increment.v, and choose the output format as Verilog. Click Write to export a synthesized Verilog netlist to your working directory. You are done with synthesis. 10. The synthesized verilog netlist will read:

// // Verilog description for cell increment, // 08/09/07 16:54:56 // // LeonardoSpectrum Level 3, 2007a.37 // module increment ( in, out ) ; input [1:0]in ; output [1:0]out ;
xor2 ix3 (.Y (out[1]), .A0 (in[0]), .A1 (in[1])) ; inv02 ix76 (.Y (out[0]), .A (in[0])) ; endmodule Simulating Synthesized Verilog Netlist (ModelSim) Back to Linux. Remember you have to access the file you exported from Leonardo. Copy it to a network drive or email it to yourself!!! 1. Invoke ModelSim by typing ./msim in your home directory. 2. Create a new library and name it syn_increment. 3. Press the compile button and choose syn_increment as the library and select the file syn_increment.v, and compile it. The file, increment will appear under the library in the Workspace. 4. The synthesized verilog netlist uses actual circuit components, and so we will need to add the components to the library to be able to simulate the netlist. Compile the file /usr/local/mentor/adk/technology/adk.v, which has the circuit components we need, and compile it to the library. You should have various circuit components (eg. and02, buf02, and xnor2) available in the library.

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Tutorial4: Synthesis of Verilog in Leonardo Spectrum

http://www.swarthmore.edu/NatSci/tali/E77/Mentor_Tutorials/tutorial4.htm

Fig: Circuit components loaded to the library. 5. Double-click the 'increment' file in your library to invoke the simulator. Click View>Objects if the Objects window is not visible. 6. Type in the command view wave to display the wave window. 7. Add the 'out' in the Objects window to the wave by right clicking it and choosing Add to Wave>Selected Signals. 8. Add input to in. Right-Click>Create Wave. Choose Repeater and press Next. Change the period to 250, and add signals 00, 01, 10 and 11 separated by commas and spaces. 9. Type in run 1000 to run the simulation for 1000 ns.

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Tutorial4: Synthesis of Verilog in Leonardo Spectrum

http://www.swarthmore.edu/NatSci/tali/E77/Mentor_Tutorials/tutorial4.htm

Fig: Simulated Verilog Netlist of an incrementor. Viewing Synthesized Verilog Netlist in Design Architect 1. Invoke Design Architect by typing ./daic from your home directory. 2. Click on File>Import Verilog. 3. Choose the synthesized file syn_increment.v as the Netlist File, choose an output directory (different from the directory you have the verilog code in), choose /usr/local/mentor/adk/technology/adk_map.vmp as the Mapping File, and press OK.

Fig: Import Verilog window. 4. The status bar should give you the status on process and will read something like 'Note : Import of Verilog netlist complete......' 5. Click File>Open>Schematic and browse to the folder that you chose, and open the schematic that has been created.

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Tutorial4: Synthesis of Verilog in Leonardo Spectrum

http://www.swarthmore.edu/NatSci/tali/E77/Mentor_Tutorials/tutorial4.htm

Fig: Schematic created by Design Architect from the Verilog Netlist.

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