International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING &

; ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME TECHNOLOGY (IJEET)

ISSN 0976 6545(Print) ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), pp. 17-25 IAEME: www.iaeme.com/ijeet.asp Journal Impact Factor (2013): 5.5028 (Calculated by GISI) www.jifactor.com

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SWITCHING LOSS CALCULATIONS OF SERIES PARALLEL SWITCHED MULTILEVEL DC-LINK INVERTER

G MADHUSAGARBABU1, N SAIKUMAR2, N DEVI PRIYA3, B PHANIKUMAR4 (E.E.E, SCET, Narsapur, A.P., INDIA) (E.E.E, SCET, Narsapur, A.P, INDIA) 3 (E.E.E, SCET, Narsapur, A.P, INDIA) 4 (Asst. Engineer (KTPS), Paloncha, A.P., INDIA)
2 1

ABSTRACT In recent days multilevel inverters has become very popular for motor driveapplications of industry. Multilevel pulse width modulation inversion is an effective solution for increasing the levels of the output wave form and thereby dramatically reduced to the harmonics and total harmonic distortion. The MLDCL provides a dc voltage with the shape of a staircase, with or without pulse width modulation, to the bridge inverter, which in turn alternates the polarity to produce an ac voltage. A Series Parallel Switched Multi-Level Inverter (MLI) based on Multi level DC link (MLDCL) Inverter topology pioneer the component reduction and add benefits to apt for economic and power quality and thereby claim its superiority over the existing MLI configurations. Finally the performance of this topology is investigated through MATLAB based simulation for SPSMLDCLI fed Single phase Induction Motor using In-phase Disposition (IPD) PWM technique and by calculating the switching losses. Keywords: Induction Motor, Multi-Level Inverter, SPSMLDCLI, THD, Switching Frequencies. I. INTRODUCTION

Multilevel inverters have very important development for high power medium voltage AC drives. Quite a lot of topologies have found industrial approval; Neutral Point Clamped, flying capacitor, H-bridge, cascaded with separated DC source, several control and modulation strategies have been developed Pulse Width Modulation (PWM), Sinusoidal PWM, Space Vector PWM and Selective harmonic Eliminations[1]. Multilevel converters are mainly controlled with sinusoidal
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

PWM extended to multiple carrier arrangements of two types: Level Shifted (LS-PWM), which includes Phase Disposition (PD-PWM), Phase Opposition Disposition (POD-PWM) and Alternative Phase Opposition Disposition (APOD-PWM) or Phase Shifted (PS-PWM) [2]. This paper presents a new variety of MLDCLI which uses lower number of sources, power switches and eliminates the necessity of capacitors. The topology coined as series parallel switched multilevel dc-link inverter (SPSMLDCLI) synthesizes a nearly distortion lesssinusoidal output voltage owing to its inherent ability to increase the number of levels. For the same number of output voltage levels, the number of power devicesrequired is 76% less when compared with the basicMLI topologies and 44% with MLDCLIs. The performance of this SPMLDCLI is investigated through MATLAB based simulation over a range of viable modulation indices.The switching loss estimation of this topology is helpful for determining the efficiency of the converter. II. CIRCUIT TOPOLOGY

The power circuit of the inverter consists of a number of voltage sources in the ratioV0: Vn with switches and a diode is connected across the H-bridge. The voltage sources are connected in series parallel manner for generating desired level of output voltage [4] To increase the number of levels further, an external cell is required which contains twovoltage sources and diodes along with a switch as shown in fig.1.Hence when a dc link voltage from power circuit is fed to the full bridge inverter, a Nearly high quality sinusoidal output voltage will be obtained. Therefore with less number of switches better THD output is obtained when compared with existing topologies. The available power switches where a simple switch and an anti-parallel diode are patched to permit regeneration experience a specific phenomenon of inter-looping andconsequently create two circulating current paths. It may lead to a possible distortion in the output voltage. The problem can however be eliminated by replacing the switches Sc, Sa, Sc1, Sa1 with IGBT s and remaining switches with MOSFET s to get high switching speed.

Fig.1.Generalized structure of SPSMLDCLI The operating modes of the fifteen level SPSMLDCLI topology are given in Table 1 and explained for two levels (50 V, 100 V) with figures (2-3).

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

Fig.2.SPSMLDCLI operating mode-level 1(50 V)

Fig.3. SPSMLDCLI operating mode-level 2(100 V)

TABLE 1: SPSMLDCLI modes of operation for 15-level topology Operating Modes Current Paths Level-1: +50 V +50vSa1 Sc S1 S2 -50V Level-2: +100 V Level-3: +150 V Level-4: +200 V Level-5: +250V Level-6: +300 V Level-7: +350 V +150vSc1(50v)DbS1S2-150v +150vSc1ScS1S2 -150v +150v(50v)Sb1SbcS1S2-150v +150vSc1(50v)Sa(150v)S1S2-150v +150vSbSc1(150v)S1S2-150v +150vSb1(50v)Sb(150v)S1S2-150v

For negative operating modes, Turn-On Inverter switches S3 and S4 instead of S1 and S2

III.

SWITCHING LOSS CALCULATIONS

Consider a single MOSFET switch connected across a dcvoltage of value Vdc. Current through switch during ontime is considered as Idc. Figure 4 shows the waveformsof the voltage across and the current through the switch, when it is operated at a switching frequency of Fs = 1/Ts,where Ts is the switching period. To simplify the expressions,the switching waveforms are represented by linearapproximations. In the figure 4, VM andiM are the voltage across and the current through the MOSFET [5, 8].

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

Fig.4. Switching characteristics of MOSFET

Where Vdc - voltage across switch when turned-off tc(on)- turn-on cross-over interval tc(off) - turn-off cross-over interval td(on)- turn-on delay time td(off)- turn-off delay time PSW - average switching loss in watts VON - voltage across switch when turned-on FS - switching frequency in Hz TS - sampling time in sec Idc - current through switch when turned-on Switching losses of MOSFET can be calculated from the turn-on and turn-off characteristics of the devices. Instantaneous voltage and current during turn on time tc(on) are [6] ; 0 it ; 0 Instantaneous power during the interval tc(on) is pt vt it = I = I and energy dissipated during this interval is tc(on),
E, I dt

(0 to )

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME
E, I 2 I /3 1 1 E, I I 2 3 3 E, I 2 I 3 E, I / 6 I / 3

During turn-off transition, of t c(off), the current falls from Idc to zero and the Von rises linearly to Vdc. The instantaneous voltage and current during this period are it I I The instantaneous power dissipated during the interval tc(off) is pt vt it = t I I t = I I t I t I Hence, the energy dissipated can be found as tc(off), E, I I t I t I dt0 to E, I I / /2 I /2 / I /3 1 E, I 1 I /3 I 2 2 1 1 I E, I 2 6 6 I t 6 I t 3 The average switching loss in the switch during each transition of turn on and turn off can be found as P, I t T / 6 I t T / 3 P, I t T / 6 I t T / 3 Hence, the average switching loss PSW in the switch is 1 v 1 I I I 6 3 6 1 I 3 / . Switching losses of IGBT can be calculated from the turn-on and turn-off characteristics of the devices as shown below,

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

The instantaneous power [8] is Pt

Fig.5. IGBT Current and Voltage Turn-on and Turn-off Waveforms

2 1 2 1 2 1 1 2 2 Hence, the average switching loss PSW in the switch is Hence from above expressions, the total average switching losses (MOSFET & IGBT switches) of SPSMLDCLI can be calculated. IV. SIMULATION RESULTS

The SPSMLDCLI has been implemented and simulated for RL and single phase Induction Motor (IM) as loads. The output voltage and current waveforms for fifteen level topology and stator current, torque and speed characteristics are shown in below figures (6-11).

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

Fig.6. Simulation Circuit for SPSMLDCLI FED induction motor

Fig.7. Output voltage of SPSMDCLI (RL-load)

Fig.8. Output current of SPSMDCLI (RL-load)

Fig.9. FFT Analysis (SPSMLDCLI)

Fig.10. IMStator current waveform

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

Fig.11. IMTorque and rotor speed waveforms

Table 2: Switching losses and %THD of 15-levelSPSMLDCLI Switching frequency(HZ) 1500 2000 3000 4000 Switching losses (W) 100.57 148.4 211.8 258.87 % THD

8.31 8.69 8.22 7.70

V.

CONCLUSION

A Series Parallel Switched Multilevel DC link Inverter fed single phase induction motor drive has been implemented using Mat Lab and simulation results are presented. Due to reduced switch count of this topology compared with existing topologies, the cost and size will be reduced and less THD output voltage will be obtained. A comparative study of THD of the output voltage waveform and switching losses of fifteenlevel SPSMLDCL inverter has been presented in this paper using the IPDPWM technique. It has been observed (Table 2) that with the decrease in carrier frequency, the THD level increases and switching losses of this MLDCLI decreases. VI. [1] [2] [3] [4] REFERENCES K. RAMANI and Dr. A.KRISHNAN SMIEE, An estimation of multilevel inverter fed induction motor drive international journal of review in computing 2009. Mauricio Angulo, Pablo Lezana , Samir kouro, Jose Rodriguez and wu level shifted for cascaded multilevel inverters with even power distribution IEEE transactions 2007. Rodriguez J, Jih-Sheng Lai, Fang Zheng Peng. Multilevel inverters: a survey of topologies, controls, and applications. IEEE Trans Indus Electron 2002;49(4): 72438. Ramkumar S, Kamaraj V, Thamizharasan S, Jeevananthan S. A new series parallel switched multilevel dc-link inverter topology. Int J Electr Power Energy Syst 2012;36:93.

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 5, Issue 1, January (2014), IAEME

Mohan Ned, Undeland T.M. & Robbins W.P., Power Electronics: Converters, Applications and Design, John Wiley and Sons, Second Edition, 2001. [6] Pradyumn K. Chaturvedi, Shailendra Jain1, Pramod Agrawal2, Rajesh K. Nema1 and Kaushal K. Sao3Switching Losses and Harmonic Investigations in Multilevel Inverters, iete journal of research | Vol 54 | ISSUE 4 | JUL-AUG 2008. [7] Jih-Sheng Lai, Fang Zheng Peng. Multilevel converters-A new breed of power converters. IEEE Trans Indus Appl 1996;l.32(3):50917. [8] Bierhoff, M.H., Fuchs, .W. Semiconductor losses in voltage source and current source IGBT converters based on analytical derivation, Power Electronics Specialists Conference PESC 04, IEEE 35th Annual, Vol.4, pp. 2836 2842, 2004. [9] Dipti Shah and Prof. B.T. Deshmukh, Reversible D.C. Drives using 4q IGBT Chopper Circuit for Industrial Applications, International Journal of Electrical Engineering & Technology (IJEET), Volume 3, Issue 1, 2012, pp. 282 - 287, ISSN Print : 0976-6545, ISSN Online: 0976-6553. [10] Abhijit D. Ghorapade and Snehal S. Mule, Simulation of IGBT Based Speed Control System for Induction Motor using Fuzzy Logic, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 3, 2013, pp. 282 - 291, ISSN Print: 0976- 6464, ISSN Online: 0976 6472.

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