PC Parallel Port Interfacing

Hughes Micro-Technologies, Inc.

BASIC INFORMATION The PC Parallel Port is commonly used to create an interface between a computer and an external piece of hardware. Found on the back of a PC, the parallel port is a D-Type 2 Pin Female Connector. The parallel port is capable of recei!in" # bits of data or transmittin" $2 bits of data, at any "i!en time.

Figure 1: Parallel Port Connection Pins %ithin these lines there are three "roups of pins known as the Data Port, &tatus Port, and Control Port. The Data Port is composed of ' lines Data ( ) Data * +Pins 2 ) #, that allow data to be transmitted or recei!ed to-from an external de!ice. Offset .ase / ( Name Data Port Read/ rite Bit No! .it * .it 1 .it .it 2 .it 3 .it 2 .it $ .it ( Ta#le 1: SPP $ata Port The &tatus Port is a read only port composed of input lines +Pins $(, $$, $2, $3, 4 $ ,, an 506 status re"ister, and two reser!ed lines. Offset .ase / $ Name Read/ rite Bit No! .it * .it 1 .it .it 2 .it 3 .it 2 .it $ .it ( Pro"erties n.usy n7ck Paper 8ut &elect 5n 9rror 506 +:ot, 0eser!ed 0eser!ed Pro"erties Data * Data 1 Data Data 2 Data 3 Data 2 Data $ Data (

0ead-%rite

&tatus Port 0ead

Ta#le %: SPP Status Port Finally, the Control Port is composed of ' lines that are used to control the sendin" and recei!in" data. ;ost importantly is the n&trobe line, which indicates that data is ready to be sent-recei!ed. Offset .ase / 2 Name Control Port Read/ rite Bit No! .it * .it 1 .it .it 2 .it 3 .it 2 .it $ .it ( Ta#le &: SPP Control Port %hen writin"-readin" from the PC Parallel Port it is important to ensure the proper address is bein" used. :ormally the PC Parallel Port is "i!en one of three commonly used base addresses. >owe!er, dependin" on what external de!ices are acti!e it is easy to confuse the correct address. Address (x3.C ) (x3.F (x3*' ) (x3* (x2*' ) (x2*F Notes: Parallel Ports which were incorporated on to ?ideo Cards <sual 7ddress For =PT $ <sual 7ddress For =PT 2 Ta#le ': Port Addresses 5t is also possible to detect the specific address assi"ned to each indi!idual =PT port within .58&. For the proper C code to perform this task please !isit@ http@--www.beyondlo"ic.or"-spp-parallel.htmA2 OP(RATION MO$(S =ike most de!ices, the PC Parallel Port has se!eral different modes of operations. These modes ran"e from &tandard ;ode, which allows for unidirectional operation, to 9xtended Capabilities ;ode +9CP,, which allows use of the 9xtended Capabilities 0e"ister +9C0,. These modes can be set in .58& and are described in detail below@ Compatibility Mode (Centronics Mode): Compatibility ;ode is a unidirectional mode used to send information from the PC to an external de!ice, usually at a rate of approximately ( B.-s. The process incorporates four steps@ $. 2. 3. 2. The data byte is written to the data lines of the proper parallel port address. 7 check is made to see if the external de!ice is busy with an operation. The &trobe =ine +Pin $, is pulled low and the data is transferred to the external de!ice. 7fter acceptin" data, the external de!ice will respond by pullin" the n7ck =ine low for Pro"erties <nused <nused 9nable .idirectional 9nable 506 &elect Printer 0eset Printer 7uto =inefeed n&trobe

0ead-%rite

Cs.

Figure %: Com"ati#ilit) Mode Timing $iagram 7lthou"h Compatibility ;ode was intended for unidirectional data transfer, there are se!eral ways to read data from an external de!ice, while in this mode. The first is the use of a bidirectional port, which would reDuire settin" the th bit in the Control Port to enable this feature. 8nce this is done, data can be transferred and read by accessin" the proper address of the PC Parallel Port. The second method allows for the transfer of # bits throu"h the use of nine lines on the &tatus and Control Ports. 9xternal data lines are attached in the displayed manner with se!eral lines usin" 8pen Collector 5n!ertors. 8pen Collector 5n!erters are used to ensure that the PC Parallel Port can still manipulate the state of each line.

Figure &: (*ternal $ata Transfer Pin Configuration 8nce the external lo"ic is prepared, data can be read from the ' lines, pro!ided that the proper C code is used. The first step reDuires writin" xxxx($(( to the Control Port to enable data transfer. 8nce this is finished, the data is transferred in two separate nibbles@ outportb(CONTROL, inportb(CONTROL) & 0xF0 | 0x04); //Set Control a = (inportb(ST T!S) & 0xF0); //Rea" t#e $S Nibble a = a |(inportb(CONTROL) & 0x0F); //Rea" t#e LS Nibble a = a % 0x&4; //Co'bine t#e $S & LS Nibble( For more information please !isit the followin" link@ http@--www.beyondlo"ic.or"-spp-parallel.htmA*

Finally, another effecti!e way of readin" data from an external de!ice is know as :ibble ;ode. :ibble ;ode reDuires the use of a 6uad 2 line to $ line multiplexer. 7lthou"h :ibble ;ode reads the same amount of information as a bidirectional connection or the pre!ious method, it is slower and reDuires the use of an external 5C. The ei"ht data lines of the external de!ice are connected to the 7 4 . input lines of the multiplexer. The outputs of the multiplexer are connected to lines on the Control and &tatus Ports, as shown below@

Figure ': Pin Connections for Ni##le Mode 8nce a"ain, :ibble ;ode reDuires the use of the proper C code to ensure the data is properly transferred. This time the =& :ibble read first, followed by the ;& nibble. Finally, the =& :ibble is shifted and the two are combined@ outportb(CONTROL, inportb(CONTROL) | 0x0)); //Sele*t LS Nibble( ) a = (inportb(ST T!S) & 0xF0); //Rea" LS Nibble a = a ++ 4; //S#i,t LS Nibble outportb(CONTROL, inportb(CONTROL) & 0xF-); //Sele*t $S Nibble(.) a = a | (inportb(ST T!S) & 0xF0); //Rea" $S Nibble b/te = b/te % 0x&&; Co'bine t#e $S & LS Nibble( For more information please !isit the followin" link@ http@--www.beyondlo"ic.or"-spp-parallel.htmA' Enhanced Parallel Port Mode (EPP) The 9PP ;ode is far more effecti!e than the Compatibility ;ode. .ecause it uses hardware to "enerate timin", rather than software, it can reach transfer speeds from (( B.-s to 2 ;.-s. This is the most common mode used for the hobbyist because the 9PP Port "enerates and controls all of the transfers to and from the peripheral. The 9PP ;ode enables a new set of re"isters, in addition to the 3 a!ailable in Compatibility ;ode. These include a new address 4 data port and se!eral others, summariEed in the table below@

Address .ase / ( .ase / $ .ase / 2 .ase / 3 .ase / 2 .ase / .ase / 1 .ase / *

Port Name Data Port +&PP, &tatus Port +&PP, Control Port +&PP, 7ddress Port +9PP, Data Port +9PP, <ndefined +$1-32bit Transfers, <ndefined +32bit Transfers, <ndefined +32bit Transfers, Ta#le +: (PP Registers

Read/

rite

%rite 0ead %rite 0ead-%rite 0ead-%rite -

5n addition, the existin" pins on the D-Type 2 Pin Female Connector ha!e different functions when in 9PP ;ode. The table below summariEes the new functions of each pin@ Pin $ 2-# $( $$ $2 $3 $2 $ $1 $* $'-2 SPP &trobe Data (-* 7ck .usy P 8ut &elect =inefeed 9rror 5nitialiEe &elect Fround (PP %rite Data (-* 5nterrupt %ait &pare &pare Data &trobe &pare 0eset 7ddress &trobe Fround I/O Function

8 7 low indicates a %rite, >i"h indicates a 0ead 5-8 Data .us. .i-directional 5 5 5 5 5 5nterrupt =ine 9PP cycle started when low, finished when hi"h. &pare - :ot <sed in 9PP >andshake &pare - :ot <sed in 9PP >andshake &pare - :ote used in 9PP >andshake

8 %hen =ow, indicates Data transfer 8 0eset - 7cti!e =ow 8 %hen low, indicates 7ddress transfer Fround

Ta#le ,: Pin Assignments For (n-anced Parallel Port Connector! =ike the cycles described in the Compatibility ;ode section, the 9PP ;ode reDuires confi"uration before a read or write cycle can be"in. 7"ain this is accomplished by writin" xxxx($((( to the Control Port. 7 timin" dia"ram for a typical write cycle is shown in the fi"ure below, howe!er, a more detailed description can be found at@ http@--www.beyondlo"ic.or"-epp-epp.htm

Figure +: (PP $ata

rite C)cle

5n this case, a data write statement would reDuire the followin" steps@ $. 2. 3. 2. . 1. *. The C code write to 9PP Data 0e"ister 2 +.ase /2,. The %rite line is pulled low indicatin" a write operation. Data is placed on Data =ines (-*. The Data &trobe is asserted if %ait is low >ost waits for 7cknowled"ment by %ait "oin" hi"h. Data &trobe is de-asserted. 9PP Data %rite Cycle 9nds.

Extended Capabilities Mode (ECP) The 9CP ;ode has transfer speeds that match that of the 9PP ;ode, howe!er, it has a few extra features worth notin". 9CP ;ode uses a F5F8 buffer for transferrin" or recei!in" data., it uses a real time data compression called 0un =en"th 9ncodin" +0=9, to achie!e compression ratios up to 12@$, and it has an 9xtended Controller 0e"ister +9C0, that allows for different operations within 9CP ;ode. For further details about the capabilities of this PC Parallel Port ;ode, please !isit the followin" link@ http@--www.beyondlo"ic.or"-ecp-ecp.htm