MICRODEVICES

MOSFETs Metal Oxide Field Effect Transistors n MOSFET xax L contact D n+ pSubstrate=bulk=body
G

gate oxide
S

S n+

G L D n+ p-

n+

n+ diffusion

The most important geometrical parameters: the gate oxide thickness xox the channel length L the aspect ratio W/L the channel with W

Remarks L, L The effective channel length L is smaller than minimum value specified by the design rule L L < L W/L The aspect ratio is a layout geometrical parameter. The central problem in CMOS design is finding the aspect ratios that give the desired performance of the circuit. Symbols for MOSFETs
D B G n+ S n n+ pG D B p+ nS p+ p+ pn junction

nMOS
D

MOSFET
D B G G S connected to VSS= VA
-

pMOS
S connected B to VDD= VA D
+

p channel MOSFET

G S

nMOSFET. Regions of operations

ID vDS= vDsat linear active avalanche increasing vGS vDS subthreshold
cutoff

D G vGS S vDS B V-

vBS0

1. Cutoff region: What is the threshold potential? - The gate source voltage at which the channel current rises above the OFF state leakage level vGS<VTh - the device acts as an open-circuit or a ID = 0 ID = the offset leakage SWITCH in the OFF state current - the impedance between drain and source is extremely high (up to 1012 )

The threshold voltage Vth is established in the fabrication sequence. It depends on xox , the dropping densities of G and B and the physical properties of the source bulk voltage VBS .

VTh = VTh0 + ( - VBS - )

(1)

VTh0 the zero body bias threshold voltage (VBS = 0) VTh0 = 0.5 1V; it can be 0.35V for nanodevices the body bias factor with units of [V1/2] or the body effect parameter n = (0.1 1.5) V ; p = (0.4 2) V the bulk Fermi potential [V]

2. The linear region nonsaturation or triode region

The MOST behaves as a voltage controlled resistor (VCR) or as a SWITCH in the OH

state.
ron

ID =

v KW (v GS -VTh - DS )v DS L 2

(2)

I D (v GS -VTh )v DS for v DS =2 ( v GS -VTh ) I D = G (v GS ) v DS

VDS >VTh vDS < vGS - VTh

ID ~ vDS where =

KW - the transconductance factor L

vGS vDS

K the process transconductance [A/V2] E.g. Process 0.8 : Kn ~ 90A / V2 Kp ~ 30A / V2 K = Cox

- the carrier surface mobility Cox = ox / xox the gate oxide capacitance per unit area ox = the permittivity of the oxide xox = the oxide thickness W, L = the effective channel width and length respectively G(vGS) = (vGS - VTh) is a voltage controlled conductance (by vGS)
3. The active region

The MOST behaves as a current source. It is a voltage controlled current source VCCS

vGS

iD

In the active region: I D f(v DS ) , MOSFET may be biased to the

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Strong, moderate or weak inversion:

IDA 100 10 subtreshold weak moderate 0 20mV 80-220mV vGS - VTh

strong

a) weak inversion: vGS VTh < 20 mV A small number of free carriers flow and form a - diffusion current MOSFET operates like a bipolar transistor
ID I D =I Do vBS = 0 vBS < 0 w vGS nVT (1-k)vBS VT ; n=1.6,.1.8 ; k =1/n e e L

subthreshold region
-100mK vGS - VTh < 0 vGS b) moderate inversion

vGS VTh + 20mV ...VTh + (80 220mV )

Drift and diffusion currents in channel are comparable

c) strong inversion
vGS > VTh +220mV drift current dominates the ID components:

ID =

Kw (v GS - VTh )2 (1 + v DS ) 2L

(3)

the channel length modulation factor [V-1] ~ (0.005, 0.06)V-1

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d vGS ID

The MOST behaves as a VCCS : any increase of vDS will cause no increase of ID or only a slight one and the value of ID is function of vGS.

s The parameter determines the slope in the output characteristic. For short channel lengths this parameter is larger than for long ID real ideal vDS
channels lengths. Thus depends on L :

1 VE L

VE is the Early voltage per unit channel length.

4. The avalanche region is also called breakdown mode. ID increases very steeply with

increasing vDS .
The border between saturation and non-saturation is given by vDSsat , that is

the value of vDS at which ID in equations (2) and (3) achieves the same value
i D = (vGS -VTh v DS 1 ) v DS (vGS -VTh ) 2 2 2 vDS = vGS -VTh = v DSsat 2 KW I DSsat = v DSsat ; = 2 L

Small signal models of the MOSFETs

a) Non-saturation region (called also linear, triode, voltage controlled resistance region) iD = v KW LW (vGS -VTh - DS )v DS (vGS -VTh )v DS L 2 L for vDS << (vGS-VTh) => iD depends

linearly on vDS .

vds d id vgs s r = 1/g

g=

i D v DS

=
VGS

KW (VGS -VTh )=f(VGS ) L

r=

L 1 , KW VGS -VTh

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MOSFETs behaves as a resistance that decreases with the aspect ratio W/L, and also by increasing VGS. It can be controlled by VGS . b) saturation region in strong inversion
iD = Lw (vGS VTh ) 2 (1 + vGS ) = f (vGS , v BS , v DS ) 2L

The drain current is strongly influenced by vGS , but also by vBS (through VTh) and vDS. The magnitudes that put into evidence this effect are transconductance and conductance 1) g m =
i D vGS
is v BS

=
Quiescent point

2I D 2KWI D KW (VGS -VTh ) = = L VGS -VTh L

(4)

2) g mb =

=g m
Q

=(0.1,...0.3)g m 2 -VBS

(5)

3) g out =

i D v DS

= I D ; rout = rds =
Q

1 I D

(6)

Active MOST in strong inversion Low frequency small signal model

g vg vgs gm s vbs b gm vbs

rds

ids vds

rds =
i ds = g m v gs + g mb v bs + i ds g m vgs v ds rds

1 = rout g out

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Small signal h.f. model

Parasitic capacitances are aided to l.f. model Cp gate oxide capacitances depletion capacitances
Gate
CGDo CGS CGSo CGDo

gate oxide D
CDB

Drain n
CDB

channel n

B Source n
CBC CSB

G B

Bulk

CGS

CSB

CGDo, CGC, CGSo = parallel plate capacitors. The gate capacitance is the total input capacitance. CG = CGx = Co xWL' (7)

L' = the drawn channel length

Cox = the capacitance per unit area of the Gate Oxide channel capacitor CGDo, CGSo correspond to the GD and GS overlap capacitors due to unwanted diffusion under the gate. CGB, CSB, CCB = junction capacitors dependent on the reverse voltage The junction capacitances:

Cj=

C jo A VR 1+ o
m

(8)

M grading parameter A the total junction area Cjo the zero bias junction capacitance per cm2 VR the reverse voltage o the potential barrier

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g vgs CCS s

CGD

d ro gm vgs vbs CSB B gmb vbs

d vds

CDB

The task of laying out the IC is given to a layout designer. He has to understand the parasitic involved in the layout. Parasitic are the stray capacitances, inductances, pn junctions and bipolar transistors with the associated problems (break down, stored charges, latch-up).
Latch-up in CMOS technology

The cross section of a typical CMOS device pair illustrates a pn pn sandwich structure.

5
+

p p

Dn n R1

G1 n
2

V+
4

vo G2 p R2 p Dp n well for p MOSFET

n
3

V
+

G2

Sp pMOS Dp v Dn o nMOS

R2 V+

5 R1 p

4 p

G1 Sn

pnpn parasitic structure

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In normal operation all the pn junction in the structure are reverse biased. If for some reason the two bipolar transistors enter the active region the circuit has a large positive feedback and both transistors conduct heavily. The structure is similar to that of a Silicon Controlled Rectifier (SCR) used in power control. In CMOS this phenomenon is called latchup and consists in a destructive break down effect. In power electronics a SCR does not break down, but switches on and remains in conduction (latch-up effect).

IC NPN TRANSISTOR AND OTHER DEVICES IN BIPOLAR TECHNOLOGY

The optimized device in bipolar technology is npn transistor. The cross section of a typical npn transistor in a junction-isolated process is shown in the following figure:

p np- substrate

n+ w

p+

P+

p n-

p+

p p+ n p

buried layer substrate pnpn Lateral pnpT

vertical pnpT (substrate T)

The same collector, base and emitter layers serve to realize the other devices in the IC. They have the electrical parameters of the npn transistor and the same depth. Therefore the resulted parameters of these devices are very poor and the realist analog ICs used no pnp transistors. Because these pnp devices utilize the tightly doped n-type epytaxial material as the base of the transistor, they are inferior to the npn devices in frequency response and high current behavior: parameter current gain transition frequency F fT tenth of GHz 16 npn 120 500MHz lateral pnp 50 5MHz

Low frequency small signal model active region

i C = ISe vBE
VT

(1+ vCE

VE ) ; IC = F I B

(9)

gm =

i C I = C v BE Q VT

(10)

go =

i C I = C v CE Q VE

ro =

VE IC

(11)

r =

v BE i B

v BE i C = =r i C o g m be

(12)

= g m r

(13)

gm transconductance ; ro output resistance ; r input shunt resistance b vb e

r

c
ro

vce

gm vbe

High frequency small signal model takes into account the parasites (resistive and

capacitive parasites) r b rb
C C r

rc v1 e
re

g m v1

ro

CCS

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rb, rc, re the finite resistance of the silicon between the top contacts on the transistor and the active base, collector regions or emitter.

C, C , CCS The capacitors correspond to the b-e, b-c, and c-s junctions and are depletion capacitances.

r is very large (much layer than X ), re very small (we may neglect it) rc is large enough to be taken into account at large currents.

RESISTORS AND CAPACITORS

Resistors. Silicon devices are constructed from diffusion layers. If the pn junctions

formed by there diffusion are reverse biased, then the layer is electrically isolated from the underlying material. The electrical parameter of the layer is the sheet resistance. L length ; W widh ; t thickness W R= L tW
t

(15)

If L = W

R=R =

(16)

R is the sheet resistance of the layer and has the units of ohms per square / ,

It is the resistance of any square sheet of material with thickness t. In bipolar ICs resistor structures includes base-diffused, emitter-diffused, ion-implanted pinch, epitaxial and pinched epitaxial resistors. In MOS ICs resistors include diffused, polysilicon and well resistors.
Capacitors

Capacitance structures include MOS and junction capacitors. (see (7) and (8)) Capacitors play a much more important role in MOS technology than they do in bipolar technology. Because of the MOS infinite input resistance, MOS amps sense voltages stored continuously and nondestructively on capacitors. These one can be used to perform many functions traditionally performed by resistors. Capacitors have poly-poly, metal-poly, metal-silicon and silicon-silicon plates.

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