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Memory Devices

Wen-Hung Liao, Ph.D. 6/6/2001

Memory Terminology
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Memory cell : a device used to store a single bit (0 or 1). Examples: FF, charged capacitor, a single spot on a magnetic disk or tape. Memory word : a group of bits (cells) in a memory that represents instructions or data of some type. Byte: a special term used for a group of 8 bits. Capacity : a way of specifying how many bits of data can be stored in a particular memory device. Example: 4096 20-bit words = 4K x20 Density : another term for capacity. Often with reference to space.

Memory Terminology(cont d)
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Address : A number that identifies the location of a word in memory. (Figure 11-2) Read operation : the operation whereby the binary word stored in a specific memory location is sensed and then transferred to another device. Write operation : the operation whereby a new word is placed into a particular memory location. Access time: amount of time required to perform a read operation. Volatile memory : any type of memory that requires the application of electrical power in order to store information.

Memory Terminology (cont d)


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Random Access Memory (RAM): memory in which the actual physical location of memory word has no effect on how long it takes to read from or write into that location. Sequential Access Memory : a type of memory in which the access time is not constant but varies depending on the address location. Read/Write Memory : any memory that can be read from and written into with equal ease. Read-Only Memory(ROM)

Memory Terminology (cont d)


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Static memory devices : semiconductor memory devices in which the stored data will remain permanently stored as long as power is applied. Dynamic memory devices : data need to be periodically refreshed. Main memory : also referred to as the computers working memory. Auxiliary memory : also referred to as mass storage. Always nonvolatile.

General Memory Operation


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Select the address in memory that is being accessed for a read or write operation. Select either a read or a write operation to be performed. Supply the input data to be stored in memory during a write operation. Hold the output data coming from memory during a read operation. Enable (or disable) the memory so that it will (or will not) respond to the address inputs and read/write command.

Address Inputs
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N words log2 N address inputs The R/W input Memory Enable: Chip Enable, Chip Select

CPU-Memory Connections
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Figure 11-5. Address Bus: a unidirectional bus that carries the binary outputs from the CPU to the memory IC to select one memory location. Data Bus: a bi-directional bus that carries data between the CPU and the memory IC. Control bus: carries control signals from the CPU to the memory IC.

Read-Only Memory
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Designed to hold data that either are permanent or will not change frequently. During normal operation, no data can be written into a ROM, but data can be read from ROM. The process of entering data is called programming or burning-in the ROM. All ROMs are nonvolatile.

ROM Block Diagram


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Figure 11-6 shows a 16x8 ROM. 4 address inputs, 8 data outputs. CS: Chip Select. The Read operation.

ROM Architecture
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Figure 11-7: architecture of a 16x8 ROM. Register array Row decoder Column decoder Output buffers.

ROM Timing
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access time, time interval between the application of a ROMs input and the appearance of the data outputs during a read operation. tOE: output enable time, the delay between the CS input and the valid data output. Refer to Figure 11-8.

Types of ROMs
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Mask-Programmed ROM: cannot be reprogrammed (Figure 11-9). Programmable ROMs (PROMs): Figure 11-11. Erasable Programmable ROM (EPROM): use UV lights to erase all cells at the same time. (15-20 minutes.) Vpp: programming voltage. Figure 11-12. Electrically Erasable PROM (EEPROM): Figure 11-13, allows rapid in-circuit erasure and reprogramming of individual bytes, suffer from low density and higher cost. CD-ROM

Flash Memory
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Figure 11-14 shows the trade-offs for the various semiconductor nonvolatile memories. Flash memory aims to provide in-circuit electrical erasability, high-speed access, high density, low cost. Erase mode: bulk erase, sector erase. The 28F256A CMOS flash memory IC: Figure 11-15. Figure 11-16: functional diagram of the 28F256A chip.

28F256A IC
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Read command Set-up Erase/Erase command Erase-verify command Set-up Program/Program command Program-verify command

ROM Applications
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Firmware Bootstrap memory Data tables Data converter Function generator Auxiliary storage: flash memoy.

Programmable Logic Devices (PLD)


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Contains large number of gates, FFs and registers that are interconnected on the chip. Many of the connections are fusible links that can be broken. The IC is said to be programmable because the specific function of the IC is determined by the selective breaking of some interconnections.

PLD vs. PAL


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Figure 11-19: two input variables A and B, an array of AND gates, array of OR gates. PLD symbology: Figure 11-20. PLD architecture--- the PROM (Figure 11-21) Programmable Array Logic (PAL): inputs to the AND gates are programmable where as inputs to the OR gates are hard-wired. (Figure 11-22) Polarity fuse: output can be inverted.

Semiconductor RAM
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When the term RAM is used with semiconductors memories, it is usually taken to mean read/write memory as opposed to ROM. RAM is used for temporary storage of programs and data. RAM is volatile. Standby mode saves power.

RAM Architecture
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Consisting of a number of registers, each storing a single data word, and each having a unique address. Read operation Write operation Chip Select Common input/output pins

Static RAM (SRAM)


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Stores data as long as power is applied. Static RAM timing Read cycle (Figure 11-28a) Write cycle (Figure 11-28b) Actual SRAM chip: MCM6264 CMOS 8Kx8

Dynamic RAM (DRAM)


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Needs to be refreshed every 2, 4,or 8 ms. DRAM structures and operation (Figure 1131,32) Address multiplexing DRAM read cycle (Figure 11-36) DRAM write cycle (Figure 11-37)

DRAM Refreshing
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DRAM chips are designed so that whenever a read operation is performed on a cell, all of the cells in that row will be refreshed. Two refresh modes:

Burst refresh: normal memory operation is suspended, and each row of the DRAM is refreshed in succession until all rows have been refreshed. Distributed refresh: row refreshing in interspersed with the normal operation.

Expanding Word Size and Capacity


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Expanding word size: connecting two 16x4 RAMs for a 16x8 module. (Figure 11-40) Expanding capacity: connecting two 16x4 chips for a 32x4 memory (Figure 11-42)

Special Memory Functions


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Power-down storage Cache memory First-in, First-out memory

Power Requirements
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Every IC needs a certain amount of electrical power to operate. Vcc (TTL) VDD(MOS) Power dissipation determined by Icc and Vcc. Average Icc(avg)= (ICCH + ICCL)/2 PD(avg) = Icc(avg) x Vcc

Speed-Power Product
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Desirable properties:

Short propagation delays (high speed) Low power dissipation

Speed-power product measures the combined effect.

Noise Immunity
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What happens if noise causes the input voltage to drop below VIH(min) or rise above VIL(max)? The noise immunity of a logic circuit refers to the circuits ability to tolerate noise without causing spurious changes in the output voltage. Noise margin: Figure 8-4. VNH=VOH(min)-VIH(min) VNL=VIL(max)-VOL(max) Example 8-1.