BHARAT ELECTRONICS LIMITED (A Govt.

of India Enterprise under the Ministry of Defence) Bharat Electronics Limited, Navaratna and a premier professional Electronics Company requires outstanding M. Tech Design Engineers with experience for Components SBU of BEL Bangalore unit.
Sl. No. 1 No. of posts 01 24900-50500 Basic pay/Pay scale (Rs.) CTC (approx.) 11 Lakhs p.a Upper age limit as on 01.12.2013

Designation

Grade

Deputy Manager (D&E) Deputy Engineer (D&E)

E-IV

35 years

E-II

10

16400-40500

7.4 Lakhs p.a

29 years

* Additional increments and service weightage will be granted to meritorious candidates at the discretion of the Management. JOB DESCRIPTION 1. DEPUTY MANAGER (D&E) No. of posts: 01 Qualification: M. Tech in Metallurgy/Material Science/Ceramic Engineering from any AICTE approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates. Experience: 5 years post qualification experience in Chemical Vapour Deposition (CVD), Hot Isostatic Pressing (HIP), Transparent Ceramics, Material Characterization, Ceramic Powder Processing, and Antireflection Coatings. Responsibilities: Absorbing the technology for optical coatings from a TOT partner, setting of the manufacturing facility, operation of CVD for ZnS dome production, Development of transparent Magnesium Aluminate Spinel, Magnesium Aluminate Spinel processing and Hot Isostatic Pressing, Alumina substrate fabrication through slip casting for Zinc Sulphide (ZnS) dome, quality control and certification of ceramics for critical properties, planning and supporting the production, managing the manpower and quality control, guiding and supervision of the team members in a result oriented manner.

2. DEPUTY ENGINEER (D&E) FRONT END DESIGN & VERIFICATION ENGINEER No. of posts: 02 Qualification: M.Tech in Micro Electronics/Electronic from any AICTE approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates. Experience: 2 years post qualification experience in working with ARM processor IP and other IPs (PCIe, Ethernet, CAN, USB, GPU etc.), HDLs (Verilog, VHDL) with VERA/System C/System Verilog, IP validation, HVL methodology (UVM, OVM), testbench automation, bug tracking and regression mechanisms, develop and integrate reusable test environments, system level scenarios, performance measurements, ABV, power aware simulations, Gate Level Functional Simulations (GLS), develop wrappers, test cases, coverage, Scripting (Perl, TCL), project verification using state of art verification tools, EDA tools and methodologies. Desirable Requirement: Design verification with ARM, APB, AHB & AXI, peripherals. Experience in verification for designs with a clock of 1 GHz or higher. 3. DEPUTY ENGINEER (D&E) ASIC IMPLEMENTATION ENGINEER No. of posts: 01 Qualification: M.Tech in Micro Electronics/Electronic System from any AICTE approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates. Experience: 2 years of post qualification experience in Design synthesis of RTL designs and block/chip level timing constraints, formal verification at RTL and netlist level, timing closure methodologies, for 65nm and below with complexity of more than 10 million gates, implementing DFT techniques (Memory BIST/Scan/on chip compression/At-speed scan/test-clocking/boundary scan/pin-muxing/logic BIST) on complex SOCs to improve testability, test vector (stuck at/At-speed/path delay/SDD/IDDQ/bridging fault) generation with high test coverage and DFT simulations at gate level with timing (SDF), scripting (perl, TCL). Desirable Requirement: Worked in 40/45 nm technology node, knowledge of lowpower aware implementation, experience in post-layout STA closure and timing ECOs.

4. DEPUTY ENGINEER (D&E) PHYSICAL DESIGN ENGINEER No. of posts: 03 Qualification: M.Tech in Micro Electronics/Electronic System from any AICTE approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates. Experience: 2 years of post qualification experience in place and route methodologies (floor planning, placement, CTS, P&R, power routing) with timing convergence and solving PNR issues, using hard marco IPs, standard cell P&R, foundry and third party I/Os, tapeouts for 65nm and below process node with complexity of at least 10 million gates, usage of state of the art automated P&R tools of MG/Cadence/Magma/Synopsistools for physical design and verification, RC extraction, parasitic extraction, IR drop analysis, thermal analysis/antenna checks/optical correction, LVS/DRC/ERC and other physical verification checks for 65nm and below, signoff task methodologies, including timing closure with crosstalk and On Chip Variation (OCV) under multimode multicomer condition, scripting (perl, TCL). Desirable Requirement: 2 years of post qualification experience in 40nm node designs, knowledge of low power designs (power gating, multi-Vt flow, power supply management etc. developing and implementing timing ECOs including effect on congestion/routing power nodes. 5. DEPUTY ENGINEER (D&E) MICROWAVE ENGINEERS No. of posts: 02 Qualification: M.Tech in Micro Electronics & Communication (Microwave) from any AICTE approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates. Experience: 2 years of post qualification experience in design experience of klystrons, TWTs and Magnetrons will be preferred.
6. DEPUTY ENGINEER (D&E) SEMICONDUCTOR PROCESS ENGINEERS

No. of posts: 02 Qualification: M.Tech in Solid Sate Technology or Micro Electronics Engineering from any AICTE approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates.

Experience: 2 years of post qualification experience in high temperature diffusion furnace operation, PECVD, LPCVD processes used in semiconductor manufacturing, Photolithographic process, chemical etching and cleaning related to semiconductor process, knowledge on semiconductor devices and process simulators. Desirable Requirement: Project work in MEMS or semiconductor devices. Pay & Benefits: In addition to Basic pay, other allowances like dearness allowance, HRA and also eligible for perks of 48% on Annual Basic Pay. Reimbursement of medical expenses, Performance Related Pay, Group insurance as per Company rules, PF, gratuity etc., will be part of the remuneration package. One year service weightage will be extended to the selected candidates

Bond: Candidates who selected for the post of Deputy Engineer have to execute a bond to serve minimum period of three years or to pay a sum of Rs. 3,00,000/- (Three lakhs) to the Company. Mode of Selection: The applications will be scrutinised and applicants meeting the above criteria will be called to appear at the written test or interview depends on the number of applications received.

General Conditions: Reservation / relaxation for SC/ST/OBC/PWD will be as per Government directives. Applications of GEN/OBC candidates should be accompanied by a crossed Demand Draft drawn on any scheduled bank (preferably SBI) for Rs.300/- (SC/ST/PWD applicants are exempted) in favour of Bharat Electronics Limited, Bangalore. The applicant is required to write his/her name at the right bottom corner on the reverse of Demand Draft. Candidate employed in PSUs / Govt. Organizations should submit the application through proper channel or produce No Objection Certificate at the time of the interview. Candidates are required to possess at least one valid e-mail id which is to be entered in the application form. Candidates shortlisted for the written test/interview will be informed through email regarding the date, time and venue for the written test and interview to the id that is furnished in the application. BEL will not be responsible for bouncing of any e-mail sent to the candidate These posts are identified to be filled up by external candidates only, through direct recruitment. Therefore, applications from internal candidates will not be considered. BEL reserves the right to increase/decrease the number of vacancies to be filled on actual requirement at the time of selection and to cancel the advertisement and/or the entire selection process at any stage. Deserving candidates may be extended relaxation in age / experience based on merit at the discretion of the Management.

Outstation SC/ST/PWD candidates will be reimbursed 2 nd class to and fro train fare by the shortest route (from their correspondence address) to the written test/interview venue, subject to production of railway ticket/receipts as per Company rules. Candidates belong to GEN/OBC will be reimbursed train fare, if they are shortlisted for the interview, subject to production of railway ticket/receipts.

Applications that are incomplete, not in the prescribed format, not legible, without the required enclosures will be summarily rejected without assigning any reasons and no correspondence in this regard will be entertained. Only Indian nationals need apply. Interested candidates may send the applications through post / courier, superscribing on the envelope the post applied for, in the downloadable application format enclosing a recent passport size photograph along with demand draft (if applicable) self attested copies of SSLC / Matriculation Certificate (proof of age), Marks cards for having passed all semesters / years of BE/B.Tech, ME/M.Tech examination, BE/B.Tech Degree certificate, ME/M.Tech Degree certificate, certificate from previous employer regarding experience, Caste Certificate, PWD Certificate (if applicable) and other relevant certificates. Candidates applying for the above posts should send their applications to the Deputy General Manager (HR) / Components & EM, Bharat Electronics Limited, Jalahalli Post, Bangalore 560 013 on or before 31.01.2014.

BEL reserves the right to debar/disqualify any candidates at any stage of the selection process for any reason what so ever. Canvassing in any form will result in disqualification.