Chapter 7 Notes

7.1 Synchronous Sequential Systems - A combinational system output depends only upon the current inputs. A sequential system output depends upon present inputs and state. How it arrived at the present state was determined by inputs previous states, something like following a path with input at each turn where to go next. A simple example is a counter that counts 0-1-2-3-0-1 etc. It has no inputs, the output and next state depends solely upon its present state, in State A the output is 00, State B the output is 01, etc. The state diagram showing the state, output, and transitions is below.
The state description of the sequential system is: Input: None other than clock. Output: z(t) element of {00,01,10,11} State: s(t) element of {A, B, C, D} Initial: s(0)=A Functions:
Present s(t) A B C D | | | | | | Next s(t+1) B C D A | | | | | | Output z(t) 00 01 10 11

Moore Machine - Output depends only upon current state. Mod-4 counter.

Synchronous sequential systems change from the present state to the next state at discrete time intervals defined by a synchronizing clock signal. The state change occurs either on the rising or falling clock edge. The wave form above shows that the state and output changes with each rising clock edge. Synchronous Systems in VHDL - The VHDL that would correspond to the above diagram and produce the wave form is given below: Note that clk'EVENT AND clk='1' means that a change occurred in the clksignal and the clk signal is '1'.

ENTITY Mod4 IS PORT ( clk : IN BIT ; OUTPUT : OUT BIT_VECTOR(1 DOWNTO 0)); END MOD4; ARCHITECTURE behavioral OF MOD4 IS TYPE STATE_TYPE IS (A, B, C, D); SIGNAL presentS, nextS: STATE_TYPE; BEGIN PROCESS (clk) BEGIN -- Present to Next State -- change on RISING clock edge

IF clk'EVENT AND clk = '1' THEN CASE presentS IS WHEN A => nextS <= B; WHEN B => nextS <= C; WHEN C => nextS <= D; WHEN D => nextS <= A; END CASE; END IF; END PROCESS; PROCESS (nextS) -- present State becomes next state BEGIN -- Output computed based on present state only presentS <= nextS; CASE presentS IS WHEN A => Output <= "00"; WHEN B => Output <= "01"; WHEN C => Output <= "10"; WHEN D => Output <= "11"; END CASE; END PROCESS; END behavioral;

Moore Machine

Synchronous Sequential Systems with Input - Most interesting sequential systems require some external input for control of which state is executed next. Synchronized systems change from the present state to the nextstate on an active clock. The next state is determined based upon the present state and the input at the the active clock edge.

The state description of the sequential system is: Input: x(t) element of {0,1} Output: z(t) element of {0,1} State: s(t) element of {A, B, C, D} Initial: s(0)=A Functions:
Present | s(t) | | A | B | C | D | | Next, Output Input x(t) 0 1 A,0 B,0 C,0 B,0 A,0 D,0 A,0 A,1 s(t+1), z(t)

Mealy Machine - Output depends upon present state and input.

The above example is a sequential system that detects the input sequence 1011, outputting a 0 when the sequence has not been detected, outputting a 1 when the sequence has been detected. The following timing diagram illustrates that on the rising clock the inputs and the present state determine the next state and the output. In this example, the sequence 1011 was detected, resulting in an output of 1 while in State D.

An example where the input sequence is 1110... illustrates that the system stays in State B as long as in State B and the input remains 1. It is important to note that the input and present state determine the next state. The decision of the next state is made at the moment of the rising clock signal.

ENTITY DetectSq IS PORT ( CLK : IN BIT ; X : IN BIT; OUTPUT : OUT BIT); END DetectSq; ARCHITECTURE behavioral OF DetectSq IS TYPE STATE_TYPE IS (A, B, C, D); SIGNAL presentS, nextS: STATE_TYPE; BEGIN PROCESS (clk) BEGIN -- Present to Next State -- change on RISING clock edge

IF clk'EVENT AND clk = '1' THEN CASE presentS IS WHEN A => IF X='1' THEN nextS <= B; ELSE nextS <= A; END IF; WHEN B => IF X='0' THEN nextS <= C; ELSE nextS <= B; END IF; WHEN C => IF X='1' THEN nextS <= D; ELSE nextS <= A; END IF; WHEN D => nextS <= A; END CASE; END IF; END PROCESS; PROCESS (nextS) BEGIN -- present State becomes next state -- Output computed based on present state and input only

presentS <= nextS; CASE presentS IS WHEN A => Output <= '0'; WHEN B => Output <= '0'; WHEN C => Output <= '0'; WHEN D => IF X='1' THEN Output <= '1'; ELSE OUTPUT <= '0'; END IF; END CASE; END PROCESS; END behavioral; Sequence Detector for 1011

7.2 Representation of the State Transition and Output Functions - The transition and output functions can be represented graphically. The representation conventions are:

Unconditional transition from State A to State B, no output. Moore machine Unconditional transition from State A to State B. Output 00 while in State A, output 01 while in State B. Moore machine Conditional transfer from State A to State B when input is 1. Output 00 while in State A, output 01 while in State B. Mealy machine Conditional transfer from State A to State B when input is 1, from A to A when input is 0. Output 00 while in State A and input is 0, output 01 while in State A and input is 1. Graphical Representation Conventions

Example: Consider the definition of a machine to determine the parity (whether an even or odd number of 1's have been received) of a sequence of 0's and 1's. The machine outputs 0 when parity is even and 1 when odd. The sequence 101 would produce a parity output of 1 while the sequence 1001000010001000 would produce a parity output of 0. The state description is:

Input: x(t) element of {0,1} Output: z(t) element of {0,1} State: s(t) element of {Even, Odd} Initial: s(0) = Even Function: z(t) = 1 if x(0,t) contains odd number of 1's otherwise 0
Present | s(t) | | Even | Odd | Next, Output Input x(t) 0 1 Even,0 Odd, 1 Odd,1 Even,0

| s(t+1), z(t) Parity Generator State Diagram

7.3 Time Behavior and Finite State Machines The state and output sequences and timing diagram of the parity generator for the input sequence x(0,7) = 10001011 is:
t x s z | | | | 0 1 Even 0 1 0 Odd 1 2 0 Odd 1 3 0 Odd 1 4 1 Odd 1 5 0 Even 0 6 1 Even 0 7 8 1 Odd Even 1 0

7.4 Finite Memory Sequential Systems

Finite State Machines - Have a finite number of states. The parity generator example has two states so is a finite state machine (FSM). Finite Memory - Depends only upon a finite number of inputs, the parity generator is not a finite memory system since it depends upon all previous inputs.

7.5 Controllers - Produce control signals (outputs) that determine the action of another part of the system. Autonomous controllers have no inputs, nonautonomous controllers respond to inputs. The Mod-4 counter is an example of an autonomous controller as it has no inputs other than the clock.

In the diagram below the output, z=00, 01, 10, 11, etc. is from the Mod-4 counter. When a comparator detects the 11 is output, a bell is rang, otherwise a light is turned on for the other counts. Additional logic determines when the output of the Mod-4 counter is z=11. The counter is unchanged but through its output acts as a controller. Alternatively, the Mod-4 counter could have an additional output that was true when in State D.

Autonomous Controller

As a non-autonomous example, consider a Mod-4 counter that outputs a control signal true (1) when the count output z =11 and a pushbutton is down (true or 1), other logic of the system rings a bell. Otherwise the bell is silent.

Non-autonomous Controller

Input: PB(t) element of {0,1} Output: Bell(t) element of {0,1} State: s(t) element of {A, B, C, D} Initial: s(0)=A
Functions: Present | Next, Output s(t) | Input PB(t) | 0 1 A | B, 0 B, B | C, 0 C, C | D, 0 D, D | A, 0 A,

0 0 0 1

| s(t+1), Bell(t) Non-autonomous Controller State Description

7.6 Equivalent Sequential Systems and Minimization of the Number of States The key insight required for minimization is that if, given the same inputs, two systems produce the same output, the systems are equivalent, that is one can replace the other. A simplistic example is given in the following diagram at left where State A and B produce the same output given the same input, the more complex diagram may be functionally replaced by the simpler at right.

Equivalent State Diagrams

Distinguishable states - Essentially, two states, A and B, are different if a given input produces a different output for A than for B.

Equivalent states - A and B states are equivalent if the same output is produced by either given the same input.

Example: Given the transition and output functions of:

Minimization Procedure 1. Group states with identical outputs into classes.

(a,b,c,e), (d,h), (f), (g) 2. Number each class.

1=(a,b,c,e), 2=(d,h), 3=(f), 4=(g) 3. Rewrite transition table for each input from a state to a class using the class numbers.
1 2 3 4 P1|(a b c e)|(d h)|(f)|(g) x=0| 3 2 3 2 | 4 4 | 3 | 4 x=1| 1 1 1 1 | 1 1 | 1 | 2

Problem 7.15 Page 192 | Input PS| x=0 x=1 a | f,0 b,0 b | d,0 c,0 c | f,0 e,0 d | g,1 a,0 e | d,0 c,0 f | f,1 b,1 g | g,0 h,1 h | g,1 a,0 |NS, Output

4. Group states with identical state to class transitions into classes, and renumber classes.

1=(a,c), 2=(b,e), 3=(d,h), 4=(f), 5=(g) 5. Rewrite transition table for each input from a state to a class using the class numbers.
1 2 3 4 5 P2|(a c)|(b e)|(d h)|(f)|(g) x=0| 4 4 | 3 3 | 5 5 | | x=1| 2 2 | 1 1 | 1 1 | |

6. Continue until there is no change in the groupings, indicating minimum number of states.
1 2 3 4 5 P3|(a c)|(b e)|(d h)|(f)|(g) x=0| 4 4 | 3 3 | 5 5 | | x=1| 2 2 | 1 1 | 1 1 | |

7. Write the state transition table with one state from each class since

each class member is equivalent to other in the class.

PS|x=0 a |f,0 b |d,0 d |g,1 f |f,1 x=1 b,0 a,0 a,0 b,1

g |g,0 d,1 State Minimization Steps

7.7 Binary Specification of Sequential Systems - Assignment of binary codes to state, input, and output.
PS|Input x(t) | a b S0| S1,p S2,q S1| S1,r S0,p S2| S1,p S2,s | NS, Output z(t)

Using the encoding of: Input: a=0, b=1 Output: p=00, q=01, r=10, s=11 State: S0=00, S1=01, S2=10

PS|Input x(t) | 0 1 00| 01,00 10,01 01| 01,10 00,00 10| 01,00 10,11 | NS, Output

z(t)

Binary Coding of States, Inputs, and Outputs

7.9 Specification of Sequential Systems in VHDL (Mealy and Moore machines) The text example of Example 7.19 (page 187) demonstrates the implementation of a Mealy machine, one in which the output depends on the present state and input and can change while in a state of the FSM. The Moore machine differs in that output depends only upon the present state and does not change while in a state but remains fixed until another state is entered. The key difference is that Moore machine outputs change only when the present state changes, on the active clock edge. This has two desirable effects: 1) synchronizing the FSM outputs with the system clock and, 2) output is stable throughout the state. Unfortunately, Moore machines are also generally more complex, requiring more states since the output cannot vary while in a given state. For example, a Mealy machine can in one state produce output based upon the binary value of two input variables a and b when ab=00, 01, 10, and 11. A Moore machine would require four states, one for ab=00, 01, 10, and 11. The weakness of pure Mealy machines is they produce output based upon input that can change at any time without regard to the system clock. This undesirable since asynchronous inputs can lead to small or runt pulses on the outputs (the very short 01 output in the first simulation figure below) while the Moore machine guarantees that all outputs will be stable throughout the time between clock pulses.

To combine the simplicity of Mealy with the stability of outputs of the Moore machines we will use Mealy machines but enforce synchronized inputs. The general approach followed in the example at right below, is to assign input x to a signal synchX only when the clock signal is rising. When the present state is changed, the outputs are computed based upon the present state and the synchronized input. In the wave form simulation below note the output for the Mealy machine with input that is not synchronized with the clock (asynchronous inputs) leading to a small or runt pulse on the outputs (the very short 01 output) while the Mealy with synchronized inputs or a Moore machine guarantees that all outputs will be stable throughout the time between clock pulses. One additional artifact of synchronizing inputs is that state changes are delayed by one clock after the inputs change. This is due to the one active clock required to synchronize the input. The next clock has the synchronized input for the state change. This is particularly noticeable in the last simulation where the synchronized version stays longer in state S0 because of the one clock delay. This form will be generally used in this class due to its relative clarity of presentation.

Mealy Design for Figure 7.19

PS|Input x(t) | 0 1 S0| S0,00 S1,00 S1| S2,01 S3,10 S2| S0,10 S1,01 S3| S2,11 S3,11 | NS, Output z(t)

-- Example 7.19 -- Mealy Machine with asynchronous input x ENTITY mealy IS PORT( clk : IN BIT; x : IN BIT; z : OUT BIT_VECTOR(1 DOWNTO

-- Example 7.19 -- Mealy Machine with synchronous input x ENTITY Ex7_19 IS PORT( clk : IN BIT; x : IN BIT; z : OUT BIT_VECTOR(1 DOWNTO 0)); END Ex7_19;

0); END moore;

ARCHITECTURE behavioral OF mealy IS TYPE STATE_TYPE IS (S0, S1, S2, S3); SIGNAL presentS, nextS: STATE_TYPE; BEGIN PROCESS (clk) -- Change next State & BEGIN -- Output on RISING clock IF clk'EVENT AND clk = '1' THEN CASE presentS IS WHEN S0 => IF x='0' THEN nextS <= S0; z <= "00"; ELSE nextS <= S1; z <= x & NOT (x); END IF; WHEN S1 => IF x='0' THEN nextS <= S2; z <= NOT(x) & x; ELSE nextS <= S3; z <= "11"; END IF; WHEN S2 => IF x='0' THEN nextS <= S0; z <= "00"; ELSE nextS <= S1; PROCESS (state, synchX) -- Change output z <= x & NOT BEGIN -- on synchronized (x); CASE state IS -- input and state END IF; WHEN S0 => z <= "00"; WHEN S3 => WHEN S1 => z <= synchX & NOT IF x='0' THEN nextS <= S2; (synchX); z <= NOT(x) & WHEN S2 => z <= NOT(synchX) & x; synchX; ELSE nextS <= S3; WHEN S3 => z <= "11"; z <= "11"; END CASE; END IF; END PROCESS; END CASE; END behavioral; END IF; END PROCESS;

ARCHITECTURE behavioral OF Ex7_19 IS TYPE STATE_TYPE IS (S0, S1, S2, S3); SIGNAL state : STATE_TYPE; SIGNAL synchX : BIT; BEGIN PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN synchX <= x; -- synchronized input x CASE state IS WHEN S0 => IF synchX='0' THEN state <= S0; ELSE state <= S1; END IF; WHEN S1 => IF synchX='0' THEN state <= S2; ELSE state <= S3; END IF; WHEN S2 => IF synchX='0' THEN state <= S0; ELSE state <= S1; END IF; WHEN S3 => IF synchX='0' THEN state <= S2; ELSE state <= S3; END IF; END CASE; END IF; END PROCESS;

PROCESS (nextS) BEGIN -- Change present State to next State presentS <= nextS; END PROCESS; END behavioral; Mealy Machine with Asynchronous Input x (Example 7.19)

Mealy Machine with Synchronized Input x (Modified Example 7.19)

-- Mealy Machine with synchronized inputs and separate present and next states ENTITY synchFSM IS PORT( clk : IN BIT; x : IN BIT; z : OUT BIT_VECTOR(1 DOWNTO 0); END synchFSM; ARCHITECTURE behavioral OF synchFSM IS TYPE STATE_TYPE IS (S0, S1, S2, S3); SIGNAL presentS, nextS: STATE_TYPE; SIGNAL synchX : BIT; BEGIN

PROCESS (clk) -- Present to Next State change on RISING clock edge BEGIN IF clk'EVENT AND clk = '1' THEN synchX <= x; CASE presentS IS WHEN S0 => IF synchX='0' THEN nextS <= S0; ELSE nextS <= S1; END IF; WHEN S1 => IF synchX='0' THEN nextS <= S2; ELSE nextS <= S3; END IF; WHEN S2 => IF synchX='0' THEN nextS <= S0; ELSE nextS <= S1; END IF; WHEN S3 => IF synchX='0' THEN nextS <= S2; ELSE nextS <= S3; END IF; END CASE; END IF; END PROCESS; PROCESS (nextS) -- Change present State BEGIN -- after rising clock edge presentS <= nextS; CASE presentS IS WHEN S0 => z <= "00"; WHEN S1 => z <= synchX & NOT(synchX); WHEN S2 => z <= NOT(synchX) & synchX; WHEN S3 => z <= "11"; END CASE; END PROCESS; END behavioral; Machine Simulation

The preferred implementation is the final example above. It is a Mealy machine with synchronized inputs and uses separate present and next state to more clearly distinguish the process of the FSM. The following example illustrates how the clock can serve to synchronize inputs. Notice that the x input occurs at any time relative to the active clock edge but the synchronized x occurs in synchronization with the clock.

-- synchronized input ENTITY synchIN IS PORT( clk : IN BIT;

x : IN BIT; synchX : OUT BIT); END synchIN; ARCHITECTURE behavioral OF synchIN IS BEGIN PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN synchX <= x; -- synchronized input x END IF; END PROCESS; END behavioral;