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MGA-635P8 GaAs ePHEMT MMIC 3.5 GHz Low Noise Amplifier with Superior Noise and Linearity Performance

Application Note 5494

Introduction

The weakest signal that a wireless receiver can recover is defined by its sensitivity [1]

Rx_sen (dBm) = -174 + 10log BW + SNR + F (Eq. 1)

where, BW is the bandwidth in Hz, SNR the required signal- to-noise ratio, and F the system noise figure.

The low noise amplifier (LNA), as its name implies, improves the receiver sensitivity by reducing the cascade noise figure. The Friss equation (Eq. 2) shows that the noise figure (F 1 ) of the 1st amplifying stage in the receiver chain (i.e. the LNA) dominates and therefore, the noise perform- ance of subsequent stages (i.e. F 2 , F 3 and so on) is of less importance.

F = F 1 +

F 2 – 1

G

1

+

F 3 – 1

G

1 G 2

+ …

(Eq. 2)

where, G n is the gain of the nth stage in the receive chain.

In a cellular base station (BTS) or a microwave relay, the antenna is located on the tower top, whereas the radio cards are housed inside a shack at the bottom. They are connected by a coaxial cable which has significant signal loss due to its considerable length. To prevent NF deg- radation due to the cable loss, a separate LNA stage is mounted close to the antenna.

Depending on whether frequency domain duplexing or time domain duplexing (TDD) is used, one antenna can be shared by both transmitter and receiver via a frequency- selective diplexer or an RF switch. Additionally, a band-pass filter may be inserted before the LNA to prevent blocking or desensitization by a strong out-of-band interferer. However, both the duplexer and the filter have losses. As these losses occur before the LNA, they have a deleterious effect on receiver sensitivity [2]. Therefore, an LNA with better noise performance can relax the loss requirements for the duplexer and filter.

Other critical performance parameters include high gain to overcome loss in the long cable connecting the tow- er-mounted LNA and the ground-level radio shack and high linearity, as the RF spectrum in the tower vicinity can

high linearity, as the RF spectrum in the tower vicinity can be very crowded due to

be very crowded due to site sharing with other wireless trans

The MGA-635P8 serves the 2.3 GHz to 4 GHz range and

is part of a new active-bias LNA product family that has

a common PCB footprint for covering the 400 to 4000

MHz range. Besides tower mounted LNA applications, the MGA-635P8 can be used in BTS radio cards, repeaters, remote radio heads, consumer premises equipment (CPE) and access points (AP).

Device physical and parametric characteristics

As shown in Figure 1, the 8-pin quad flat non-lead (QFN, 2 x 2 x 0.75 mm) packaged MGA-635P8 microwave monolith-

ic integrated circuit (MMIC) consists of a cascode amplifier

and an active bias regulator. The cascode topology advan-advan- tages are high-gain with current reuse and better reverse isolation (ISO). The 0.25 μm feature size GaAs enhance- ment-mode pseudo-morphic High Electron Mobility Tran- sistor (ePHEMT) process [3] has a high gain-bandwidth

product, f T , of over 30 GHz. The high bandwidth allows the target gain to be achieved in one cascade stage. Johnson noise generated in the circuit interconnects is minimized by doubling the metal thickness compared to previous process technology.

The internal bias regulator allows the LNA quiescent current (Ids) to be adjusted by either varying R BIAS or by an externally applied bias voltage, V BIAS (Figure 5a). The regu- lator’s low current drive requirement (I BIAS ≤ 1 mA) is com- patible with most CMOS families and it may be possible to switch the LNA directly from a microcontroller in time domain duplexing applications. In battery-powered appli- cations, the adjustable bias can also be used to trade-off linearity for power saving.

The Ids temperature stability is achieved by the regulator and the LNA having undergone similar processing. The V BIAS and V GS voltages “mirror” each other to compen- sate for thermal drift [4] and transconductance variation between different wafer batches.

BIAS GENERATE Vbias [1] [8] NU BYPASS RFin [2] [7] RFout AMP NU [3] [6]
BIAS GENERATE
Vbias [1]
[8] NU
BYPASS
RFin [2]
[7] RFout
AMP
NU [3]
[6] NU
ESD
NU [4]
[5] NU
PROTECT
S TABILIZE

Figure 1. MMIC simplified circuit

Off-chip circuit

To demonstrate the MMIC RF performances, a 3.5 GHz LNA was designed and then assembled. Twelve off-chip passive components were needed on the PCB to perform matching and biasing as it was not feasible to integrate these functions on the chip. The complete LNA circuit is shown in Figure 5a.

At the input side, C1 and L1 provide DC blocking and RF choking functions, respectively. The combination of C1 and L3 forms a high pass L network to transform the device input impedance Z IN to the Smith chart centre (Figure 2). Due to the 6 dB gain reduction per octave phe- nomenon known as Miller capacitance, a high forward transconductance (gm) in the active device is necessary for adequate gain at 3.5 GHz. Unfortunately, the high gm device will then have very high gain at low frequencies (LF). The input match’s high-pass response progressively rolls off the gain below the operating frequency, f 0, and thus prevents LF instability.

The device Z OUT is already close to 50 ohm at f 0 , so no further matching is necessary. Thus, C2 and L2 function as DC block and choke, respectively. They also impart a high-pass characteristic to further enhance the LF stability.

S(1,1) C1 L3 S(1,1) S(1,1) sp3g5_withL1c1 sp3g5_withL1 sp3g5 S(1,1)
S(1,1)
C1
L3
S(1,1)
S(1,1)
sp3g5_withL1c1
sp3g5_withL1
sp3g5
S(1,1)

freq (3.000 GHz to 4.000 GHz)

Figure 2. Simulated input matching trajectory

In the first design iteration, a wire-wound 0402 inductor was used for L2, resulting in a Rollett stability factor k of 0.94 at the lowest point (11 GHz). When L2 was substituted with a multilayer 0402 inductor in a subsequent prototype, the lowest k marginally improved to 1.2 at 10 GHz (see Figure 9). We hypothesized that the multilayer inductor’s comparatively greater loss (or lower Q) at 10 GHz was re- sponsible for the improved stability. The simulated result in Figure 3 lends further credence to the observation that k can be improved by lowering Q in L2.

The chip inductors selected for L1 – L3 should have self resonant frequency (SRF) above f 0 . This precaution will ensure the inductors behave predictably at 3.5 GHz.

As the output and input pins are biased from the same voltage supply (Vdd), a portion of the output signals may detrimentally travel back to the input by conduction along the shared DC path. The phasor addition of output and input signals can create gain ripple and even oscillation below f 0 . To ward off inadvertent output-input feedback over the power supply, decoupling capacitors, C3-C6, shunt the AC signals to ground. Combining small and large capacitances enables suppression over a broader frequency spectrum.

Q = 5 Q = 25 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1
Q = 5
Q = 25
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
Centre: 10.0 GHz
Span: 2.0 GHz
50 m ~ 20 g 401 p
Figure 3. Simulated k vs. frequency as a function of L2’s unloaded Q.
Reducing the Q UL from 25 to 5 at 10 GHz can improve k.
Lin
without
with LF stab
1.02 1.01 = 1 1 0.99 0.98 0.97 0.96 0.95 0.94 0.93 0.92 Start: 0
1.02
1.01
=
1
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
Start: 0 Hz
Stop: 1.0 GHz
Figure 4. Measured input reflection coefficient before and after adding the
R2-C6 low-frequency termination network.

Despite the input match’s high-pass response, its finite out-of-band rejection permits some leak-through of low frequency signals. Since the FET gate approximates an open circuit at low frequencies, the signals are then reflected back to the source.The incidence and reflected input signals vary in phase over frequency, so their vectorial addition creates ripples in the input reflection coefficient ( IN ) as shown in Figure 4. At the frequencies where the ripple peaks exceed unity, the amplifier is potentially unstable. It follows that the stability criterion k is also less than 1 at the affected frequencies. The countermeasure comprising R2 and C6 reduces ripples below f 0 by presenting a resistive termi- nation to reflected signals. RF-grounding capacitor C3 is selected for a reactance (X) of approximately 8 at f 0 so that below 1 GHz, C3 gradually “disappears”. Subsequent- ly, the low frequencies reflected by the gate are diverted to R2 and return to ground through the shunt capacitor C6. As the ripples occurred at a frequency interval of ~75 MHz, the value of C6 should be large enough to effectively bypass down to this frequency.

To switch the LNA in time domain duplexing (TDD) appli- cations, R BIAS can be disconnected from Vdd to allow the input of a 0 V-5 V control voltage. The time taken to turn on the LNA is constrained by the time constant of the R BIAS and C6 combined. For a faster turn-on, C6 can be reduced to the same value as C3. On this evaluation board, the turn-on time has been measured at approximately 0.6 S using a 10 pF value at C6.

PCB design for LNA performance evaluation

The PCB, which measures 21.5 x 18 mm, uses microstrip with a co-planar ground on 10-mil Rogers RO4350 material. This mid-priced substrate has modest RF perfor- mances and is compatible with the FR4 fabrication process [5]. As the thin RO4350 PCB is too flexible on its own, an additional 1.2 mm thick FR4 layer is glued to the former’s ground-plane side for stiffening it and making the PCB stack thick enough (1.45 mm) for a snug fit with standard edge-launch RF connectors.

The centre paddle at the MMIC bottom and pin 4 must be connected to the RF ground using the shortest possible route in order to minimize deleterious parasitic effects. If significant parasitic inductance exists between the MMIC and the PCB ground plane, possible maladies may include gain degeneration and oscillation at >10 GHz. In the example layout shown in Figure 5 (b), connection to the bottom ground plane is made using four via-holes that were placed directly under the MMIC. Following good RF practice, all unused MMIC pins (5, 6 and 8) are also connected to ground.

RF connections were made through edge-launch SMA- to-microstrip transitions (Johnson Component P/N 142- 0701-856), and the DC supply was connected via a 2-pin straight PCB header. Other than C5 and C6, which are 0805-size because of their large capacitance value, all other RLC components are 0402 size. The area occupied by components is approximately 8 x 10 mm (80 sq. mm).

Vdd V BIAS R BIAS C6 R1 C5 R2 C4 C3 L2 L1 [1] [8]
Vdd
V BIAS
R BIAS
C6
R1
C5
R2
C4
C3
L2
L1
[1]
[8]
IN
OUT
C1
[2]
[7]
[3]
[6]
L3
C2
[4]
[5]
(a)
[8] IN OUT C1 [2] [7] [3] [6] L3 C2 [4] [5] (a) (b) Figure 5.

(b)

Figure 5. (a) LNA evaluation circuit and (b) Component placement diagram

Table 1. LNA evaluation circuit part list

Part

Value

Remark

C1

1.5 pF

Murata GRM15

C2

10 pF

Murata GRM15

L1

12 nH

CoilCraft 0402CS

L2

3.9 nH

Toko LL1005

L3

2.2 nH

CoilCraft 0402CS

C3, C4

10 pF

Murata GRM15

C5, C6

4.7 F

Q1

MGA635P8

Avago

R1

0

R2

56

RBIAS

3k3

Component and PCB modelling

The PCB design was simulated before being built to minimize or even eliminate on-the-bench tuning. Pre- dicting potential problems such as out-of-band instabil- ity could also obviate committing a bad PCB layout to fabrication.

To facilitate the design of the matching circuitry, we obtained the MMIC’s scattering parameters (s2p) by measuring the physical device on a custom-designed fixture at typical bias conditions. This characterization fixture used the same PCB material (10-mil RO4350) intended for the prototype LNA. After removing the fixture effect from the raw data by the thru-reflect-line TRL technique, the resultant s2p data represented the device and its PCB footprint (i.e. mounting pads and substrate beneath the device). The s2p file was subsequently imported into Agilent Technologies ADS2006A software for circuit simulation.

During the first simulation iteration, we modelled the off-chip components by employing simplified equiva- lent circuits. Although manufacturer-supplied s2p files could be used to model these RLC passives, they lacked the convenience of changing component values on-the- fly and would have slowed down the tuning process in the simulator. In addition, the s2p data provided by the capacitor manufacturer is severely limited in usefulness because it has a single reference plane along the chip’s long axis [6] and hence is only accurate for shunt-con- nected capacitors. A capacitor in series with the RF path cannot be accurately represented by this data because it is really a two-port device that requires two reference planes, i.e., one for each terminal.

The simplified equivalent circuits of the RLC compo-

most

nents

important parasitic element as described by Rhea [7]. These component models, which consisted of a 2 or

were

created

by

intuitively

selecting

the

3-element equivalent circuit, could only account for the fundamental resonance, whereas real-world passives have multiple higher resonances. A more accurate modelling technique such as measurement-based models can cover multiple higher resonances [8], but require additional measurements and computer optimization to develop. For designing the LNA impedance matching, the simple models’ frequency limitation can be tolerated because we are mainly interested in the frequency range around f 0 .

It is also worth noting that many of the manufacturer-

supplied s2p files are also frequency limited, e.g., most Murata chip capacitors are characterized to 6 GHz.

The inductor model used the typical Q UL values specified

at the frequency nearest to f 0 as published in the data-

sheet (usually 1.7 GHz or 1.8 GHz depending on manufac-

turer) and then extrapolated to 3.5 GHz and above using a

Q √f relation. An inductor’s parasitic capacitance (Cpst)

was calculated from the published typical SRF values but with an extra 0.1 pF added to account for the parasitic capacitance associated with the PCB pads.

The parasitic inductance (Lpst) in the capacitor model followed the values provided by the vendor-supplied software [9]. However, L1 and L3’s circuit model were sub- sequently replaced with the manufacturer’s s2p data after the correct inductance value was determined.

The bias section (DC) of the PCB was not modelled because

it is not expected to impact the RF performance. The

edge-launched SMA jacks (female) were modelled using the ADS2006A parameterized component for a coaxial line with the parameter values from the manufacturer. However, discontinuity effects at the coax-to-microstrip interface [9] were ignored because additional work would have been required to extract these parameters by either measurement or electromagnetic simulation.

SNP1

File="MGA635P8_55mA.s2p" 1 2 1 2 1 2 Ref dmbd_in dmbd_out X2 X1 Term2 Term1 Num=1
File="MGA635P8_55mA.s2p"
1
2
1
2
1
2
Ref
dmbd_in
dmbd_out
X2
X1
Term2
Term1
Num=1
Num=2
Z=50 Ohm
Z=50 Ohm

(a)

Results and discussion

Nominal evaluation board DC bias values are Vdd = 5 V and Idd = 60 ±5 mA (set by R BIAS = 3.3 k ). Key parameters are specified at 3.5 GHz.

Our foremost design goal was to achieve good return loss (IRL < -15 dB) concurrently with low noise (F < 1 dB). This requirement originated from the BTS market segment where the pre-LNA diplexer or filter is sensitive to the IN . Older BTS implementations usually rely on either an isolator or a quadrature coupler at the input of the balanced LNA to achieve simultaneous input match and low noise figure. But newer implementations have sought to eliminate the isolator or the quadrature coupler for both cost and space reasons. In Figure 7 the measured perfor- mances at mid-band are: IRL = -16 dB, ORL = -12 dB and ISO = -32 dB. The IRL minima occurred ~300 MHz lower than intended operating frequency (i.e., 3.2 GHz instead of 3.5 GHz). However no attempt was made to retune

MSub
MSub

MSub1

H=0.25 mm

Er=3.48

Cond=4.7E+7

T=0.02 mm

TanD=0.004

 

C1

Taper1

TL1

TL22

R=Rpst Ohm

TL2

W1=W mm

W=W mm

W=W mm

L=Lpst nH

W=W mm

W2=W2 mm

L=5.mm

L=0.5 mm

C=1.5 pF

L=1.2 mm

L=0.8 mm

L=5.mm L=0.5 mm C=1.5 pF L=1.2 mm L=0.8 mm W=W mm L=1.1 mm TL21 W=W mm

W=W mm

L=1.1 mm

TL21

W=W mm

L=1.4 mm

R=50 Ohm

L=Lpst nH

CCI_0402CS TL5 SNP1 A=1.25 mm Type=12.0 nH CCI_0402CS Ri=4.6 mm SNP2 Ro=5.3 mm Type=2.2 nH
CCI_0402CS
TL5
SNP1
A=1.25 mm
Type=12.0 nH
CCI_0402CS
Ri=4.6 mm
SNP2
Ro=5.3 mm
Type=2.2 nH
L=9.375 mm
C3
T=0.0013 mm
L=Lpst nH
Cond1=4.1E7
C=10 pF
Cond2=1.5E7
Er=2.08
TanD=0.001
Var
Eqn
VAR2
W=0.6
R1
C5
TL8
W2=0.28
L=Lpst nH
W=W mm
Lpst=0.5
C=4.7 uF
L=3.9 mm
Cpst=0.15
Rpst=0.5

TL7

(b)

the input match because the critical specifications were already met. Besides, shifting the frequency to exactly 3.5 GHz would require LC values of already met. Besides, shifting the frequency to exactly 3.5 GHz would require LC values of a finer granularity than

the common E12. The bandwidth at the -10 dB RL points was in excess of 1 GHz at both input and output sides. This wide span was in excess of 1 GHz at both input and output sides. This wide span of the matching networks confers some immunity to component tolerances.

Some disagreement between simulated and measured

results occurred over the evaluated frequency range,

particularly IRL. This is a limitation of the “guesstimated” component and PCB models used in the simulation.

C2 Taper2 TL3 TL4 R=Rpst Ohm W1=W mm W=W mm L=Lpst nH W=W mm W2=W2
C2
Taper2
TL3
TL4
R=Rpst Ohm
W1=W mm
W=W mm
L=Lpst nH
W=W mm
W2=W2 mm
L=1.1 mm
L=5.5 mm
TL6
C=100 pF
L=0.8 mm
L2
L=3.9 nH
Ql=42
Fl=1.8 GHz
C=Cpst pF
TL14
W=W mm
L=1.2 mm
Var
Eqn
VAR1
C4
TL13
W=0.6
L=Lpst nH
W=W mm
W2=0.28
C=10 pF
L=1.3 mm
Lpst=0.5
Cpst=0.15
Rpst=0.5
TL12
R2
C6
W=W mm
R=0 Ohm
L=Lpst nH
L=0.8 mm
L=Lpst nH
C=4.7 uF

(c)

Figure 6. Two-level hierarchical model of the LNA (a) top level consisting of the device s-parameter file and input/output sub-modules, (b) input section equivalent circuit, and (c) output section equivalent circuit

IRL mes IRL sim ORL mes dB ISO mes ISO sim ORL sim 0 -5
IRL mes
IRL sim
ORL mes
dB
ISO mes
ISO sim
ORL sim
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
Centre: 3.5 GHz
Span: 1.0 GHz
1008
10 m - 6g
401 p

Figure 7. Measured and simulated input return loss (IRL), output return loss (ORL) and reverse isolation (ISO) vs. frequency

dB G k D 20 10 10 9 08 -10 7 -20 6 -30 5
dB
G
k
D
20
10
10
9
08
-10
7
-20
6
-30
5
-40
4
-50
3
-60
2
-70
1
-80
0
Start: 50.0 MHz
Stop: 20.0 GHz
1010
1D01

Figure 9. Measured gain (G), Rollett stability factor (k) and stability measure (D) vs. frequency

F mes F sim G sim G mes Centre: 3.0 GHz 8/24/2010 1:49:38 PM Span:
F mes
F sim
G sim
G mes
Centre: 3.0 GHz
8/24/2010 1:49:38 PM
Span: 2.0 GHz
1D#1, 2 - 4 g 41 pt

dB

20 Due to receiver component non-linearity, adjacent-

19 channel signals can create third-order intermodulation

18 distortion (IMD3). The non-linearity defined by the 2f1-f2

17 or 2f2-f1 relationship is impossible to filter as they are very

16 close to the wanted signal. A key measure of linearity, the

15 third-order intercept point, OIP 3 , is defined as the point

14 where the fundamental signal power (P fund ) and the IMD3

13 power theoretically intersect. In the linear region, OIP3 can

12 be calculated from the IMD3 amplitude using Equation 3:

11

10

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

IM

OIP 3 = P fund +

2

where, IM is difference between the fundamental and the intermodulation product power in dB.

Two input tones at 3500 and 3501 MHz were used for eval- uating this design, however, other frequency spacing is not expected to change the results significantly. As shown in Figure 10, in the linear operating region enclosed by Pi < -4 dBm, OIP 3 is ≥35 dBm at the nominal bias. The null or sweet-spot in the IMD at around -6 dBm input drive is indicative of class AB operation. The null was caused by the small-signal IMD and large-signal IMD being out-of- phase at the onset of saturation [11].

Figure 8. Measured and simulated noise figure (F) and gain (G) vs. frequency

The measured noise figure (F) is slightly less than 1 dB at f 0 . The F minima occurred around 3 GHz due to the afore- mentioned offset in the input match.

Figure 9 graphically portrays several stability parameters. The gain curve decreases monotonically with frequency without any abrupt inflection. The absence of prominent peaks in the gain response lessens the chance of an inopportunely dimensioned metal enclosure stimulating oscillation due to cavity resonance effect. Additionally, the Rollett stability factor (k) and stability measure (D) were computed from measurement of the LNA s-parameters. The combination of k > 1 and D < 1 over the evaluated range implies unconditional stability with any termination having a positive real part.

Po, IMD3 & OIP3 vs. Pi

dBm Po Imd OIP3 dBm dB G Id mA 20 40 15.2 80 10 38
dBm
Po
Imd
OIP3
dBm
dB
G
Id
mA
20
40
15.2
80
10
38
15
78
0
36
14.8
76
-10
34
14.6
74
-20
32
14.4
72
-30
30
14.2
70
-40
28
14
68
-50
26
13.8
66
-60
24
13.6
64
-70
22
13.4
62
-80
20
13.2
60
Start: -20.0 dBm
Pi
Stop: 0 dBm
Centre: 7.0 dBm
Po
Span: 30.0 dBm
100709
02
1012
1D01

Figure 10. Measured output power, third-order intermodulation power and third-order intercept point vs. frequency

Blocking, which desensitizes the receiver by lowering

G and increasing F [12], can be caused by either a non-

synchronous interferer, such as a powerful transmitter sharing the same tower, or by a synchronous source, such as the transmission that leaks past the circulator or duplexer in a transceiver with simultaneous transmit and receive capability [13]. A component with a high gain- compression threshold can therefore resist blockers more effectively. Gain compression is primarily caused by non-

linear transfer characteristic in an amplifier that is driven beyond its linear region with increasing heat dissipation

as a minor contributor.

Because GaAs has comparatively lower bulk conductivity than silicon, less RF power is wastefully dissipated as heat. Furthermore, the low knee voltage, 0.3 V, of the ePHEMT process allows a larger voltage swing before clipping [14]. Figure 11 shows an output power 1-dB compression point (P1dB) of ~19 dBm.

Figure 11. Measured G and Id vs. output power

Table 2. Evaluation key LNA parameters

Parameter

Typical value

Vdd (V)

5.0

Idd (mA)

60

R

BIAS ( )

3k3

G (dB)

15

F

(dB)

<1

RL (dB)

<-12

OIP3 (dBm)

35

P1dB (dBm)

19

References

[1] Agilent Technologies application note, “AN57-1 Funda- mentals of RF and Microwave Noise Figure Measurements,” [Online] Available: http://www.agilent.com

[2] I. Hunter, R. Ranson, A. Guyette, and A. Abunjaileh, “Micro- wave Filter Design from a Systems Perspective,” IEEE Micro- wave Magazine, pp. 71-77, Oct. 2007.

[3] K. Fujii and H. Morkner, “Single supply 1W Ku-band Power Amplifier Based on 0.25gm E-mode PHEMT,” Microwave Sym- posium Digest, 2006.

[4] C. Blair,“Biasing LDMOS FETs for linear operation”, Applied Mi- crowave & Wireless, Jan. 2000, pp. 92.

High

Frequency Circuit Materials,”rev. 1.4, [Online] Available: http:// www.rogers-corp.com

Characteristic

specification,

Parameters of Murata Component Library,”[Online] Available:

http://www.murata.com

[7] R. W. Rhea, Oscillator Design and Computer Simulation, Atlanta:

[6] Murata

[5] Rogers

Corp.

Inc.

product

product

specification “RO4000

“About

Series

Noble, 1995, pp. 21-26.

[8]

I. Bahl, Lumped Elements for RF and Microwave Circuits, Norwood, MA: Artech, 2003, chap. 2.4.5 and 5.4.4.

[9]

Murata Manufacturing software, “Murata Chip S-Parameter & Impedance Library Version 3.6.0,” 2004.

[10] J Chramiec” and J K Piotrowski, "Novel approach to the characterization of coaxial-to-microstrip transitions," 27th European Microwave Conference, 1997.

[11] P. M. Cabral, J. C. Pedro and N. B. Carvalho, “A Unified Theory for Nonlinear Distortion Characteristics in Different Ampli- fier Technologies,” Microwave Journal, Apr. 2005.

[12] W. Domino, N. Vakilian and D. Agahi, “Polynomial Model of Blocker Effects on LNA/Mixer Devices,” Applied Microwave & Wireless, Jun. 2001.

[13] O. K. Jensen, and et al, “RF Receiver Requirements for 3G W-CDMA Mobile Equipment”, Microwave Journal, pp. 24, Feb. 2000.

[14] Der-Woei Wu, J. S. Wei, C. Su, R. M. Parkhurst, SL Fu, S. Chang, and R. B. Levitsky,“An enhancement-mode PHEMT for single- supply power amplifiers,” HP journal, Feb. 1998.

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. AV02-2777EN - December 20, 2010

Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. AV02-2777EN - December 20,