Beruflich Dokumente
Kultur Dokumente
(20 Tutorials containing 57 MASTAR exercises) Thomas Skotnicki & Frederic Boeuf
Summary
This set of slides intends to cover a wide part of the CMOS device physics from the basic solidstate properties to the system level functions, using the MASTAR software ~ 57 Exercices can be found within 20 Tutorials covering several aspects of the device and CMOS circuit physics and operation
Outline
Tutorial 1 : General MASTAR presentation (1 ex.) Tutorial 2 : Creating a Profile (Saving device parameters) (1 ex.) Tutorial 3 : Modifying a Profile (3 ex.) Tutorial 4 : Device Workspace Basics : Creating a Plot File (5 ex.) Tutorial 5 : Basic Physics of the Electron Mobility in Silicon (4 ex.) Tutorial 6 : Basic Physics of the Hole Mobility in Silicon (4 ex.) Tutorial 7 : Carrier Mobility in MOSFETs (6 ex.) Tutorial 8 : Carrier Mobility and Drive Current in Strained-MOSFETs (3 ex.) Tutorial 9 : Coulomb Limited Carrier Mobility (2 ex.) Tutorial 10 : Using the System Layout Module (2 ex.) Tutorial 11 : Using the System Layout Module For industrial feasibility evaluation (2 ex.) Tutorial 12 : Inverter Delay (6 ex.) Tutorial 13 : Device Scaling (4 ex.) Tutorial 14 : H-K dielectric and Metal Gate Stack (3 ex.) Tutorial 15 : Device Variability (2 ex.) Tutorial 16 : SRAM Variability (3 ex.) Tutorial 17 : Device Speed (1 ex.) Tutorial 18 : III-V High Mobility Channel Materials (1 ex.) Tutorial 19 : Device Structure FDSOI (3 ex.) Tutorial 20 : Device Structure DG / FinFET (1 ex.)
T. Skotnicki & F. Boeuf
3
Tutorial 1
General MASTAR Presentation
Description
Objective
this series of exercices intends to present a general view of the MASTAR tool which will be used for all this course on device physics Basic operation and principle are reviewed
Pre-requisite :
none
Loading MASTAR
1. Open MASTAR directory, then double click on MASTAR.exe
3. Click on continue
7
General Presentation
Roadmap Workspace Device Workspace Adv. Physics Workspace
Roadmap Workspace
Input : up to 5 architectures, year of production, familly (HP, LoP, LstP)
Output : Ion, Ioff, Vth, DIBL, CET, CV/I Graphics Output : Ion/Ioff, Vt-L, performance points (cloud), users Plot Usage : Device (reverse) engineering, platform definition
Output : Basic MOSFET caracteristics Graphics Output : Ion/Ioff vs CMOS node, CV/I vs Year trend-line, gate leakage vs year Usage : long term view of CMOS Roadmaps (e.g. ITRS roadmap)
T. Skotnicki & F. Boeuf
Output : (Strain) Silicon band structure (electron and holes), ballistic current, Energy level in confined inversion channel,
Output Window : Device Performance :Vth, Ion, Ioff, SS, DIBL, Graphical Representation (Ion/Ioff, Vt-L, DIBL-L
Roadmap Workspace
Input Window : up to 5 architectures Graphical Representation of the Roadmaps Output Window : Main Device output caracteristics
Tutorial 2
Creating a Profile (Saving device parameters)
12
Description
Objective
this series of exercices intends to learn how to handle the MASTAR software Basic functions are reviewed
Loading/saving data Graphical representation of calculations results in real-time
Output Window : Device Performance :Vth, Ion, Ioff, SS, DIBL, Graphical Representation (Ion/Ioff, Vt-L, DIBL-L
2. Select Default.pro
2. Output is calculated
Modifing a Profile
2. Current Point is moving on Ion/Ioff Graph 3. Play with other parameters : Vdd, Tox
Tutorial 3
Device Workspace Basics : Modifying a Profile (Saving device parameters)
Description
Objective
this series of exercices intends to learn how to handle the MASTAR software Basic functions are reviewed
Creating profiles Saving Data
Output Window : Device Performance :Vth, Ion, Ioff, SS, DIBL, Graphical Representation (Ion/Ioff, Vt-L, DIBL-L
2. Output is calculated
2. Current Point is moving on Ion/Ioff Graph 3. Play with other parameters : Vdd, Tox
1. Enter Lg=39nm 2. Enter Tox=1.55nm 3. Enter Xj=15nm 4. Enter Vdd=1.1V 5. Enter Rs=180 Ohm.m 6. Check Conventional Slope
2. Click on Save-As
Tutorial 4
Device Workspace Basics : Creating a Plot File
Description
Objective
this series of exercices intends to learn how to handle the MASTAR software Basic functions are reviewed
Creating a plot file from existing profiles Creating a plot file from a ASCII text file Adjusting the display
Profile (.pro)
Stocks MOS parameters
Clouds (.clo)
Ion/Ioff is generated from a single profile by varying MOS parameters (e.g. Lg, Nbulk ) Experimental Data can be imported from a texttext-file
1. Click on Profiles
2. Select ex1_LVT.pro by double clicking or use Add>> button. Repeat the operation with ex1_SVT.pro
37
2. Click on the Triangle to load the corresponding profile into the Device Workspace
1. Set ymax=1000
Note : When opening a plot file (.plm), each profile (= plot component) is recalculated. Therefore a plot is not a simple prepre-calculated line but a realreal-time calculated line
T. Skotnicki & F. Boeuf
44
2. Syntax is as follows [label displayed in graph] Ion = value in A/m Ioff = value in nA/m
Note : Plot are displayed with dotted line and Mastar Plot are displayed with solid lines
T. Skotnicki & F. Boeuf
47
Tutorial 5
Basic Physics of the Electron Mobility in Silicon
Description
Objectives
This series of exercices intends to describe a simplified conduction band-structure of Silicon Conduction band is analyzed for relaxed and strainedSilicon. From Bandstructure calculations, impact on mobility is deduced
49
Bibliography
A Comprehensive Modeling Study of Two-Dimensional Silicon Subbands Using a Full-Zone k.p Method, M. Szczap, N. Cavassilas, F. Michelini, F. Payet, F. Boeuf, and T. Skotnicki, In Extented Abstracts of SSDM 2007 (JSAP CAT AP071239), pp. 462-463 Analytical Model for Phonon-Limited Mobility in n-MOS Inversion Layers on Arbitrarily Oriented and Strained Si Surfaces, Mlanie Szczap, Nicolas Cavassilas, Frdric Boeuf, Fabrice Payet and Thomas Skotnicki, in Extented Abstracts of SSDM 2006 (JSAP CAT AP061239), pp 1062-1063 Strained Si/SiGe MOSFET Capacitance modeling based on band structure analysis, F. Gilibert, D. Rideau, F. Payet, F. Boeuf, E. Batail, M. Minondo, R. Bouchakour,T. Skotnicki and H. Jaouen, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.281-285 Low temperature characterization of effective mobility in uniaxially and biaxially strained N-MOSFETs, F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Boeuf and T. Skotnicki, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.525-528
Velocity
v=
2Ec m*
1.
=q
T. Skotnicki & F. Boeuf
m
*
E(k ) =
h 2k 2 2m
V(x)
1 1 2 E = m h2 k 2
k m=m0=9.1e-31 kg ?
1 2 =
k
E1 E2
E1 H = E 2
E +E E= 1 2 2 2 2 + 4
Eigenvalues ?
D( ) = =0
E (u.a)
2 2 E1 + E2 E= + 2 4
Eg
1 1 2 E = m h2 k 2
-1.E+11
-5.E+10
5.E+10
1.E+11
(z) 001
(y) 010
(x)100
6 equivalent types of electrons are involved in conduction regime of nMOS 2 types of holes are involved in conduction regime of pMOS : heavy and light
Efield ml =0.92m0
If Electric field is // to the elipsoid, then conduction mass is ml
mt=0.19m0 Efield
If Electric field is to the elipsoid, then conduction mass is mt
57
Strain Configurator
58
Select (100) substrate Select (011) orientation Check device orientation here
59
(1)
(2)
60
Answer : Most of the carrier will populate a lower mt mass valley. Average conduction mass is then decreasing leading to a higher mobility
(1)
61
Answer : Most of the carrier will populate a lower mass valley. Average conduction mass is then decreasing leading to a higher mobility
(2)
(1)
62
Most of carriers will populate these lowest energy valley (001) and (010)
Answer : The Z-valley has a lower enegy, so that there will be less light electrons. So, the average conduction mass is then increasing from {2/3mt,1/3ml} to {1/2mt,1/2ml} leading to a lower mobility
63
Tutorial 6
Basic Physics of the Hole Mobility in Silicon
Description
Objectives
This series of exercices intends to describe a simplified valence band-structure of Silicon Valence band is analyzed using a 6x6 k.p. model. Hole population and effective masses are analyzed as a function of stress
65
(1)
UP
MID
LOW
Note : Most of the carriers Are in the UP and MID (degenerated) Average conduction mass along L for holes is then 66 (0.562+0.148)/2=0.355
T. Skotnicki & F. Boeuf
67
68
(3)
(2)
(1)
Answer : Most of the carrier will populate the heavier mass valley, which also become heavier than in relaxed silicon. Average conduction mass in then increasing. Mobility is decreasing
69
(3)
(2)
(1)
Answer : Most of the carrier will populate the UP valley, which also become lighter than in relaxed silicon. Average conduction mass in then decreasing, and mobility is increasing
70
Hole mass along the channel direction are now lighter than on relaxed silicon
71
N
Unstrained Si
0.2
Si bulk
-0.1
HH LH
0.1
Energy (eV)
Energy (eV)
-0.2
>80 % in HH
SO
0.0
< 1 % in HH
-0.1 -0.2
-0.3
HH SO
-0.4
-0.5
-0.3
[100]
[110]
[100]
[110]
When straining Si, not only the effective mass of holes and the E carrier population are changed, but also the electron-phonon interaction time is increasing leading to a better mobility
T. Skotnicki & F. Boeuf
++ +
Biaxial Compression
Biaxial Tension
Tutorial 7
Carrier Mobility in MOSFETs
76
Effective Mobility
Goal of the exercise
Observe the Effective Mobility behavior as a function of effective field
Use variation on channel doping and length Use variation on gate oxide thickness
77
Bibliography
On the universality of inversion-layer mobility in nand p-channel MOSFETs S. Takagi; M. Iwase; A. Toriumi, Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International Digital Object Identifier,10.1109/IEDM.1988.32840, Publication Year: 1988 , Page(s): 398 401 On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.; Electron Devices, IEEE Transactions on.Volume: 41 , Issue: 12 Digital Object Identifier: 10.1109/16.337449 Publication Year: 1994 , Page(s): 2357 - 2362
AC=A0Eeff1/3
log( eff)
1 = 1 + 1 eff AC SR
eff = f (Eeff)
SR=A1Eeff-2
Eeff
80
81
Answer : When pocket dose , the Vth value is also (2) . Since Eeff (Vg+Vth)/6Tox , Eeff is therefore , therefore eff
(1)
82
(2)
Answer : When L , due to short channel effects, Vth is (1) Since Eeff (Vg+Vth)/6Tox , Eeff is also , therefore eff (2)
83
(3)
84
Answer : 1. When checking Ioff=constant, Channel doping is adjusted automatically to match the given Ioff 2. Due to short channel effects, the S factor is degraded from 90 to 115mV/dec when L (2) 3. To match the same Ioff, Vth has to be higher than before (307mV vs 230mV) 4. Since Eeff (Vg+Vth)/6Tox , Eeff is also , therefore eff (3)
(2)
Saturation current of the transistor is plotted as a function of Lgate, with Ioff kept constant Observe the optimum of saturation current around L 60nm for 60nm < L < 100nm, Idsat is improved by the decreased in L for L<60nm, the increase in Eeff is degrading eff more rapidly and therefore Idsat drops.
Note to Pr : The optimum value of L depends of several technological parameters, such as Tox and Xj
86
Tutorial 8
Carrier Mobility and Drive Current in StrainedMOSFETs
87
Bibliography
Non-Uniform Mobility Enhancement Techniques and their Impact on Device Performance Fabrice Payet, Frdric Boeuf, Claude Ortolland* and Thomas Skotnicki, Trans. Electron Devices Volume 55, Issue 4, April 2008 Page(s):1050 1057 Stress Memorization Technique (SMT) Optimization for 45nm CMOS, C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd P. Stolk, F. Boeuf & F. Arnaud , in Digest of Tech. Papers. Symposium on VLSI Technology 2006 (IEEE CAT No 06CH37743), pp 9697. Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm FD SOI Devices with Ultra Thin Silicon Channels , C. Gallon, C. Fenouillet-Beranger, S. Denorme, F. Boeuf, V. Fiori, N. Loubet, A. Vandooren, T. Kormann, M. Broekaart, P. Gouraud, F. Leverd, G. Imbert, C. Chaton, C. Laviron, L. Gabette, F. Vigilant, P. Garnier, H. Bernard, A. Tarnowka, R. Pantel, F. Pionnier, S. Jullian, S. Cristoloveanu and T. Skotnicki, Jpn. J. Appl. Phys. Vol. 45 (2006) Part 1, No. 4B, pp 3058-3063 Strained Si/SiGe MOSFET Capacitance modeling based on band structure analysis, F. Gilibert, D. Rideau, F. Paye, F. Boeuf, E. Batail, M. Minondo, R. Bouchakour,T. Skotnicki and H. Jaouen, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.281-285
SixGe1-x Based
Cristal Orientation
Liners
SiGe SEG
STI
Bulk
SSOI
In-plane
Out of plane
CESL
Tensile nMOS
SMT
Tensile nMOS
SiGe SD
Compressive
SACVD
Tensile Bi-axial nMOS+pMOS
nMOS+pMOS Si
SiGe
BULK
box
SSOI
Rotated substrate
Cristal Orientation
T. Skotnicki & F. Boeuf
91
3. Adjust Nbulk to 1e18 in order to re-adjust Ioff to ~10nA/m 4. Open the mobility Tab and uncheck Activate Strain Liner
(1)
(1)
(2)
93
(1)
Question
Ex-1 : Answer
with
Long channel devices : L Vdsat Vgt/(1+d) Idsat eff.vgt Idsat/Idsat = eff/eff Short channel devices : L 0 Vdsat L.Ec L.Vsat/eff Idsat Vsat Idsat/Idsat = Vsat/ Vsat
96
CESL Tensile
Io ff (A /m )
+15.6%
1.E-07
Tension
(F.Buf et al., IEDM 2004 , SSDM 2004)
98
(1)
(2)
99
100
(1)
(2)
101
102
Long channel devices : L Vdsat Vgt/(1+d) Idsat eff.vgt Idsat/Idsat = eff/eff Short channel devices : L 0 Vdsat L.Ec L.Vsat/eff Idsat Vsat Idsat/Idsat = Vsat/ Vsat
103
Tutorial 9
Coulomb Limited Carrier Mobility
104
Description
Objective of this tutorial is
To introduce the concept of Coulomb-Limited mobility Analyse the impact of Coulomb Scattering (CbS) on MOSFET performance when transistors are shrinked
Content
Background
Coulomb-limited Mobility Modeling Screening Effect Modeling
Ex-1 : plotting eff(Eeff) curves for various channel dopings Ex-2: Performance evolution of scaled MOSFETs with and without CbS
T. Skotnicki & F. Boeuf
105
Bibliography
Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon Masetti, G.; Severi, M.; Solmi, S.; Electron Devices, IEEE Transactions on . Volume: 30 , Issue: 7 Digital Object Identifier: 10.1109/T-ED.1983.21207 Publication Year: 1983 , Page(s): 764 - 769 Impact of Coulomb Scattering on the Characteristics of Nanoscale Devices, Frdric Boeuf, Grard Ghibaudo* and Thomas Skotnicki, Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, Sendai, 2009, pp1048-1049 Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs Mujtaba, A.; Takagi, S.-I.; Dutton, R.; VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on . Digital Object Identifier: 10.1109/VLSIT.1995.520876 Publication Year: 1995 , Page(s): 99 - 100 On the universality of inversion layer mobility in Si MOSFET's: Part Ieffects of substrate impurity concentration Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.; Electron Devices, IEEE Transactions on.Volume: 41 , Issue: 12 Digital Object Identifier: 10.1109/16.337449 Publication Year: 1994 , Page(s): 2357 - 2362
T. Skotnicki & F. Boeuf
106
Strong Inversion
Gate
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - Neutral -k0r - V(r)~1/r*e Area -
Source
Drain
Source
V(r)~1/r
Electron (holes) transport in the transistor channel is pertubated by the Coulomb potential created by fixed charges. This is called Coulomb Limited Mobility
In strong inversion, the Coulomb potential created by impurities is screened by the inversion layer. This is the Screening Effect , which lowers the impact of Coulombic interaction between carriers and impurities in the on-state of the transistor
108
Drain
(a) (b)
7.7E16
ac
3E17
sr
7.7E17 2.2E18
3. Adjust Nbulk to 1e18 in order to re-adjust Ioff to ~10nA/m 4. Open the mobility Tab and uncheck Activate Strain Liner
(1)
(1)
(2)
111
Click on Compute In order to avoid scale issue in the display NB : select Red then compute, then select Blue and compute, Green and compute and finally Black and compute
112
113
(2)
(1)
114
(1)
3e17
7e17
1e18
115
?
Coulomb interaction is on
Performance ? Why ?
NB : Ioff constant must be checked !
Ex-2 : Answer
Performance is this time degraded ! In order to keep Ioff constant, channel doping is increased when L is decreased to 50nm. The CbS is then higher, and mobility is now decribes by the blue curve below which is lower than the previous case (green). As a consequence, Ion is decreasing .
L=60nm Ion=678A/m
L=50nm Ion=666A/m
Tutorial 10
Using the System Layout Module
119
Objective
Objective is to review the basic operation of the System Layout module of MASTAR
Plotting I-V curves of nMOS and pMOS Creating Layout of Inverters and SRAM Simulating speed of Ring Oscillators
Module Overview
MOSFET window Inverter Cell SRAM Layout
1-Click on the green arrow to load Device profiles : nMOS pMOS Pass Gate transistor for SRAM calculation
Smooth = 0
Smooth = 0.1
adjust = 0.93
Cgd is automatically calculated by using Cgate+Miller (overlap+outerfringe), with gate heigth = 2*Lgate
4 Input you inverter layout It can be saved independantly or with the whole system profile
Interter delay in then calculted automatically using a Cload= 1fF Then results for various FO are displayed
Interter delay in then calculted automatically using a Cload= 1fF Then results for various FO are displayed
This graph show the Vout of each inverter node in the case of a single calculation
133
You can also generate random variation on inverter generation by checking the box, and enter the number of wanted calculation
134