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CMOS Physics using MASTAR

(20 Tutorials containing 57 MASTAR exercises) Thomas Skotnicki & Frederic Boeuf

Summary
This set of slides intends to cover a wide part of the CMOS device physics from the basic solidstate properties to the system level functions, using the MASTAR software ~ 57 Exercices can be found within 20 Tutorials covering several aspects of the device and CMOS circuit physics and operation

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Outline
Tutorial 1 : General MASTAR presentation (1 ex.) Tutorial 2 : Creating a Profile (Saving device parameters) (1 ex.) Tutorial 3 : Modifying a Profile (3 ex.) Tutorial 4 : Device Workspace Basics : Creating a Plot File (5 ex.) Tutorial 5 : Basic Physics of the Electron Mobility in Silicon (4 ex.) Tutorial 6 : Basic Physics of the Hole Mobility in Silicon (4 ex.) Tutorial 7 : Carrier Mobility in MOSFETs (6 ex.) Tutorial 8 : Carrier Mobility and Drive Current in Strained-MOSFETs (3 ex.) Tutorial 9 : Coulomb Limited Carrier Mobility (2 ex.) Tutorial 10 : Using the System Layout Module (2 ex.) Tutorial 11 : Using the System Layout Module For industrial feasibility evaluation (2 ex.) Tutorial 12 : Inverter Delay (6 ex.) Tutorial 13 : Device Scaling (4 ex.) Tutorial 14 : H-K dielectric and Metal Gate Stack (3 ex.) Tutorial 15 : Device Variability (2 ex.) Tutorial 16 : SRAM Variability (3 ex.) Tutorial 17 : Device Speed (1 ex.) Tutorial 18 : III-V High Mobility Channel Materials (1 ex.) Tutorial 19 : Device Structure FDSOI (3 ex.) Tutorial 20 : Device Structure DG / FinFET (1 ex.)
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Tutorial 1
General MASTAR Presentation

Description
Objective
this series of exercices intends to present a general view of the MASTAR tool which will be used for all this course on device physics Basic operation and principle are reviewed

Pre-requisite :
none

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Bibliography on MASTAR Model


Introduction to MOSFET Physics, T.Skotnicki, F.Boeuf and T. Poiroux, Chapter 3 of Physics And Operation of Silicon Devices in Integrated Circuits, WILEY ISBN 978-184821-163-6 Optimal scaling methodologies and transistor performance, T. Skotnicki and F. Boeuf Chapter 6 in High-K Gate Dielectric Materials for VLSI MOSFET Applications, H. Huff and D. Gilmer, Eds. New York:Springer Verlag

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Loading MASTAR
1. Open MASTAR directory, then double click on MASTAR.exe

2. Read and Accept the User Agreement


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3. Click on continue
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General Presentation
Roadmap Workspace Device Workspace Adv. Physics Workspace

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What Does MASTAR Compute ?


Device Workspace
Input : 1 Architecture (Bulk, SOI, DG) Geometry, stress, Materials, Power supply

Roadmap Workspace
Input : up to 5 architectures, year of production, familly (HP, LoP, LstP)

Adv. Physics Workspace


Input : specific to each module : Strain, Quantum confinement, FDSOI , Balistic transport

Output : Ion, Ioff, Vth, DIBL, CET, CV/I Graphics Output : Ion/Ioff, Vt-L, performance points (cloud), users Plot Usage : Device (reverse) engineering, platform definition

Output : Basic MOSFET caracteristics Graphics Output : Ion/Ioff vs CMOS node, CV/I vs Year trend-line, gate leakage vs year Usage : long term view of CMOS Roadmaps (e.g. ITRS roadmap)
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Output : (Strain) Silicon band structure (electron and holes), ballistic current, Energy level in confined inversion channel,

Usage : Fine device physics assesment. Longer calculation time

Device Workspace Presentation

Input Window : Device Geometry, Doping, Strain

Output Window : Device Performance :Vth, Ion, Ioff, SS, DIBL, Graphical Representation (Ion/Ioff, Vt-L, DIBL-L

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Roadmap Workspace

Input Window : up to 5 architectures Graphical Representation of the Roadmaps Output Window : Main Device output caracteristics

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Tutorial 2
Creating a Profile (Saving device parameters)

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Description
Objective
this series of exercices intends to learn how to handle the MASTAR software Basic functions are reviewed
Loading/saving data Graphical representation of calculations results in real-time

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Device Workspace Presentation

Input Window : Device Geometry, Doping, Strain

Output Window : Device Performance :Vth, Ion, Ioff, SS, DIBL, Graphical Representation (Ion/Ioff, Vt-L, DIBL-L

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1. Click on View Graphics

2. Select Cloud Ion/Ioff

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Loading Default Profile


4. Close window

1. Click on () icon : this will open the load profile window

2. Select Default.pro

3. Click on the Load button

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1. Device parameters are loaded from the file Default.pro

2. Output is calculated

3. Current Ion/Ioff point is show on the Cloud_Ion/Ioff graph

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Modifing a Profile

1. Play with Nbulk arrows to change channel doping of the MOSFET

2. Current Point is moving on Ion/Ioff Graph 3. Play with other parameters : Vdd, Tox

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Tutorial 3
Device Workspace Basics : Modifying a Profile (Saving device parameters)

Description
Objective
this series of exercices intends to learn how to handle the MASTAR software Basic functions are reviewed
Creating profiles Saving Data

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Device Workspace Presentation

Input Window : Device Geometry, Doping, Strain

Output Window : Device Performance :Vth, Ion, Ioff, SS, DIBL, Graphical Representation (Ion/Ioff, Vt-L, DIBL-L

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1. Click on View Graphics

2. Select Cloud Ion/Ioff

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Loading Default Profile


4. Close window

1. Click on () icon : this will open the load profile window

2. Select Default.pro 3. Click on the Load button

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1. Device parameters are loaded from the file Default.pro

2. Output is calculated

3. Current Ion/Ioff point is show on the Cloud_Ion/Ioff graph

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Ex-1 : Modifing a Profile

1. Play with Nbulk arrows to change channel doping of the MOSFET

2. Current Point is moving on Ion/Ioff Graph 3. Play with other parameters : Vdd, Tox

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Ex-2 : Profile Definition (1)

1. Enter Lg=39nm 2. Enter Tox=1.55nm 3. Enter Xj=15nm 4. Enter Vdd=1.1V 5. Enter Rs=180 Ohm.m 6. Check Conventional Slope

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Ex-2 : Profile Definition (2)

1. Adjust Nbulk, so that Ioff=10nA/m

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Ex-2 : Profile Definition (3)


1. Result is shown here

2. Click on Save-As

3. Name the file ex1_LVT.pro 4. Click on Save

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Ex3 Define another profile


2. Click on Save As

1. Adjust Nbulk, so that Ioff=0.1nA/m 3. Name ex1_SVT.pro , then click on Save

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Tutorial 4
Device Workspace Basics : Creating a Plot File

Description
Objective
this series of exercices intends to learn how to handle the MASTAR software Basic functions are reviewed
Creating a plot file from existing profiles Creating a plot file from a ASCII text file Adjusting the display

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Generate Graphics with MASTAR


GRAPHICS

Profile (.pro)
Stocks MOS parameters

Simple Plot (.plt)


Ion/Ioff target Plot is generated from a texttext-file (ASCII)

MASTAR Plot (.plm)


Collection of profiles Each profile is recalculated to generate the Ion/Ioff MASTAR plot

Clouds (.clo)
Ion/Ioff is generated from a single profile by varying MOS parameters (e.g. Lg, Nbulk ) Experimental Data can be imported from a texttext-file

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Ex 1 - Creating a MASTAR Plot from previously saved Profiles (.pro)

1. Right-click inside the Cloud_Ion_Ioff

2. Select Plot > Edit/Modify Plot

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Ex- 1 : Creating a Plot

1. Click on New Plot

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Ex- 1 : Creating a Plot

1. Name the file example1.plt

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Ex-1 : Creating a Plot

1. The new file appears in the plot list

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Ex-1 : Creating a Plot

1. Click on Profiles

3. Both selected profile should appear in the Profile in Plot list

4. Click on Apply Change , then Close Window

2. Select ex1_LVT.pro by double clicking or use Add>> button. Repeat the operation with ex1_SVT.pro
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Ex- 1 : Creating a Plot

1. A Plot containing the previously saved profiles in created

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Ex-2 :Quick Load a Profile from a Plot


1. Put the mouse cursor on the ex1_LVT profile

2. Click on the Triangle to load the corresponding profile into the Device Workspace

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Ex 3 : Adding another Plot (1)

1. Right-click inside the Cloud_Ion_Ioff

2. Select Plot > Load/Unload Plot

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Ex 3 : Adding another Plot (2)

2. Click Add Button 1. Select ITRS2003_HP_MASTAR.pl m

3. Click Close Button

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Ex 3 : Adding another Plot (3)


1. Plot is only Partially visible

2. Right click in graphic window

3. Select Modify Scale

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Ex 4 : Changing the Plot Scale

1. Set ymax=1000

2. Set xmax=2500 3. Click on Apply

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Ex 4 : Changing the Plot Scale (2)


1. ITRS Roadmap 2003 is now visible

Note : When opening a plot file (.plm), each profile (= plot component) is recalculated. Therefore a plot is not a simple prepre-calculated line but a realreal-time calculated line
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Ex 5 - Creating your own plot (.plt) from text file


1. Open explorer and go to the MASTAR installation directory (e.g. C:\MASTAR) 2. Go to /Data/Plots sub-directories

3. Select plot_example.plt and double click

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Ex 5 : Creating your own plot (.plt) from text file


1. The file is opened in Windows Note Pad Label Perf. Value

2. Syntax is as follows [label displayed in graph] Ion = value in A/m Ioff = value in nA/m

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Displaying your plots


1. Return to MASTAR and open the plot_example.plt file using contextual menu (righ click)

2. Graph is displayed on graph.

Note : Plot are displayed with dotted line and Mastar Plot are displayed with solid lines
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Tutorial 5
Basic Physics of the Electron Mobility in Silicon

Description
Objectives
This series of exercices intends to describe a simplified conduction band-structure of Silicon Conduction band is analyzed for relaxed and strainedSilicon. From Bandstructure calculations, impact on mobility is deduced

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Bibliography
A Comprehensive Modeling Study of Two-Dimensional Silicon Subbands Using a Full-Zone k.p Method, M. Szczap, N. Cavassilas, F. Michelini, F. Payet, F. Boeuf, and T. Skotnicki, In Extented Abstracts of SSDM 2007 (JSAP CAT AP071239), pp. 462-463 Analytical Model for Phonon-Limited Mobility in n-MOS Inversion Layers on Arbitrarily Oriented and Strained Si Surfaces, Mlanie Szczap, Nicolas Cavassilas, Frdric Boeuf, Fabrice Payet and Thomas Skotnicki, in Extented Abstracts of SSDM 2006 (JSAP CAT AP061239), pp 1062-1063 Strained Si/SiGe MOSFET Capacitance modeling based on band structure analysis, F. Gilibert, D. Rideau, F. Payet, F. Boeuf, E. Batail, M. Minondo, R. Bouchakour,T. Skotnicki and H. Jaouen, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.281-285 Low temperature characterization of effective mobility in uniaxially and biaxially strained N-MOSFETs, F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Boeuf and T. Skotnicki, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.525-528

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Note : Ion Enhancement by materials


I DS VDS W = eCox VG Vth VDS 2 L
Transistor Architecture Material Properties Carrier velocity under electric field E in the linear regime: v = E Ecritical Efield
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Velocity

Velocity saturation regime

Note : Mobility In Silicon


E
Shockwave from lattice vibration, or impurities, or gate oxide rugosity every seconds carrier, mass m*

v=

2Ec m*

1.

Small m* : ligth electrons or holes

2. High (less possible collision)

=q
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m
*

Note : Periodic Potential & Band Structure


E
Free Electron Electron in a Periodic Potential Model Krning Peyney

E(k ) =

h 2k 2 2m

V(x)

1 1 2 E = m h2 k 2

k m=m0=9.1e-31 kg ?

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Note : Coupled States


E E1(k) E2(k)
Two electron states are coupled

1 2 =

k
E1 E2

E1 H = E 2
E +E E= 1 2 2 2 2 + 4

Eigenvalues ?
D( ) = =0

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Note : Bangap and Effective Masses


m<m0 or m>m0
1 1 2 E = m h2 k 2

E (u.a)

2 2 E1 + E2 E= + 2 4

Eg

1 1 2 E = m h2 k 2

-1.E+11

-5.E+10

0.E+00 -50 k (1/m)

5.E+10

1.E+11

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Note : Silicon Band-Structure


Silicon Band Structure
ml m
t

(z) 001

(y) 010

(x)100

6 equivalent types of electrons are involved in conduction regime of nMOS 2 types of holes are involved in conduction regime of pMOS : heavy and light

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Note : Longitutinal and Transverse Effective Masses of Electrons

Efield ml =0.92m0
If Electric field is // to the elipsoid, then conduction mass is ml

mt=0.19m0 Efield
If Electric field is to the elipsoid, then conduction mass is mt

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Note : Layout of Strain Module in MASTAR


Cristal and Device orientation configurator Conduction band Iso-energy surface

Strain Configurator

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Note : Choosing Proper Cristal & Device Orientation


Move the camera Choose Cristal Orientation Choose Device in-plane Orientation

Select (100) substrate Select (011) orientation Check device orientation here

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Ex1-Electrons : Relaxed Silicon


1. Load relaxed.xps (1) 2. Observe the 6-equivalent valleys of the conduction band. All Elipsoid have the same size, and relative energy shift is 0.0 eV (2) 3. Remember that electric field for transport is parallel to the Length , i.e. along the gate length direction 4. Direction along the elipsoid, (named longitudinal) have a HEAVY mass, whereas transverse direction have a lighter mass.

(1)

Note : Average conduction mass is 2/3 of mt (light) 1/3 of ml (heavy)

(2)

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Ex2- Electrons : Unixial Tensile Silicon


1. In the strain configurator, click on activate along the gate length (1) 2. Default value is 1000MPa of tensile strain 3. Look at the energy diagrams : Green valleys becomes bigger, meaning that their population increases. Look at the energy shift (2) 4. Lower energy valley is now deltaZ (green), in which the smaller mass is // to the electric field

What about the mobility in tensile strained Silicon ?


(2)

Answer : Most of the carrier will populate a lower mt mass valley. Average conduction mass is then decreasing leading to a higher mobility

Most of carriers will populate the lowest energy valley (100)

(1)

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Ex3 - Electrons : Bi-axial Tensile Strained Silicon


1. In the strain configurator, click on activate along the gate width and the gate length (1) 2. Inout a value of 1500MPa of tensile strain in both direction (this is typicall of Si/SiGe20% ). Resulting stress is then bi-axial and tensile 3. Look at the energy diagrams : Green valleys becomes bigger, meaning that their population increases. Look at the energy shift (2). Shift is higher than in the uni-axial case. 4. Lower energy valley is now deltaZ (green), in which the smaller mass is // to the electric field

What about the mobility in biaxially tensile strained Silicon ?

Answer : Most of the carrier will populate a lower mass valley. Average conduction mass is then decreasing leading to a higher mobility

(2)

Most of carriers will populate the lowest energy valley (100)

(1)

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Ex-4 : Electrons - Uniaxial Compressive Silicon


1. In the strain configurator, click on activate along the gate gate length (1) 2. Replace the value of 1500MPa of tensile strain by -1500 Mpa. This reprent a compressive uniaxial stress along the gate length. 3. Look at the energy diagrams : red and blue valleys becomes bigger, meaning that their population increases. Look at the energy shift (2). 4. Lower energy valleys are now deltaX(red) and delta Y(blue), in which the average mass is 50%mt and 50% ml

What about the mobility in uniaxially strained Silicon ?

Most of carriers will populate these lowest energy valley (001) and (010)

Answer : The Z-valley has a lower enegy, so that there will be less light electrons. So, the average conduction mass is then increasing from {2/3mt,1/3ml} to {1/2mt,1/2ml} leading to a lower mobility
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Tutorial 6
Basic Physics of the Hole Mobility in Silicon

Description
Objectives
This series of exercices intends to describe a simplified valence band-structure of Silicon Valence band is analyzed using a 6x6 k.p. model. Hole population and effective masses are analyzed as a function of stress

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Ex1 : Valence Band of Silicon


1. Load relaxed.xps (1) 2. In theview graphic menu, select 2D band diagram, and zoom on the Valence band 3. Note : the valence band is here calulated using a 6x6 k.p. Hamiltonian, giving information on the fist 3 bands. These bands are note UP (upper), MID (middle) and LOW (lower). 4. Note the effective masses computed at gamma point

(1)

UP

MID

LOW

Note : Most of the carriers Are in the UP and MID (degenerated) Average conduction mass along L for holes is then 66 (0.562+0.148)/2=0.355
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Ex2 : Holes - Iso Energy in the Valence Band


1. In the View Graphics menu, select 3D VB Iso Energy 2. Compute the 3D curve for the upper band, starting from 25meV from the top of the band 3. A highly anisotropic structure is calculated

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Note - Reading the Iso-Enegy of the Valence Band


1. The structure represent all the wave vectors of same energy. Remembering that E~k/m*, this curve shows where k/m* is constant . The effective mass of holes is then highly anisotropic. 2. When m* is large (heavy holes) k is also higher in order to keep energy constant. This is symbolized by the red peaks on the iso-enegy surface. 3. When m* is lower (ligh holes) k is also lower to keep energy constant. This corresponds to the blue divot in the isoenergy surface

Direction with an heavy mass

Direction with an light mass

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Ex3 Holes : Uniaxial Tensile Strain


1. In the strain configurator, click on activate along the gate length (1) 2. Input a value of 1000MPa of tensile strain 3. Look at the energy band diagram

What about the hole mobility in unixaxial tensile strained Silicon ?

(3)

(2)

(1)

Answer : Most of the carrier will populate the heavier mass valley, which also become heavier than in relaxed silicon. Average conduction mass in then increasing. Mobility is decreasing
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Ex4 Holes : Uniaxial Compressive Strain


1. In the strain configurator, click on activate along the gate length (1) 2. Input a value of 2000MPa of compressive strain 3. Look at the energy band diagram

What about the hole mobility in unixaxial tensile strained Silicon ?

(3)

(2)

(1)

Answer : Most of the carrier will populate the UP valley, which also become lighter than in relaxed silicon. Average conduction mass in then decreasing, and mobility is increasing
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Note : Iso Energy of Holes with compressive uniaxial strain

Hole mass along the channel direction are now lighter than on relaxed silicon

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Note : Redistribution in subbands and scattering reduction due to Strained-Si


Fermi-Dirac
0.0

N
Unstrained Si
0.2

Bi-axial BiStrainedStrained -Si


Si/Si0.5Ge0.5 LH E(LH-HH)

Si bulk
-0.1

HH LH

0.1

Energy (eV)

Energy (eV)

-0.2

>80 % in HH
SO

0.0

< 1 % in HH
-0.1 -0.2

-0.3

HH SO

-0.4

-0.5

-0.3

[100]

[110]

[100]

[110]

When straining Si, not only the effective mass of holes and the E carrier population are changed, but also the electron-phonon interaction time is increasing leading to a better mobility
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Main Stress Configurations (1)

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Main Stress Configurations (2)

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Summary of Stress Configurations


Electron Tensile - biaxial Compressive - biaxial Tensile uniaxial - along Lg Compressive uniaxial- along Lg Hole

+ + uniaxial Compression along Lg

++ +

Biaxial Compression

Biaxial Tension

Uniaxial Tension along Lg

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Tutorial 7
Carrier Mobility in MOSFETs

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Effective Mobility
Goal of the exercise
Observe the Effective Mobility behavior as a function of effective field
Use variation on channel doping and length Use variation on gate oxide thickness

Add/remove Mobility enhancement

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Bibliography
On the universality of inversion-layer mobility in nand p-channel MOSFETs S. Takagi; M. Iwase; A. Toriumi, Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International Digital Object Identifier,10.1109/IEDM.1988.32840, Publication Year: 1988 , Page(s): 398 401 On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.; Electron Devices, IEEE Transactions on.Volume: 41 , Issue: 12 Digital Object Identifier: 10.1109/16.337449 Publication Year: 1994 , Page(s): 2357 - 2362

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Note : Universal Mobility Law


From S. Takagi et al.

Surface roughness limited mobility

AC=A0Eeff1/3

log( eff)

1 = 1 + 1 eff AC SR

eff = f (Eeff)
SR=A1Eeff-2

Acoustic phonons limited mobility

Eeff

Eeff depends on transistor parameters :

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Ex-1: Effective Mobility (1)


1. 2. Load Baseline.pro (nMOS transistor). Open Auxiliary eff/Eff in the View Graphics menu

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Ex-1: Effective Mobility (2)


1. Click on the Mobility Tab 2. Deactivate Strain Liner Observe the yellow point going on the univesal curve

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Ex-2: Impact of Pockets


1. Click on the Pocket tab 2. Increase the Dose to 9e13 at/cm3 (1) Observe the yellow point going on the univesal curve
(2)

When Pocket dose , the effective Mobility (eff) decreases : why ?

Answer : When pocket dose , the Vth value is also (2) . Since Eeff (Vg+Vth)/6Tox , Eeff is therefore , therefore eff

(1)

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Ex-3 : Impact of Lgate


1. Decrease gate length from 60nm down to 48nm
(1)

Why is Effective Mobility (eff) increasing when Lgate is

(2)

Answer : When L , due to short channel effects, Vth is (1) Since Eeff (Vg+Vth)/6Tox , Eeff is also , therefore eff (2)

Note to Pr : when decreasing L be carefull of too low Vth (<0)

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Ex- 5 : Impact of Lgate at constant Ioff


1. 2.
(1)

Go back to L=60nm, then check Ioff=constant (1) Re-input L=48nm


(2)

(3)

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Ex- 5 : Impact of Lgate at constant Ioff (2)


Effective Mobility (eff) DECREASES with Lgate when Ioff is constant. Why ?

Answer : 1. When checking Ioff=constant, Channel doping is adjusted automatically to match the given Ioff 2. Due to short channel effects, the S factor is degraded from 90 to 115mV/dec when L (2) 3. To match the same Ioff, Vth has to be higher than before (307mV vs 230mV) 4. Since Eeff (Vg+Vth)/6Tox , Eeff is also , therefore eff (3)

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Ex-6 : Optimal Gate Length


1. 2. 3. Uncheck Ioff=constant and go back to L=60nm open Auxiliary Ion(L) in the View Graphics menu (1) Choose Lmin=45nm, Lmax=100nm, 30 points then click on start (2)
(1)

(2)

Saturation current of the transistor is plotted as a function of Lgate, with Ioff kept constant Observe the optimum of saturation current around L 60nm for 60nm < L < 100nm, Idsat is improved by the decreased in L for L<60nm, the increase in Eeff is degrading eff more rapidly and therefore Idsat drops.

Note to Pr : The optimum value of L depends of several technological parameters, such as Tox and Xj

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Tutorial 8
Carrier Mobility and Drive Current in StrainedMOSFETs

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Drive Current in Strained-Si


Goal of the exercice
Objective is to link the previous exercice on basic of mobility to the performance of MOSFETfabricated with strained-Silicon First, techniques to create strained-Si transistors are shown Second,example of bi-axial strained-si devices are analysed through MASTAR Finally, application of local-strained-Silicon techniques is described and simulated with MASTAR

Pre-requisite : Basics of mobility and Mobility tutorials Contents


Background
Process techniques to create Strain in Silicon channel of a MOSFET transistor

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Bibliography
Non-Uniform Mobility Enhancement Techniques and their Impact on Device Performance Fabrice Payet, Frdric Boeuf, Claude Ortolland* and Thomas Skotnicki, Trans. Electron Devices Volume 55, Issue 4, April 2008 Page(s):1050 1057 Stress Memorization Technique (SMT) Optimization for 45nm CMOS, C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd P. Stolk, F. Boeuf & F. Arnaud , in Digest of Tech. Papers. Symposium on VLSI Technology 2006 (IEEE CAT No 06CH37743), pp 9697. Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm FD SOI Devices with Ultra Thin Silicon Channels , C. Gallon, C. Fenouillet-Beranger, S. Denorme, F. Boeuf, V. Fiori, N. Loubet, A. Vandooren, T. Kormann, M. Broekaart, P. Gouraud, F. Leverd, G. Imbert, C. Chaton, C. Laviron, L. Gabette, F. Vigilant, P. Garnier, H. Bernard, A. Tarnowka, R. Pantel, F. Pionnier, S. Jullian, S. Cristoloveanu and T. Skotnicki, Jpn. J. Appl. Phys. Vol. 45 (2006) Part 1, No. 4B, pp 3058-3063 Strained Si/SiGe MOSFET Capacitance modeling based on band structure analysis, F. Gilibert, D. Rideau, F. Paye, F. Boeuf, E. Batail, M. Minondo, R. Bouchakour,T. Skotnicki and H. Jaouen, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.281-285

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Note : Mobility Enhancement Techniques


SubstrateSubstrate -based ProcessProcess -based Induced Stess

SixGe1-x Based

Cristal Orientation

Liners

SiGe SEG

STI

Bulk

SSOI

In-plane

Out of plane

CESL
Tensile nMOS

SMT
Tensile nMOS

SiGe SD
Compressive

SACVD
Tensile Bi-axial nMOS+pMOS

Tensile bi-axial stress

Natural mobility boost

nMOS+pMOS Si

pMOS Mod.Orientation Si Channel

Compressive pMOS pMOS

SiGe
BULK

box

SSOI

Rotated substrate

Cristal Orientation
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Note : Substrate-Base Strained-Si


Silicon layer sees a bi-axial tensile stress when grown on relaxed Si(1-x)Ge(x)

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Note : mobility improvement

Maximum mobility improvement for electrons ~ x1.8


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Prepare the Exercise


1. 2. Load baseline.pro , note the Ioff value (11.9nA/m) Open the pocket tab and uncheck Pockets (1) Ioff will increase to the lower doping

3. Adjust Nbulk to 1e18 in order to re-adjust Ioff to ~10nA/m 4. Open the mobility Tab and uncheck Activate Strain Liner

(1)

(1)

(2)

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Ex 1 : Global Strained by using substrate


1. 2. 3. 4. Open the Mobility Tab and input K_sub=1.8 (i.e. max mobility improvement) Open the Auxiliary Ion Strain Improvement L Ion(L) Computhe curve into a new Selection (red,blue, green or black) Observe how the Idsat is enhanced by the increased mobility, as a function of L

(1)

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Question

Drive current improvement is not constant with Lgate . WHY ?

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Ex-1 : Answer
with

Long channel devices : L Vdsat Vgt/(1+d) Idsat eff.vgt Idsat/Idsat = eff/eff Short channel devices : L 0 Vdsat L.Ec L.Vsat/eff Idsat Vsat Idsat/Idsat = Vsat/ Vsat

Full calculation of Id enhancement with L by F.Payet et al., T-ED

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Uniaxial Stress By Stressed-Liner


Strained MOSFET (Lg=30nm) by CESL 2D mecanical Simulations Impact on nMOSFETs performances
1.E-06 Vdd=0.9V Strained Unstrained

CESL Tensile

Io ff (A /m )

+15.6%

1.E-07

Tension
(F.Buf et al., IEDM 2004 , SSDM 2004)

1.E-08 250 450 650 Ion (A/m) 850

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Ex-2 : Local Stressor vs eff (1)


Local stressor deposited on the top of the transistor gate creates an important stress pocket on the channel edge Stress depends on Lgate. Mechanical calculation shows that :

See F.Payet et al., TED 2007

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Ex-2 : Local Stressor vs eff (2)


1. 2. 3. Open the Mobility Tab and check Activate Local Strain Re-compute the Ion(L) curve into a new Selection (red,blue, green or black) Observe how the Idsat is enhanced by the increased mobility due to local stress

(1)

(2)

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Ex-2 : Local Stressor vs eff (3)


1. 2. Change the scale of the graphics and plot Ion(L) for L varying between 10m and 45nm (use the red slot) Uncheck Local Strain in the mobility tab, and use the blue slot to plot the Ion(L)
Ion is more improved for short gate length than for long gate length. Why ?

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Ex-2 : Local Stressor vs eff (4)


1. 2. 3. Open the view graphics tab, then select Auxiliary Generic (1) Select Lgate variation from 45nm to 10m Set Lgate as X axis and Mueff as Y axis and plot the result
Effective Mobility (eff) increases when Lgate decreases This comes from the variation of the stress (deformation) applied to the transistor channel. When L is reduced, the tensile stress pockets are overlapping, leading to and increase of mueff for shorter gate length with local stress , mobility is improved on short channel transistors.

(1)

(2)

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Ex-3 : Local Stressor impact on Ion


1. 2. Now, open the view graphics menu and plot Auxialiry Ion Strain Improvement (L) Plot the graphic between 45nm and 10m
Ion improvement is not monotonic Why ?

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Ex-3 : Local Stressor impact on Ion


Answer :
with

Long channel devices : L Vdsat Vgt/(1+d) Idsat eff.vgt Idsat/Idsat = eff/eff Short channel devices : L 0 Vdsat L.Ec L.Vsat/eff Idsat Vsat Idsat/Idsat = Vsat/ Vsat

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Tutorial 9
Coulomb Limited Carrier Mobility

104

Description
Objective of this tutorial is
To introduce the concept of Coulomb-Limited mobility Analyse the impact of Coulomb Scattering (CbS) on MOSFET performance when transistors are shrinked

Content
Background
Coulomb-limited Mobility Modeling Screening Effect Modeling

Ex-1 : plotting eff(Eeff) curves for various channel dopings Ex-2: Performance evolution of scaled MOSFETs with and without CbS
T. Skotnicki & F. Boeuf
105

Bibliography
Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon Masetti, G.; Severi, M.; Solmi, S.; Electron Devices, IEEE Transactions on . Volume: 30 , Issue: 7 Digital Object Identifier: 10.1109/T-ED.1983.21207 Publication Year: 1983 , Page(s): 764 - 769 Impact of Coulomb Scattering on the Characteristics of Nanoscale Devices, Frdric Boeuf, Grard Ghibaudo* and Thomas Skotnicki, Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, Sendai, 2009, pp1048-1049 Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs Mujtaba, A.; Takagi, S.-I.; Dutton, R.; VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on . Digital Object Identifier: 10.1109/VLSIT.1995.520876 Publication Year: 1995 , Page(s): 99 - 100 On the universality of inversion layer mobility in Si MOSFET's: Part Ieffects of substrate impurity concentration Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.; Electron Devices, IEEE Transactions on.Volume: 41 , Issue: 12 Digital Object Identifier: 10.1109/16.337449 Publication Year: 1994 , Page(s): 2357 - 2362
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Note : Universal Mobility Law Cont


Coulombic branch

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Coulomb Limited Mobility


Weak Inversion
Gate
-

Strong Inversion
Gate
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - Neutral -k0r - V(r)~1/r*e Area -

Source

Drain

Source

V(r)~1/r

Electron (holes) transport in the transistor channel is pertubated by the Coulomb potential created by fixed charges. This is called Coulomb Limited Mobility

In strong inversion, the Coulomb potential created by impurities is screened by the inversion layer. This is the Screening Effect , which lowers the impact of Coulombic interaction between carriers and impurities in the on-state of the transistor

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Drain

Weak Inversion Mobility Modeling


From Massetti et al., Coulomb-limited mobility can be expressed as a function of substrate doping concentration (i.e. impurities concentration)

(a) (b)

G. Masetti et al. , IEEE Trans. Elec. Dev, 1983, p764


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Simple Modelisation of the Screening Effect

7.7E16

ac
3E17

sr
7.7E17 2.2E18

c,n c,n c,n

F.Buf et al., SSDM 2009

S. Takagi et al, T-ED, VOL. 41, NO. 12, DECEMBER 1994


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Prepare the Exercise


1. 2. Load baseline.pro , note the Ioff value (11.9nA/m) Open the pocket tab and uncheck Pockets (1) Ioff will increase to the lower doping

3. Adjust Nbulk to 1e18 in order to re-adjust Ioff to ~10nA/m 4. Open the mobility Tab and uncheck Activate Strain Liner

(1)

(1)

(2)

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Plotting Mobility Law : eff vs Eeff

Vdd is used to generate Eff variation

Select Eeff for X and eff for Y axis

Click on Compute In order to avoid scale issue in the display NB : select Red then compute, then select Blue and compute, Green and compute and finally Black and compute

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Ex- 1 : Plotting eff vs Eeff

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Ex-1 : Plotting eff vs Eeff with Coulomb Scattering [CbS] (1)

(2)

(1)

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Ex- 1 : Plotting eff vs Eeff with Coulomb Scattering [CbS] (2)


Change channel doping from 3e17 at/cm to 1e18 at/cm as shown on the graph (1) Plot a new curve (color) for each case

(1)

3e17

7e17

1e18

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Exercise 2 : CMOS L-scaling w/o CbS


L=60nm =281cm/Vs, Eeff=0.94MV/cm Ion=692A/m

Same Ioff L-shrink

L=50nm =276cm/Vs, Eeff=0.96MV/cm Ion=694A/m

Coulomb interaction is off

NB : Ioff constant must be checked !

Performance increases thanks to reduced L-Gate


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Ex- 2 : CMOS L-scaling w/ CbS


L=60nm =262cm/Vs, Eeff=0.94MV/cm Ion=679A/m

Same Ioff L-shrink

L=50nm =? , Eff = ? , Ion = ?

?
Coulomb interaction is on

Performance ? Why ?
NB : Ioff constant must be checked !

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Ex-2 : Answer
Performance is this time degraded ! In order to keep Ioff constant, channel doping is increased when L is decreased to 50nm. The CbS is then higher, and mobility is now decribes by the blue curve below which is lower than the previous case (green). As a consequence, Ion is decreasing .

L=60nm Ion=678A/m

L=50nm Ion=666A/m

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Tutorial 10
Using the System Layout Module

119

Objective
Objective is to review the basic operation of the System Layout module of MASTAR
Plotting I-V curves of nMOS and pMOS Creating Layout of Inverters and SRAM Simulating speed of Ring Oscillators

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Module Overview
MOSFET window Inverter Cell SRAM Layout

Id-Vd and Id-Vg Capacitance Window

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Ex- 1 : Plotting I-V curves (1)

1-Click on the green arrow to load Device profiles : nMOS pMOS Pass Gate transistor for SRAM calculation

2-I-V are automatically calculated

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Click in View Graphic to display graphical output window

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Ex- 1 : Plotting I-V curves (3)


On any graphic window, right click to open a contextual menu

e.g. on Id(Vd) curve, right click then select Compute

T. Skotnicki & F. Boeuf

Smooth = 0

adjust = 1.13 Reference point from device calculation (no interpolation)

Smooth = 0.1

adjust = 0.93

T. Skotnicki & F. Boeuf

Ex-2 : Computing Inverter Delay (1)


To start, you need to load at least two (inverter) or 3 (SRAM) device profile (n & p + PassGate)

T. Skotnicki & F. Boeuf

Ex-2 : Computing Inverter Delay (2)

Cgd is automatically calculated by using Cgate+Miller (overlap+outerfringe), with gate heigth = 2*Lgate

3 enter parasitic capacitance values Cj,ch Cj,bot

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Ex-2 : Computing Inverter Delay (3)

4 Input you inverter layout It can be saved independantly or with the whole system profile

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Ex-2 : Computing Inverter Delay (4)


You can enter manually the layout parameters And save/load them

Note : Gate length comes from the device profile

T. Skotnicki & F. Boeuf

Ex-2 : Computing Inverter Delay (5)

Interter delay in then calculted automatically using a Cload= 1fF Then results for various FO are displayed

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Ex-2 : Computing Inverter Delay (6)

Interter delay in then calculted automatically using a Cload= 1fF Then results for various FO are displayed

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Ex-2 : Computing Inverter Delay (7)


Result can be monitored by going into ViewGraphics > Tp inverter

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This graph show the Vout of each inverter node in the case of a single calculation

Preference can be modified (! FanOut is not used here)

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Statiscal data on Tp @ C=1fF repartition is displayed

You can also generate random variation on inverter generation by checking the box, and enter the number of wanted calculation

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Ex-3 : Computing Inverter Delay including interconnections

Another way to compute delay is proposed by including R and C lines

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