RIPPLE CARRY ADDER: A ripple carry adder has multiple 1-bit adder blocks to perform addition of two N-bit

binary numbers. Maximum value of N in our case is 64.The ripple carry adder circuit has less operating speed i.e. usually takes more time for calculation of sum. The reason behind that is every 1-bit adder in the block has to wait for the carry generated from the previous full adder, in order to generate the sum and output carry. The 1-bit adder worst case propagation delay is 2 tg (assuming a sum of products expression for sum and carry ignoring delay for inverters) where tg is the time delay of 1 gate to process the given input .The worst case propagation delay of 64 bit adder will be 128 tg gate delays. If we assume each gate delay of 10ns then the worst case delay will be 1280ns. Sum of an individual 1-bit adder can be calculated by using the Boolean equation Sum= (A xor B) xor cin A, B, cin are the inputs to the 1-bit adder circuit

If we observe the longest path in schematic circuit diagram of 1-bit adder for the estimation of worst case propagation delay occurred in calculation of output carry and sum.it is observed that for the calculation of carry output, the worst case propagation delay is 30ns (assuming 10ns of delay for each gate) and 20ns for sum.so the worst case delay for computing the sum of 64 bit-adder will be (64*20=128ns) Carry look ahead adder: A popular first addition technique is carry look-ahead (cla) addition which is accomplished using 1-bit partial full adder circuits. Carry signals are calculated in advance depending on the input signals. It uses two concepts for the generation of output carry, which are carry generate and carry propagate. Let A (i) and B (i) are the given input bits and i is the position of the bit. Then carry output of cla ca be calculated by using the formulae G(i) (CARRY GENERATE)=A(i) AND B(i) IF A, B is 1 for some i.it implies that particular bits have generated the carry output irrespective of the (i1) bits carry out generation. Which will act as carry input for ith position bits. P(i) (carry propagate)=A(i) xor B(i) If one of the given A(i) and B(i) input is 1 and the other is zero. so in these case carry output cannot be generated without the propagation of carryout of i-1 position bit to the ith position bit as an input carry So C(i+1)( carryout)=G(i) or (p(i) and cin) Sum=A(i) XOR B(i) XOR C(i) Here we have three gate delays for the generation of c(i) The worst case delay of a 64 bit adder circuit is 10tg which is 100ns