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STM32VL- Training

Tunis Jan 2012

V1.0
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CONTENTS
PART I : CORTEX-M3

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PART II : STM32F100 device

PART III : STM32 Value line Discovery Kit

PART - I

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CORTEX M3

CONTENTS
Objectives Introduction Cortex-M3 Processor Cortex M3 interrupt handling Cortex-M3 Memory Map Power Management System Timer (SysTick) Debug Capabilities

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OBJECTIVES

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Familiarize with Cortex M3 At the end of the part you will be able to List the main features of the Cortex M3

CONTENTS
Objectives Introduction Cortex-M3 Processor Cortex M3 interrupt handling Cortex-M3 Memory Map Power Management System Timer (SysTick) Debug Capabilities

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What is ARM(Advanced Risc Machines)?

ARM is an UK company that designs innovative 32-bit microprocessors ARM leads the world of RISC microprocessor cores ARM develops directly and through partnership the tools, systems and services to support its architecture.

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Why use an ARM-based processor?

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Sales in billions of dollars

Why Cortex M3?

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More Than 28 company ST, NXP, Atmel, Samsung

Cortex-A Series, applications processors for complex OS and user applications. Cortex-R Series, real-time systems profile. Cortex-M Series, microcontroller profile optimized for cost-sensitive applications..

The number at the end of the Cortex name refers to the relative performance level, with 1 the lowest and 8 the highest.
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ARM Cortex processor family

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CONTENTS
Objectives Introduction Cortex-M3 Processor Cortex M3 interrupt handling Cortex-M3 Memory Map Power Management System Timer (SysTick) Debug Capabilities

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Cortex-M3 Processor
Interrupt controller: -1 to 240 interrupts. - 256 Priority levels - Hard Fault -SysTick (Porting !!!) Wakup Int. controller: Wakeup from Sleep modes throuht interrupts & exceptions Debug Access port

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Hierarchical processor integrating core and advanced system peripherals

CM3 Core: Harvard (Separate Busses) 32 Bits Register & ALUs.

Embedded Trace MacroCell Optional Memory Protection Unit (8 regions)

WIC

Integrated Trace module: Low cost (2 wires)

4 Watch points 8 Hardware Breakpoints Multi layer Bus Matrix (Parallel transfers between core, memory, & peripherals
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Cortex-M3 Processor

Cortex-M3 Processor Main Features

ARM v7M Architecture Thumb-2 Instruction Set Architecture
Mix of 16 and 32 bit instructions for very high code density

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Harvard architecture
Separate I & D buses allow parallel instruction fetching & data storage

Integrated Nested Vectored Interrupt Controller (NVIC) Vector Table is addresses. Integrated Bus Matrix Data memory management 3 Stage Pipeline Integrated System Timer (SysTick) for Real Time OS

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Data Memory management (1/7)

Cortex-M3 includes two technologies to reduce Data memory requirements: 1. Unaligned Data Support 2. Atomic Bit Banding

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These technologies can dramatically improve data (SRAM) memory utilization, potentially enabling silicon designers and users to reduce the amount of SRAM required and dramatically impacting silicon usage.

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Data Memory management(2/7)

Unaligned Data Support:
Other Core does not support unaligned data Long (32) Long (32) short (16) short (16) Char Char Char Char ARM Cortex-M3 supports unaligned data that can improve SRAM utilization Long (32) Long (32) short (16) short (16) Char Char Char Char

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Data aligned on word boundaries

Unused (wasted) space

Free space Can be used

Reduces SRAM Memory Requirements By Over 50%

Less Memory - LowER Cost devices

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Data Memory management(3/7)

Structure management example

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long (32) char (8)

long (32) char (8) long long (32) char (8) char (8) char (8) long (32) int (16)c int (16) long

32bit machine which does not support unaligned data

long (32) char (8) char (8) char (8)

int (16) long

Data aligned

int (16) long (32) int (16)c int (16) long (32) char (8)

char (8)

long (32)

Unused (wasted) space

Free space for the rest of the application

Reduces SRAM Memory Requirements By Over 25%

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Data Memory management(4/7)

Bit Banding:
Traditional method
Disable external events Read byte (RAM, register) 32bit @Rbase+N b31

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Speed and code size optimized Cortex-M3 implementation

REAL memory image

0 1 0 0 1 0 1 1
Mask and modify bit element

b0

example: 20000000h to 200FFFFFh

X X X X X 1 X X
Write byte (RAM, register)

b31

0 1 0 0 1 1 1 1 b0
Enable external events

VIRTUAL aliased bit banding image

Bit Banding done by bus matrix. Single instruction Read/Modify/Write (no more masking). No new instruction set Use standard data one (AND, OR, XOR). Optimized RAM, peripherals and IOs registers accesses Easy multi-task semaphore management
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Data Memory management(5/7)

32MB alias region

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1MB Peripheral bit-band region

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Data Memory management(6/7)

Bit Banding

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Each bit of the bit band region (1MB) is mapped to one 32 bit address (32 MB Bit Band Alias = Virtual zone ). Each bit in the Bit Band region can be accessed separately through the corresponding 32 bits register in the alias region.

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Data Memory management(7/7)

Bit Banding
Bit Banding formula (mapping the bit to the register) is:

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bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number 4) where: bit_word_addr: is the address of the word in the alias memory region that maps to the targeted bit. bit_band_base is the starting address of the alias region (0x22000000 or 0x42000000 ) byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position of the targeted bit(0-7).

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Data Memory management: exercice

Bit Banding
Example -1:

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How to map bit 15 of the byte located at address 0x40000300 in the alias region. Solution: We are accessing the peripheral bit band region beginning at 0x 0x40000000 and mapped to the bit band alias zone with bit_band_base = 0x42000000

Byte_offset = 0x40000300 - 0x40000000 = 0x300 0x42000000 + ( 0x301*32) + (7 * 4) = 0x4200603C =bit_word_addr Reading address 0x4200603C returns the value of bit 15 of the byte at address 0x40000300. Writing to address 0x4200609C has the same effect as a readmodify-write operation on bit 15 of the byte at address 0x40000300.
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Instruction Pipeline(1/3)
PC points to fetch stage:
FETCH
Instruction fetched from memory

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DECODE

Instruction decoded

Register(s) read from Register Bank

EXECUTE

Shift and ALU operation or memory access Write register(s) back to Register Bank

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Instruction Pipeline(2/3)
Optimal Pipelining:
Cycle Operation ADD SUB ORR AND ORR EOR F- Fetch D - Decode F D F E D F E D F E D F E D F E - Execute E D E 1 2 3 4 5 6 7 8 9

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All operations here are registers (single cycle execution) In this example it takes 6 cycles to execute 6 instructions Clock cycles per Instructions (CPI) = 1
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Instruction Pipeline(3/3)
Flushing : A flush of the pipeline can occur because of
A Branch An exception A breakpoint Branch Pipeline Example:
1 F D F E D F F D F E D F F- Fetch D - Decode E - Execute E D E 2 3 4 5 6 7 8

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Cycle Address Operation 0x8000 B 0x8FEC 0x8002 0x8004 0x8FEC 0x8FEE 0x8FF0 SUB ORR AND ORR EOR

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Register Set(1/2)
Registers R0-R12 are simple registers that can be used to hold program variables. Registers R13-R15 have special functions within the Cortex CPU.
R13: Register R13 is used as the stack pointer R14: called the link register. used to store the return address when a call is made to a procedure R15: is the program counter
Register Set
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13(SP) R14(LR) R15 (PC) xPSR

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xPSR:The Program Status Register contains status fields for instruction execution

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CONTENTS
Objectives Introduction Cortex-M3 Processor Cortex M3 interrupt handling Cortex-M3 Memory Map System Timer (SysTick) Debug Capabilities

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Interrupt Handling
The Cortex-M3 processor integrates an advanced Nested Vectored Interrupt Controller (NVIC)
The NVIC supports up to 240 dynamically reprioritizes interrupts each with up to 256 levels of priority Supports advanced features for next generation real-time applications: Tail-chaining of pending interrupts Interrupt Pre-emption Late Arrival

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Interrupt Response- Tail Chaining(1/3)

Highest

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IRQ1 IRQ2 42 CYCLES ARM7 PUSH 26

Tail-chaining

Interrupt handling in assembler code

ISR 1

POP 16

PUSH 26

ISR 2

POP 16

Interrupt handling in HW

Cortex-M3

PUSH 12

ISR 1 6 6 CYCLES

ISR 2

POP 12

ARM7 26 cycles from IRQ1 to ISR1 entered Up to 42 cycles 42 cycles from ISR1 exit to ISR2 entry 16 cycles to return from ISR2

Cortex-M3 12 cycles from IRQ1 to ISR1 entered 12 cycles 6 cycles from ISR1 exit to ISR2 entry 12 cycles to return from ISR2

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Interrupt Response Preemption(2/3)

Highest

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IRQ1 IRQ2 42 CYCLES ARM7 ISR 1 POP 16 Cortex-M3 ISR 1 POP

111

PUSH 2 26 ISR 2 6

ISR 2

POP 16

POP 12

7-18 CYCLES

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Interrupt Response Late Arriving(3/3)

Less than 12 cycle IRQ1
Highest

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IRQ2 ARM7 PUSH 26 Cortex-M3

PUSH

PUSH 26 ISR 1
TailChaining

ISR 1

POP 16

ISR 2

POP 16

ISR 2 6

POP 12

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Interrupt Response Lab

More than12 cycle
Highest

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NMI IRQ1 IRQ2 IRQ3 Less than12 cycle

PUSH PUSH

NMI

ISR 1

POP

ISR 2

ISR 3

POP

ISR 2 Starts

Push for ISR1 begins Pre-empted by NMI New instruction fetch in

parallel minimises time to NMI

Cortex-M3 Following NMI processor tail-chains into ISR1 ISR2 Completed Pop only occurs on return to Main

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NVIC Registers
Each interrupt input has several registers to control it Enable/Disable Bit
Enable or disable the interrupt Can be set, cleared or read

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Pending Bit
If the pending bit is set, then the interrupt is pending A pending interrupt can only be taken (become active) if it is enabled and it has sufficient priority to run

Pending bit can be set, cleared or read Active Bit

A bit is set if the interrupt is executing or active-stacked Active-stacked means the interrupt was executing, but was preempted by another higher-priority interrupt Active register is normally read only

Priority field priority management for each interrupt

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Cortex-M3 Exception Types

No. 1 2 3 4 5 6 7-10 11 12 13 14 15 16 256 Exception Type Reset NMI Hard Fault MemManage Fault Bus Fault Usage Fault Reserved SVCall Debug Monitor Reserved PendSV SYSTICK Interrupt #0 .. Interrupt#240 Priority -3 (Highest) -2 -1 0 1 2 N.A. 3 4 N.A. 5 6 7 247 Type of Priority fixed fixed fixed settable settable settable N.A. settable settable N.A. settable settable settable settable settable Pendable request for System Device System Tick Timer External Interrupt #0 .. External Interrupt #240 System Service call Reset Non-Maskable Interrupt Default fault if other hander not implemented Descriptions

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MPU violation or access to illegal locations Fault if AHB interface receives error Exceptions due to program errors

Break points, watch points, external debug

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CONTENTS
Objectives Introduction Cortex-M3 Processor Cortex M3 interrupt handling Cortex-M3 Memory Map Power Management System Timer (SysTick) Debug Capabilities

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System Timer (SysTick)

Flexible system timer 24-bit self-reloading down counter with end of count interrupt generation 2 configurable Clock sources Suitable for Real Time OS or other scheduled tasks
In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8 (provided externally by the Reset Clock Control )

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CONTENTS
Objectives Introduction
What is ARM ? Why use an ARM-based processor? Cortex-M3 Processor Main Features Data Memory Instruction Pipeline Write Buffer

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Cortex-M3 Processor

Privilege, Modes, Stacks and Register Set Cortex M3 interrupt handling

Exception/Interrupt Handling, NVIC Registers Cortex-M3 Exception Types Vector Table

Cortex-M3 Memory Map Power Management System Timer (SysTick) Debug Capabilities
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Debug Capabilities
Three solutions are possible :
JTAG SWD

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More pins available for the application

Joint Test Action Group easy flashed application debugging

2 hardware breakpoints 8 hardware breakpoints

Serial Wire Debug for targeted low bandwidth data trace

Enhanced Thematic Mapper capability for better real time debugging

Instruction trace only

ETM

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PART - II

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STM32F10x Device

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CONTENTS
Objectives STM32F10x Device
Block Diagram Memory mapping and boot modes System Architecture

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STM32F10x System Peripherals

Main features

STM32F10x Minimum External Components STM32F10x standard peripheral Library

What is CMSIS? Package organization STM32F10xxx standard peripheral library architecture Coding conventions Using the Library
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OBJECTIVES
Familiarize with STM32F10x device At the end of the training you will be able to

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List the main features of the STM32F10x system peripherals Configure the standard library environment Develop your applications using the STM32F10x standard library

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CONTENTS
Objectives STM32F10x Device
Block Diagram Memory mapping and boot modes System Architecture

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STM32F10x System Peripherals

Main features

STM32F10x Minimum External Components STM32F10x standard peripheral Library

What is CMSIS? Package organization STM32F10xxx standard peripheral library architecture Coding conventions Using the Library
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More choice with STM32 series

The general purpose F-1 series addresses a wide range of applications, from the lowest price-sensitive design to the computing intensive, high memory Footprint Get the highest performance with the F-2 series for computing intensive application and advanced connectivity. The F-2 series maintains the compatibility with the F-1 series. Get the highest performance with the Design ultra-low-power applications with the L-1 series for those who are power conscious and seek the absolute lowest energy consumption. The L-1 series maintains the compatibility with the F-1 series.

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STM32 portfolio based on F1 series

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STM32 Value line 16K-32KBytes block diagram

Core and operating conditions
ARM Cortex-M3 1.25 DMIPS/MHz up to 24 MHz 2.0 V to 3.6 V range -40 to +105 C
Flash I/F

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CORTEXTM-M3 CPU
24 MHz ARM Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz)

16kB - 32kB Flash Memory 4kB SRAM

Power Supply
Reg 1.8V

POR/PDR/PVD XTAL oscillators

32KHz + 4~25MHz

JTAG/SW Debug
Nested vect IT Ctrl

20B Backup Data

Int. RC oscillators
40KHz + 8MHz

Rich connectivity
5 communications peripherals

1 x Systick Timer

PLL RTC / AWU

Advanced analog
12-bit1.2 s conversion time ADC Dual channel 12-bit DAC

DMA
7 Channels

Clock Control Bridge

ARM Peripheral Bus 1
(max 24MHz)

Bridge ARM Peripheral Bus 2

1 x 16-bit PWM

Enhanced control
16-bit motor control timer 5x 16-bit PWM timers

Synchronized AC Timer

5 x 16-bit timer
(max 24MHz)

1 x CEC

Up to 16 Ext. ITs 37/51 I/Os

2 x Watchdog
(independent & window)

2-channel 12-bit DAC

1 x USART/LIN
Smartcard / IrDa Modem Control

LQFP48, LQFP/BGA64

1 x SPI 1 x USART/LIN
Smartcard/IrDa Modem Control

1 x 12-bit ADC up to 16 channels Temperature Sensor 1 x I 2C

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STM32 Value line 64K-128KBytes block diagram

Core and operating conditions
ARM Cortex-M3 1.25 DMIPS/MHz up to 24 MHz 2.0 V to 3.6 V range -40 to +105 C CORTEXTM-M3 CPU
24 MHz ARM Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz)
Flash I/F

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64kB - 128kB Flash Memory 8kB SRAM

Power Supply
Reg 1.8V

POR/PDR/PVD XTAL oscillators

32KHz + 4~25MHz

JTAG/SW Debug
Nested vect IT Ctrl

20B Backup Data

Int. RC oscillators
40KHz + 8MHz

Rich connectivity
8 communications peripherals

1 x Systick Timer DMA

7 Channels

PLL RTC / AWU

Clock Control Bridge

ARM Peripheral Bus1
(max 24MHz)

Advanced analog
12-bit1.2 s conversion time ADC Dual channel 12-bit DAC
1 x 16-bit PWM
Synchronized AC Timer

Bridge ARM Peripheral Bus2 6 x 16-bit Timer

(max 24MHz)

1 x CEC

Enhanced control
16-bit motor control timer 6x 16-bit PWM timers

Up to 16 Ext. ITs 37/51/80 I/Os 1 x SPI

2 x Watchdog
(independent & window)

2-channel 12-bit DAC

2 x USART/LIN
Smartcard / IrDa Modem Control

LQFP48, LQFP/BGA64, LQFP100

1 x USART/LIN
Smartcard/IrDa Modem Control

1 x 12-bit ADC up to16 channels Temperature Sensor

1 x SPI 2 x I 2C

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STM32 Value line 256K-512KBytes block diagram

Flash I/F

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Core and operating conditions

ARM Cortex-M3 1.25 DMIPS/MHz up to 24 MHz 2.0 V to 3.6 V range -40 to +105 C

CORTEXTM-M3 CPU 24 MHz

256KB-512kB Flash Memory

Power Supply
Reg 1.8V

POR/PDR/PVD

ARM Lite Hi-Speed 36us Matrix / Arbiter (max 24MHz)

24KB-32kB SRAM 84B Backup Data

XTAL oscillators
32KHz + 4~25MHz

JTAG/SW Debug
Nested vect IT Ctrl

Int. RC oscillators
40KHz + 8MHz

Rich connectivity
11 communications peripherals

1 x Systick Timer

FSMC
SRAM/ NOR/ LCD parallel interface

PLL

DMA up to 12 Channels

Clock Control Bridge Bridge

ARM Peripheral Bus 1
(max 24MHz)

RTC / AWU

FSMC
SRAM, NOR, memories support. LCD Parallel interface 8/16-bit Intel 8080 and Motorola 68K

1 x 16-bit PWM

ARM Peripheral Bus 2

Synchronized AC Timer

10 x 16-bit Timer 2 x Watchdog

(independent & window)

Enhanced control
16-bit motor control timer 10x 16-bit PWM timers

1 x CEC

Up to 16 Ext. ITs 51/80/112 I/Os 1 x SPI

(max 24MHz)

4 x USART/LIN
2-channel 12-bit DAC
Smartcard / IrDa Modem Control

LQFP64, LQFP100, LQFP144

1 x USART/LIN
Smartcard/IrDa Modem Control

1 x 12-bit ADC up to 16 channels

2 x SPI 2 x I2C

Temperature Sensor

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Memory Mapping and Boot Modes

Addressable memory space of 4 GBytes RAM : up to 32 kBytes FLASH : up to 512 kBytes

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Boot modes:
Depending on the Boot configuration - Embedded Flash Memory - System Memory - Embedded SRAM Memory is aliased at @0x00
BOOT Mode Selection Pins BOOT1 x 0 BOOT0 0 1 1 User Flash User Flash is selected as boot space SystemMemory is selected as boot space Embedded SRAM is selected as boot space

0xFFFF FFFF 0xE010 0000 0xE00F FFFF

Reserved Cortex-M3 internal peripherals

Reserved

0xE000 0000

0x1FFF F80F 0x1FFF F800 0x1FFF F7FF

Reserved

Option Bytes SystemMemory

Boot Mode

Aliasing

0x1FFF F000

Reserved

SystemMemory Embedded SRAM

0x4000 0000

Peripherals Reserved
Flash

0x0801 FFFF

0x0800 0000

0x2000 0000

SRAM Reserved

SystemMemory: contains the Bootloader

used to re-program the FLASH through USART1.

0x0000 0000

CODE

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STM32F10x :Boot Modes

Boot mode = System Memory For applications where firmware update is performed frequently (example: Satellite receiver, Playsattion, etc).

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System memory

The CPU executes the boot loader: 1) Data packets containing code are Received through through serial peripheral (UART). The Flash is reprogrammed with the new received code

CPU

(Boot Loader)

ata packets (code)

UART

Bus Matrix

Flash (Application Code)

2)

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CONTENTS
Objectives STM32F10x Device
Block Diagram Memory mapping and boot modes System Architecture

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STM32F10x System Peripherals

Main features

STM32F10x Minimum External Components STM32F10x standard peripheral Library

What is CMSIS? Package organization STM32F10xxx standard peripheral library architecture Coding conventions Using the Library
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STM32F101x Series Block Diagram

Flash I/F

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CORTEXTM-M3 CPU 24 MHz

256KB-512kB Flash Memory

Power Supply
Reg 1.8V

POR/PDR/PVD

ARM Lite Hi-Speed 36us Matrix / Arbiter (max 24MHz)

24KB-32kB SRAM 84B Backup Data

XTAL oscillators
32KHz + 4~25MHz

JTAG/SW Debug
Nested vect IT Ctrl

Int. RC oscillators
40KHz + 8MHz

1 x Systick Timer

FSMC
SRAM/ NOR/ LCD parallel interface

PLL

DMA up to 12 Channels

Clock Control Bridge Bridge

ARM Peripheral Bus
(max 24MHz)

RTC / AWU

1 x 16-bit PWM
Synchronized AC Timer

Up to 16 Ext. ITs 51/80/112 I/Os 1 x SPI 1 x USART/LIN

Smartcard/IrDa Modem Control

ARM Peripheral Bus

10 x 16-bit Timer 2 x Watchdog

(independent & window)

1 x CEC

(max 24MHz)

4 x USART/LIN
2-channel 12-bit DAC
Smartcard / IrDa Modem Control

1 x 12-bit ADC up to 16 channels

2 x SPI 2 x I2C

Temperature Sensor

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Power Control (PWR) and Backup Domain (BKP)

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Power Supply
Power Supply Schemes
VDD = 2.0 to 3.6 V: External Power Supply for I/Os and the internal regulator. VDDA = 2.0 to 3.6 V: External Analog Power supplies for ADC, Reset blocks, RCs and PLL. ADC working only if VDDA 2.4 V VBAT = 1.8 to 3.6 V: For Backup domain when VDD is not present.
VBAT

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VDDA domain
VREFVREF+ VDDA VSSA A/D converter Temp. sensor Reset block PLL

VDD domain
I/O Rings STANDBY circuitry (Wake-up logic, IWDG, RCC CSR reg) Voltage Regulator

V18 domain

VSS VDD

Core Memories Digital peripherals

Low Voltage Detector

Backup domain
LSE crystal 32K osc BKP registers RCC BDCR register RTC

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Power On Reset / Power Down Reset

Integrated POR(Power On Reset )/ PDR(Power Down Reset ): circuitry guarantees proper product reset when voltage is not in the product guaranteed voltage range (2V to 3.6V)
No need for external reset circuit

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VDD

Vtrh Vtrl

POR
40mv hysteresis

PDR

Tempo 2ms

Reset

POR and PDR have a typical hysteresis of 40mV

Vtrl min 1.8V / Vtrh max 2V

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Programmable Voltage Detector (PVD)

Programmable Voltage Detector(PVD)
Enabled by software Monitor the VDD power supply by comparing it to a threshold Threshold configurable from 2.2V to 2.9V by step of 100mV
VDD

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PVD Threshold

100mv hysteresis

PVD Output

Threshold

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Low Power Modes

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STM32F10x Low Power modes: uses CortexM3 Sleep modes

SLEEP, STOP and STANDBY modes
The reset circuitry, POR/PDR, is active in STANDBY and STOP modes
Feature
Consumption in RUN mode w/ execute from Flash on internal RC and peripherals clock ON Consumption in RUN mode w/ execute from Flash on PLL 24 MHz (HSE : external clock = 8MHz) and peripherals clock ON Consumption in RUN mode w/ execute from Flash on PLL 24 MHz (HSE : external clock = 8MHz) and peripherals clock OFF STOP w/ Voltage Regulator in low power Low speed and high-speed internal RC oscillators and high-speed oscillator OFF(no independent watchdog) STANDBY w/ low-speed oscillator and RTC OFF Low-speed internal RC oscillator and independent watchdog OFF RTC on VBAT

STM32F10x typ
4.9mA 36mA 27mA 14A

(*)

2A 1.4 A

(*) : Typical

values are measured at TA = 25 C, VDD/VBAT = 3.3 V.

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CONTENTS
Objectives STM32F10x Device
Block Diagram Memory mapping and boot modes System Architecture

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STM32F10x System Peripherals

Main features

STM32F10x Minimum External Components STM32F10x standard peripheral Library

What is CMSIS? Package organization STM32F10xxx standard peripheral library architecture Coding conventions Using the Library
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What is CMSIS?
Definition:

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The Cortex-M3 Microcontroller Software Interface Standard (CMSIS) is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems and middleware components. For more details, please refer to www.onarm.com.

CMSIS layer structure

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Package organization

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STM32F10xxx standard peripheral library architecture

- STM32 interrupt IRQ list/ Specific options for the Cortex-M3 core - STM32 peripheral memory mapping and physical register address definition - Configuration options User application

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Cortex-M3 exceptions

Peripheral header file

Include NVIC and SysTick drivers

Low-level & API functions to Perform basic operations offered by the peripheral
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Using the Library (1/4)

following functions: RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx , ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx , ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx , ENABLE);

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1) Before configuring a peripheral, you have to enable its clock by calling one of the

2) PPP_DeInit(..) function can be used to set all PPPs peripheral registers to their reset values: PPP_DeInit(PPPx); 3) If after peripheral configuration, the user wants to modify one or more peripheral settings he should proceed as following: PPP_InitStucture.memberX = valX; PPP_InitStructure.memberY = valY; PPP_Init(PPPx, &PPP_InitStructure);

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Using the Library (2/4)

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At this stage the PPP peripheral is initialized and can be enabled by making a call to PPP_Cmd(..) function: PPP_Cmd(PPPx, ENABLE); Note: This function is used only for communication peripherals like UART, SPI, To access the functionality of the PPP peripheral, the user can use a set of dedicated functions. These functions are specific to the peripheral and for more details refer to STM32F10x Firmware Library User Manual.

Example of GPIO Functions available

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Using the Library (3/4)

UART1 configuration example :
/* Enable USART1 Clock */

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RCC_APB2PeriphClockCmd( USART1, ENABLE ); /* set all UART1s peripheral registers to their reset values */ USART_DeInit( USART1 ) ;
/* USART1 configuration ------------------------------------------------------*/ /* USART1 configured as follow: - BaudRate = 19200 baud - Word Length = 8 Bits - One Stop Bit - Even parity - Hardware flow control disabled (RTS and CTS signals) - Receive and transmit enabled */

USART_InitStructure.USART_BaudRate = 9600; USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_Parity = USART_Parity_Even; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
/* Configure USART1 */

USART_Init( USART1, &USART_InitStructure);

/* Enable USART1 */

USART_Cmd( USART1, ENABLE );

USART 1 is ready now

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Using the Library (4/4)

Files to be modified by the user:
stm32f10x_conf.h
/* Includes -----------------------------------------------------------------*/ /* Uncomment the line below to enable peripheral header file inclusion */ /* #include "stm32f10x_adc.h" */ /* #include "stm32f10x_bkp.h" */ /* #include "stm32f10x_can.h" */

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main.c

#include "stm32f10x.h int main(void) { ... GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); }

stm32f10x_It.h

stm32f10x.h

/* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) /* #define STM32F10X_LD */ /*!< STM32 Low density devices */ #endif /* STM32F10x Interrupt Number Definition*/
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */

/* Exported functions ----------------------------------------------- */ void NMI_Handler(void); void HardFault_Handler(void); stm32f10x_It.c #include "stm32f10x_it.h" void EXTI1_IRQHandler(void) { GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); }

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PART - III

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STM32 Value line Discovery Kit

64

STM32 Value line Discovery Kit

-CSF-Training-

Microcontroller Division of MMS Group June, 2010

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The cheapest and quickest way to discover the STM32

Everything included for a quick start with the STM32 Value Line
Price: $9.90 (RRP) Order code: STM32VLDISCOVERY Available NOW from ST and Distributors

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In circuit ST-LINK debugger / programmer included to debug Discovery kit applications or other target board applications. Ideal for quick evaluation, learning or prototyping Dedicated web site www.st.com/stm32-discovery
Examples ready to run Schematics Forums and more

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STM32 Value line Discovery Board

A compact all in one board The debugger ST-link is on the board itself Few leds and button for immediate usage The extension connector will all STM32 pins enable building more complex applications by using an extension board The board can be used as an independent ST-link for your own board if needed
Extension connector On each side

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ST-LINK SWD connector

84mm

STM32F100RBT6B User button Led Blue Led Green

42mm

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Tools and Software

Development Toolchain support
Free Atollic TrueSTUDIO lite version with unlimited code-size and usage-time. IAR EWARM KEIL MDK-ARM

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Software examples available at www.st.com/stm32-discovery for a quick start to evaluate and develop with the STM32 Value line

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Features and Benefits

Feature STM32F100RBT6B microcontroller Benefit Discover STM32 with STM32 Value line, including 128-Kbyte Flash, 8-Kbyte RAM in a 64pin LQFP Immediate plug-and-play demonstration Adapts the demo to the future application environment Non-intrusive debug with the in-circuit debugger present on STM32 Value line Discovery. The kit can be used as an ST-link for your own board Ideal for prototyping and easy probing. Enable quick connection to a prototyping board Complete kit enabling full software development, no need for additional software. Fast startup, accelerate your developments.

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Self powered by USB cable between PC and STM32 Value line Discovery Can supply target application with 5 V and 3 V On-board ST-Link with USB interface for programming and debugging Selection mode switch to use the kit as a standalone ST-Link (with SWD connector) Extension header for all QFP64 I/Os Development toolchains from partners Large number of free, downloadable ready-touse software examples

More than 37 Videos are available on YouTube web site. example: link : http://www.youtube.com/watch?v=5Si0tgqrAd0
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STM32F100xx Value Line necessary docs

RM0041 (Reference Manual): Peripherals description PM0063 (Flash Programming Manual): Flash description Product Datasheet STM32F100x468B-B: Electrical parameters

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STM32F10x Standard Peripheral Library V3.3.0: STM32 value Line Firmware library, examples AN3268 (STM32VLDISCOVERY firmware package): STM32 discovery Firmware library UM0919 (STM32VLDISCOVERY STM32 value line Discovery): STM32 discovery board description, schematics UM0985 (Developing your STM32VLDISCOVERY application using the IAR Embedded Workbench software): Tools description...

All docs are available from www.st.com/mcu

70

Contact us

-CSF-Training-

1- Systmes Embarqus Consulting: C (STM32, PIC...), Embedded C, VHDL

a. Email: SystemesEmbarquesConsulting@gmail.com b. Page faceBook :https://www.facebook.com/Systemes.Embarques.Consulting c. Marketing phone number: +216 52 02 16 71

2- Linux embarqu Consulting (Embedded Linux)

a. Email: LinuxEmbarquesConsulting@gmail.com b. Page faceBook : https://www.facebook.com/Linux.embarque c. Marketing phone number: +216 52 02 16 71

3- Formation RH: Interview, CV,

a. Email: Tunisieformationrh@gmail.com b. Page faceBook : https://www.facebook.com/FormationRH c. Marketing phone number: +216 21 33 33 91

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Now you are able to

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Develop your application around STM32F100 device

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Thank you

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