Analog Integrated Circuits and Signal Processing, 21, 229252 (1999)

# 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for
Low Voltage/Low Power CMOS Circuit Design
DANIEL FOTY
Gilgamesh Associates, Fletcher VT 05444
E-mail: dfoty@sover.net
Received May 1, 1996; Revised April 16, 1997; Accepted April 23, 1997
Abstract. The present ``state of the art'' in analytical MOSFET modeling for SPICE circuit simulation is
reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulation
represents an ``upper limit'' of what is possible from any type of model, but that good parameter extraction is
required to most closely approach that limit. The individual model types presently in common use are examined,
with discussion of the behavior of each model, its strengths and weaknesses, its applicability to certain types of
circuits, and criteria that a circuit design ``consumer'' can employ to judge a model before using it for circuit
design. Some related issues, such as node charge and gate capacitance modeling, charge conservation, and
statistical simulation of process variations, are also evaluated. Finally, new trends, directions, and requirements of
MOSFET modeling for circuit simulation are considered.
Key Words:
1. Introduction
In the past several years, the integrated circuit
business has grown into a major international
industry. ICs are appearing in a wider and more
diverse set of applications, many of which were not
considered until recently.
During this time, CMOS has emerged as the
technology of choice for IC fabrication [1]. CMOS
has achieved a dominant position due to its inherently
low power consumption, the ability to follow simple
scaling laws [2], excellent stability of operation,
relative ease of manufacturing, and the ability of a
single process technology to be used exibly for
numerous applications. Signicantly, supply is
creating its own demand; much of the new growth
in IC usage is occurring outside of the traditional
``computational'' area. It perhaps can be said that in
the near future, ``If it doesn't rot, it will have silicon
in it.''
As applications proliferate and fabrication tech-
nology takes on commodity dynamics, the need
increases for improved modeling and simulation
capabilities. These capabilities are important for the
reduction of the number of ``fab-and-x'' cycles,
improvement of nal circuit yields, and reduction of
total development costs. With SPICE [3,4] rmly in
place as the de facto circuit simulation standard, the
required improvements in the ability to model
MOSFETs must occur within this existing framework.
The requirements on MOSFET modeling are
becoming more stringent, due to the increased use
of analog circuits, the integration of mixed digital and
analog functions on the same chip, and the growth of
low power applications; in all these cases, the margin
for error in the MOSFET models is greatly reduced.
To simulate CMOS circuits, these MOSFET
models, which serve as a representative of the
underlying fabrication technology, must be invoked.
Thus, the MOSFET models serve as the critical link
between the circuit designer and the fabrication
facility. This use of the MOSFET models becomes
even more important for the emerging fabless design
industry, as the circuit designers are separated from
their foundries, both geographically and philosophi-
cally. In this situation, the MOSFET models serve as
the ``communication vehicle'' between the circuit
designer and the foundry.
This discussion would seem to indicate that new
methods and MOSFET models will be required to
improve the situation. However, this is not fully the
case; much of the existing ``infrastructure'' for
analytical MOSFET modeling can be put to better
use, through improved parameter extraction and
model building techniques, and more ``enlightened''
use of these models by circuit designers. Existing and
widely available MOSFET models can, with careful
parameter extraction, be made to serve most of the
present circuit design needs. In addition, a circuit
designer can, by becoming familiar with the details of
each type of model, evaluate incoming models before
their use to determine if they are adequate for the
particular circuit design application in question.
2. Analytical MOSFET Modeling for Circuit
Simulation
SPICE, the Simulation Program with Integrated
Circuit Emphasis, was developed at the University
of California/Berkeley during the late 1960s [3,4]. It
was a successor to an earlier effort with the somewhat
dubious moniker of CANCER [5]. With its academic
origins, the core of SPICE was made publicly and
widely available; thus, SPICE became the de facto
circuit simulation standard of an emerging industry.
SPICE introduced a fully numerical approach to
circuit simulation, in which the circuit nodes dene a
matrix and the external nodes provide the boundary
conditions. The matrix is constructed and solved,
producing the circuit behavior. This approach relies
heavily on element sub-models of the various
components of the circuit. These components range
from the very simple (e.g. a resistor) to the very
complex (e.g. the MOSFET).
It is interesting to note that the original MOSFET
model used in SPICE [6] predates the development of
numerical circuit simulation, and was instead devel-
oped to provide a physical understanding of the
behavior of the MOSFET. In fact, the working
MOSFET was a relatively new element at that time,
and was not very important to early users of SPICE. It
is only more recently that the development of
MOSFET models began to focus on their circuit
simulation usage. This is an interesting piece of
history, which still colors the relationship between
SPICE and its available MOSFET models.
The development of new and improved analytical
descriptions of MOSFET behavior is not the focus of
this paper. Instead, this problem will be approached as
one in which both designers and model builders are
attempting to make the best use of existing models.
Thus, there are two distinct sides of the situation to be
considered. The rst is the structure and formulation
of the equations of the MOSFET model, while the
second is the parameter extraction and model building
that are necessary to assemble a parameter list for a
specic process technology. This division must be
clearly understood and emphasized. The model
formulation represents the ``upper limit'' of what a
particular type of analytical MOSFET model is
capable of achieving. ``Informed'' parameter extrac-
tion and model building are required to most closely
approach that limit and make the best use of the
capabilities of that particular type of MOSFET model.
The best circuit simulation results are obtained when a
designer employs MOSFET models which are
accurate, mathematically robust and efcient, amen-
able to workable parameter extraction, and suitable
for the particular circuit design applications under
consideration.
It is important to note that when the analytical
model structure itself is incapable of properly
modeling some physical effect, a clumsy stop-gap
solution of limited validity is often invoked; this
``solution'' is usually constructed for a small region of
device operation, but is not generally valid. The
designer should be aware of situations where this
practice is commonly envoked.
In an ideal world, the behavior of MOSFETs would
be completely understood on a purely physical basis.
The listing of model parameter values could be
compiled directly from routine process characteriza-
tion measurements, and the MOSFET model ``deck''
would be nished. Unfortunately, the present reality
differs considerably from this ideal situation. All
analytical model formulations contain some degree of
empirical character; this forces the introduction of
semi-empirical and empirical model parameters
which must be determined by parameter extraction.
Therefore, analytical MOSFET models contain
two types of parameters. Process parameters are
treated as physically meaningful, and their values are
taken directly from routine process characterization
measurements. Electrical parameters cannot be
determined from process characterization; their
values must instead be determined by non-linear
least squares tting to measured electrical data. As a
230 D. Foty
consequence, these parameters usually lack true
physical meaning.
3. Details of the MOSFET Models
Today, virtually all the analytical MOSFET models in
use for circuit simulation are based on the ``original''
1964 description of a long, wide transistor [6]. Over
time, various small geometry effects have been added
as ``corrections''; this process has continued for three
decades. This approach has introduced considerable
and increasing complexity into the MOSFET models.
In general, each ``new and improved'' model
includes several new small geometry ``corrections''.
However, the observer will note another clear trend
that continues to grow in importance. The mathema-
tical ``tness'' of the analytical formulation has
received increasing attention; as a result, the
mathematical behavior of the model equations
during circuit simulation has gradually overridden
``physical understanding'', and the empirical char-
acter of the models continues to increase. In addition,
during most of the history of MOS model develop-
ment, the main ``driver'' was advancing fabrication
technology; however, in recent years, this situation
has changed dramatically. MOS model development
is now largely driven by the increasing use of subtle
and detailed features of MOSFET behavior in
advanced circuit design.
In examining the MOSFET models which are
presently in use in popular SPICE circuit simulators,
three clear generations of models can be noted. The
rst generation models include Level 1, Level 2, and
Level 3. These are relatively physical models, which
are strongly connected to the process technology. The
device geometry is contained entirely in the model
equations, and a small set of model parameters is used
to describe the device behavior. Radical changes were
introduced with the second generation models, which
include BSIM, HSPICE Level 28 (a BSIM deriva-
tive), and BSIM2. In these models, extensive
mathematical conditioning was introduced, with a
clear emphasis on the behavior of the model equations
during circuit simulation. Model parameters are
determined in isolation for each MOSFET of a set
of devices; then, geometry dependence is introduced
by tting a second ``layer'' of parameters to the
``individual'' parameters. As a result, these models
take on a degree of empirical character that far
exceeds that found in the rst generation models. As a
consequence, the model formulation becomes less
important, as the core of the effort to correctly
describe device behavior shifts to parameter extrac-
tion and model building.
At this time, the third generation of MOSFET
models is just beginning to emerge. Models such as
BSIM3, MOS Model 9, and EKV are being included
in mainstream SPICE circuit simulation packages,
and new models are appearing as third generation
``candidates'' which may (or may not) nd wide-
spread acceptance and usage. The ``original intent'' of
these efforts was a return to simpler, more physically-
based models (vs. the situation in the second
generation models). Further improvements in mathe-
matical conditioning are being developed, including
the introduction of specially designed ``smoothing
functions'' for the description of the various transition
regions in the device behavior. New developments are
appearing regularly in this area, and this trend is
expected to continue.
The individual MOSFET models will now be
considered in some detail. The following discussion
will focus on the strengths and weaknesses of each
model in practical use; for a more extensive
discussion of model structure and parameter determi-
nation, the reader is referred to a detailed text on the
subject [7].
3.1. First Generation Models
3.1.1. Level 1. The Level 1 model is basically
identical to the ``original'' 1964 model [6], and is very
similar to the MOSFET model which is typically
developed in a standard undergraduate text on
semiconductor devices [8]. The model formulation
employs the gradual channel approximation; that is,
the depletion charge is taken as varying negligibly
along the channel. This leads to the ``square law'' for
the saturated drain current, in the form
I
ds;sat

mC
ox
W
eff
L
eff
? V
gs
V
t

2
1
The only small geometry effect included in the Level
1 formulation is an empirical method of accounting
for the effect of channel length modulation on the
device current. It is assumed that the saturation
Perspectives on Analytical Modeling of Small Geometry MOSFETs 231
current increases linearly with increasing drain
voltage; this allows (1) to be slightly modied to
I
ds;sat

mC
ox
W
eff
L
eff
? V
gs
V
t

2
? 1 LAMBDA? V
ds

2
As shown in Fig. 1, this method describes a single
point on the x-axis toward which all the saturation
curves extrapolate; this method is similar to the
introduction of the Early voltage [9] into bipolar
transistor models. No subthreshold current model is
included in Level 1.
The Level 1 model can be regarded as obsolete and
inappropriate for modern MOSFET technology. It is
only useful as a teaching instrument for an intro-
ductory discussion of analytical MOSFET modeling.
For example, model parameters can be extracted with
a hand calculator, which can be a useful pedigogical
exercise. The Level 1 model also has some utility for
hand calculations, since it is the only model (until
recently) with an equation set simple enough for such
usage.
3.1.2. Level 2. The Level 2 model [10] represents
the rst attempt to include small geometry effects in
an analytical MOSFET model in SPICE. The effort is
very complex and detailed, and leads to a very
complicated model that has limited usefulness.
In contrast to Level 1, Level 2 includes a detailed
description of the MOSFET depletion region for
implementation in the threshold voltage model [11];
drain-induced barrier lowering (DIBL), however, is
not included. The channel mobility is not treated as a
constant; instead, a model [12,13] is used which
accounts for the decrease in the mobility with
increasing vertical eld,
m
s
UO
e
Si
C
ox
?
UCRIT
V
gs
V
t

_ _
UEXP
3
for values of the vertical eld larger than a ``critical
eld'' (represented by UCRIT), the mobility
decreases with increasing vertical eld. Meanwhile,
the effect of the lateral eld is neglected.
The drain current model is derived by integrating
the depletion charge model [14], leading to
I
ds

mW
eff
C
ox
L
eff
L
0
V
gs
V
fb
2f
f

_ _
? V
0
ds

V
0
ds
2
_

2
3
f
s
? g ? V
ds
2f
f
V
bs

3
2
2f
f
V
bs

3
2
_ _
f
n
?
V
0
ds
2
2f
f
V
bs
? V
0
ds
_ __
4
where
V
0
dsat
minV
ds
; V
dsat
5
While essentially accurate, note that (4) contains two
3
2
-power terms which in practice are computationally
inefcient.
The reduction of the saturation voltage by carrier
velocity saturation [15] is included; however, the
derivation used in Level 2 produces a hideously
complex and inefcient quartic expression. Despite
the detail and complexity of the drain current model
and the saturation voltage model, a rather poor result
is produced in short channel devices, as shown in Fig.
2(a). Note the severe discontinuity in the rst
derivative of the drain current at V
ds
V
dsat
.
A subthreshold current model is also introduced
with Level 2 [16]. The model is very simple, and
includes only one parameter; thus, it has very limited
validity, and can only be t to one particular value of
channel length, drain voltage, and temperature. While
continuity at the weak-strong inversion transition
point is guaranteed, the rst derivative of the current is
discontinuous at this point, as shown in Fig. 2(b). This
can lead to convergence problems during circuit
simulation.
Overall, the Level 2 model is very complex
mathematically, and thus is slow and inefcient
Fig. 1. The Level 1 description of the saturation region current,
which implies that all the saturated current curves have the same
x-intercept at 1/LAMBDA.
232 D. Foty
during circuit simulation; convergence problems are
also frequently encountered. At this time, Level 2 has
fallen into disuse, as it was largely replaced with
Level 3. Somewhat interestingly, Level 2 still nds
some use due to its inclusion of the Level 1 ``l-
model'' for the saturation region current (see Fig. 1).
The model parameter LAMBDA can be taken to
represent the output conductance g
ds
and used in
analog circuit design; this is the case in a popular text
on that subject [17]. However, it should be noted that
while this approach can be useful for a ``rst pass''
description of device behavior, the output conduc-
tance behavior of a MOSFET is much more
complicated than the ``l-model'' allows. For a
``real'' analog circuit simulation, a more advanced
model (such as HSPICE Level 28 or BSIM3) should
be employed.
Another problem with Level 2 is that the extracted
and constructed model can be made to work well at
only one geometry. For example, if the circuit
designer changes the value of the channel length to
one other than the specic choice used for parameter
extraction and model development, the correlation
between the model and the MOSFET data will
deteriorate.
3.1.3. Level 3. Although it is similar in structure to
Level 2, Level 3 [10] was developed to address the
shortcomings of its predecessor. Most importantly,
Level 3 introduces a semi-empirical approach; this
causes Level 3 to be at least as accurate as Level 2,
while being much more efcient during circuit
simulation. Much more emphasis is placed on
parameter extraction for the description of device
behavior, in contrast to the Level 2 approach of
computing various effects ``internally'' using a small
number of ``physically-based'' parameters. Added
physical effects include DIBL and the reduction of the
mobility by the lateral eld. Level 3 has proven to be a
simple and relatively efcient model, and has been
used very successfully for digital circuit design;
therefore, it is still in wide use today.
In structure, the Level 3 description of the device
depletion region is similar to the Level 2 model, but is
mathematically improved [18]. The effect of the
vertical eld on the mobility is included through a
simple semi-empirical model which has proven to be
quite accurate:
m
v

UO
1 THETA? V
gs
VTO
6
Note that since the parameter VTO represents the
``zero bias'' threshold voltage, this model neglects the
effect of the substrate bias on the mobility. In contrast
to Level 2, the effect of the lateral eld on the mobility
is also taken into account; the carrier saturation
velocity is used to compute a reduced value of the
saturation voltage in the form
(a)
Fig. 2.
b
Level 2 results for a W/L20 mm/0.7 mm device; (a)
saturation characteristics; note the severe rst derivative
discontinuity in the model at V
ds
V
dsat
; (b) subthreshold region;
note the rst derivitave discontinuity in the neighborhood of V
t
.
Perspectives on Analytical Modeling of Small Geometry MOSFETs 233
V
dsat

V
gs
V
t

1
f
s
? g
42f
f
V
bs

1
2
f
n
_ _
VMAX? L
eff
m
eff

V
gs
V
t

1
f
s
? g
42f
f
V
bs

1
2
f
n
_ _
_

_
_

_
2

VMAX? L
eff
m
eff
_ _
2

_
7
This expression is much simpler and more efcient
than its Level 2 counterpart. Also, improved results
are achieved, as shown in Fig. 3(a). Note, however,
that a rst derivative discontinuity is still present in
the model results at V
ds
V
dsat
; the effect of this
``kink'' will be discussed more fully below.
The drain current description begins with a Level 2-
like expression; then, a Taylor expansion is used [19]
on the depletion charge expression to eliminate the
3
2
-
power terms which proved to be inefcient in Level 2.
Signicantly, this represents the rst instance of
``mathematical conditioning'' in a SPICE MOSFET
model. The basic drain current expression is
(a)
(b)
(c) (d)
Fig. 3. Level 3 results; (a) saturation characteristics of a W/L20 mm/0.7 mm device; note that a derivative discontinuity is present at
V
ds
V
dsat
; but that it is much less severe than the one which occurs in the Level 2 results (Fig. 2(a)); (b) a modied geometric scheme
for the construction of a ``binned'' model; ve devices are used here, rather than three; (c) the molded drain current vs. the channel length,
V
gs
V
ds
5:0 V, showing the discontinuity at the L0.9 mm bin boundary; (d) a comparison of the modeled and measured output
conductance; due to the discontinuity in the rst derivative introduced by the model for V
dsat
, the Level 3 model gives a very poor result,
rendering it unsuitable for analog applications.
234 D. Foty
I
ds

m
eff
C
ox
W
eff
L
eff
L
0
?
_
V
gs
V
t
? V
0
ds

V
0
ds
2
2
? 1
f
s
? g
42f
f
V
bs

1
2
f
n
_ __
8
where V
0
ds
is given by (4). The subthreshold current
model developed for use in Level 2 is also
implemented in Level 3, and is subject to the same
shortcomings.
As in Level 2, an extracted Level 3 model works
well for only one device geometry; if the channel
length is changed to a value different than the one
chosen for model construction, the ability of the
model to describe the data deteriorates. A clumsy
solution to this problem is the introduction of model
``binning''. In this method, the length-width geometry
``space'' is broken up into sub-regions, as shown in
Fig. 3(b); each sub-region will have its own
independent model. This approach is commonly
used in the integrated circuit industry. However,
binning introduces problems of its own. The models,
such as Level 3, are not designed to accommodate
binning; as a result, the drain current (and other
modeled device properties) will be discontinuous at
the bin boundaries, as shown in Fig. 3(c). A model
result such as this can be disastrous if a circuit
designer optimizes one or more channel lengths in a
particular circuit. Problems are also encountered if
this boundary is present during statistical simulations.
However, Level 3 is a relatively simple, robust, and
reliable model, and has been used very successfully
for many years. It remains very popular for digital
circuit design, is efcient for very large circuits, and is
widely available in all SPICE circuit simulators.
While Level 3 is useful, it does contain some
drawbacks of which the circuit designer should be
aware, so that Level 3 is not pushed beyond its useful
limits. As noted in Fig. 3(a), there is a discontinuity in
the derivative of the drain current at the saturation
voltage point; an experienced user will note that this
problem becomes more severe in shorter channel
length devices. In addition to possible convergence
problems and slowing of circuit simulations, Level 3
produces very poor results for the output conductance,
as shown in Fig. 3(d). Finally, the subthreshold model
is very weak and of limited validity. As a result of
these shortcomings, Level 3 is not suitable for analog
circuit design; a more advanced model should be used
for that purpose.
3.2. Second Generation Models
3.2.1. Second Generation Model Structure. Before
discussing the individual second generation models, a
few detailed comments on their basic structure must
be made. As noted earlier, the second generation
models represent a radical departure from their rst
generation predecessors. The device geometry
(channel length and width) is contained in the model
equations (as in the rst generation models); however,
in addition, separate geometry parameters are
included.
The basic second generation parameter structure is
best illustrated through a brief description of the
parameter extraction process. A set of devices is
chosen for model building. In the rst phase of model
construction, sets of model parameters are extracted
completely independently for each of these devices;
these parameters are extracted for the device model
equations (the ``intrinsic model structure''). In the
second phase of model construction, a second
``layer'' of model parameters is t to the parameters
determined during the rst phase; the rst phase
parameters are used as ``data,'', and the geometry
dependence is introduced using the ``extrinsic model
structure,'' in the form
Z Z
LZ
L
eff

WZ
W
eff
9
The nal model parameter deck will contain Z, LZ,
and WZ; thus, model parameters actually are
determined in ``triplets'' (e.g. X3MS, LX3MS, and
WX3MS). The goal of the scheme described by (9) is
to take a particular combination of L
eff
and W
eff
, and
use the model parameters Z, LZ, and WZ to
``reconstitute'' the value of Z which was originally
extracted in the rst phase for that particular device
geometry.
3.2.2. BSIM. BSIM [20,21] is the rst of the second
generation models. In its formulation, a clear shift of
emphasis to mathematical conditioning for circuit
simulation usage is noted. The approach to small
geometry effects is strictly empirical; while this
Perspectives on Analytical Modeling of Small Geometry MOSFETs 235
improves the nal model results, any connection of
the model to the underlying process technology is
greatly weakened. Due to this empirical approach, and
the ``two layer'' parameter structure described above,
in BSIM (and the other second generation models),
the model structure becomes more of a shell, and the
real ``work'' (and burden) of producing good model
results shifts to parameter extraction.
In addition to the major structural changes, several
improvements were introduced into BSIM. Most
notably, BSIM contains a more physically-based and
generally useful subthreshold model. In addition, the
threshold voltage model is improved with additional
terms to describe more detailed device behavior.
The BSIM depletion charge model is similar to the
Level 3 description, but eventually leads to a
simplied expression. The threshold voltage model
contains an expanded expression that is basically
empirical, but which allows more detailed accuracy,
for the description of, for example, non-uniform
substrate doping. The basic mobility model is a
composite expression which employs a three point
interpolation for its description. The effect of the
vertical eld on the mobility is included in a manner
similar to that used in Level 3 (although in BSIM the
substrate bias dependence is included), while lateral
eld effects are immersed in the drain current model.
The basis of the BSIM drain current model is quite
complex, with a rather complicated derivation;
however, by the careful introduction of composite
terms, rather simple nal expressions are reached.
Polynomial expressions are used to replace the
3
2
-
power terms which appear when the basic depletion
charge expression is integrated; this leads to the
expression for the linear region drain current:
I
ds;lin

m
v
C
ox
W
eff
L
eff
? V
gs
V
t
? V
ds

a
2
? V
2
ds
_ _
10
As in the earlier models, BSIM includes a description
for the reduction of the saturation voltage by carrier
velocity saturation. A rather simple expression for the
saturation voltage is produced:
V
dsat

V
gs
V
t
a ? K
1
2
11
The saturation region current expression is then
I
ds;sat
I
ds;sat

m
v
C
ox
W
eff
L
eff
?
1
2 ? a ? K
_ _
? V
gs
V
t

2
12
Typical results are depicted in Fig. 4(a). Note that the
mathematical structure of the BSIM result is much
better than Level 2 and Level 3; the severe rst
derivative discontinuity at the saturation voltage,
present in the earlier models, does not occur here.
However, some loss of model accuracy in the
neighborhood of the saturation voltage is clearly
visible; this will be discussed below.
BSIM also includes a more detailed subthreshold
current model [22], which is mathematically condi-
tioned to repair the derivative discontinuity at the
weak inversion-strong inversion transition which
occurs in earlier models [23]:
I
weak

I
exp
? I
limit
I
exp
I
limit
13
I
exp

m
v
C
ox
W
eff
L
eff
?
k
b
T
q
_ _
2
e
1:8
? e
q
k
b
T
V
gs
V
t
=n
? 1 e

q
k
b
T
? V
ds
_ _
14
I
limit
I
ds

m
v
C
ox
W
eff
2L
eff
? 3 ?
k
b
T
q
_ _
2
15
As shown in Fig. 4(b), the results are considerably
improved. With several parameters in (13), this model
is more generally applicable.
Overall, BSIM represents a major mathematical
improvement over its predecessors, and in general
demonstrates better circuit simulation behavior.
However, BSIM demonstrates some loss of accuracy
in submicron devices (usually for L
eff
51 mm and
t
ox
515 nm); this can be seen in Fig. 4(a), where the
model does not perform well in the neighborhood of
the saturation voltage. The geometry scheme
described by (9) begins to break down in submicron
devices, which would force the use of model
``binning'' with its associated problems. This
``extrinsic'' model structure assumes that the indivi-
dual device parameters will vary linearly with
1
L
eff
and
1
W
eff
; this assumption is, in practice, rather poor, and
has the effect of degrading the nal model results,
particularly for ``intermediate'' geometries. In addi-
tion, the polynomial expressions can behave quite
236 D. Foty
badly in certain circumstances; this is particularly true
of the quadratic expressions, which can ``go the
wrong way'' when used outside of their originally-
intended range. For example, negative values of the
output conductance g
ds
can occur under some
circumstances Fig. 4(c), such as for low gate biases.
The fraction
g
m
I
ds
is not monotonic at V
gs
V
t
; this can
cause convergence problems.
Another structural problem with BSIM is the
independent calculation of a strong inversion current
I
strong
and a weak inversion current I
weak
. The
development of BSIM was focused on digital circuit
design; it is thus assumed that I
strong
4I
weak
, and the
total drain current is computed from
I
total
I
strong
I
weak
16
However, this assumption is poor for low drain biases;
here, I
strong
&I
weak
, and (16) provides a poor descrip-
tion. As a result, BSIM predicts a ``jump'' in the drain
current at the transition, as shown in Fig. 4(d). Finally,
although the drain current description is good, there is
no independent accounting for the output conduc-
tance. Thus, overall, BSIM is an improved model for
(a) (b)
(c) (d)
Fig. 4. BSIM results for a W=L 20 mm=0:7 mm device: (a) saturation characteristics; the results are much improved over those of Level 2
(Fig. 2) and Level 3 Fig. 3(a); (b) subthreshold region; these results are much better than those produced by the model used in Level 2 and
Level 3 Fig. 2(b); (c) result with a gate bias of V
gs
1:0 V; note the negative output conductance for high drain biases; (d) detail in the
weak-strong inversion transition region, V
ds
0:1 V; note the ``jump'' in the characteristic near V
gs
0:9 V due to the simple addition of
the weak and strong inversion currents.
Perspectives on Analytical Modeling of Small Geometry MOSFETs 237
digital circuit design, but is not suitable for analog
circuit design.
The reader should note that the improvements in
BSIM are paid for with a more complex mathematical
formulation; although the results are better than those
of Level 3, the simplicity of Level 3 makes it faster
and more efcient in circuit simulation. However,
BSIM is less likely to encounter convergence
problems.
3.2.3. HSPICE Level 28. HSPICE Level 28 is a
proprietary MOSFET model developed by Meta-
Software and introduced through its popular HSPICE
simulator [24]. HSPICE Level 28 is based on BSIM,
but is extensively modied. Since most of the model
formulation is proprietary, many of the specic details
are difcult to discuss. However, HSPICE Level 28
has demonstrated good results and is extensively used
in industry, particularly for analog circuit design.
A unique feature of HSPICE Level 28 is the
admission that model binning will be necessary; thus,
the model is designed to accommodate binning and to
cope with the side effects. Of particular note, it is
possible to ensure the continuity of the drain current
(and other model characteristics) across the bin
boundaries.
Instead of (9), HSPICE Level 28 employs a
geometry expression of the form
Z ZO LZ?
1
L
eff

1
L
ref
_ _
WZ?
1
W
eff

1
W
ref
_ _
PZ?
1
L
eff

1
L
ref
_ _
?
1
W
eff

1
W
ref
_ _
17
In contrast to BSIM, HSPICE Level 28 model
parameters appear in quadruplets.
The features of (17) are best illustrated by
examining bin 1 of Fig. 5(a). As shown, different
values of L
ref
and W
ref
can be set in each bin (Fig. 12
shows the values for bin 1, L
ref ;1
and W
ref ;1
). Along
the length axis, at point a, the continuity of the value
of Z is guaranteed (the reader may wish to use (17) to
verify this). Similarly, along the width axis, continuity
is guaranteed at point b. Another feature of HSPICE
Level 28 is the introduction of the product term in
(17). The use of the product term guarantees
continuity across point c. The availability of the
product term improves the model accuracy from what
would be possible with only the length and width
terms; in addition, this approach guarantees continuity
of parameters across the ``faces'' of the bins. As
shown in Fig. 5(b), the drain current is continuous
across a bin boundary; this is in contrast to the results
for a binned Level 3 model (see Fig. 3(c)).
(a)
Fig. 5.
b
The HSPICE Level 28 binning scheme; (a) a description
of how the L, W, and P parameters affect model continuity across
bin boundaries; (b) the modeled drain current vs. channel length,
V
gs
V
ds
5:0 V, showing a continuous result across the bin
boundary at L 0:9 mm; this is in contrast to the Level 3 result
Fig. 3(c), which shows a discontinuity at this bin boundary.
238 D. Foty
As to the underlying equations, as noted earlier,
HSPICE Level 28 is a modied version of BSIM.
There are slight modications to the BSIM mobility
and threshold voltage models; in the latter, the
quadratic expressions from BSIM are extensively
conditioned. The current equations are basically the
same, but the transition regions receive extensive
conditioning. This improves the behavior of the model
during circuit simulation, and also makes it suitable
for use in analog circuit design. In particular, a
transition region between the linear and saturation
regions is dened in the neighborhood of the
saturation voltage; this leads to good current Fig.
6(a) and output conductance Fig. 6(b) results. Also,
the subthreshold model parametrically denes mul-
tiple sub-regions around the weak-strong inversion
transition. This eliminates the ``jump'' in the current
which can occur in BSIM for low drain biases (see
Fig. 4(d)), and also produces a monotonic result for
g
m
I
ds
at V
gs
V
t
. Good results are produced, as shown in
Fig. 6(c) and Fig. 6(d). The negative output
conductance problem of BSIM Fig. 4(c) is not present
in HSPICE Level 28, as shown in Fig. 6(e).
Overall, HSPICE Level 28 shows a very clear
emphasis on the circuit simulation usage of the model.
The model parameter set is almost entirely empirical,
and there is very strong emphasis on the conditioning
of the transition regions to make good tting results
possible. An interesting aspect of HSPICE Level 28 is
its circuit simulation behavior. Given the basic BSIM
structure used in HSPICE Level 28, it would be
expected that the complexity of the formulation would
lead to slow circuit simulation speed. particularly as
BSIM is known to be slower than Level 3 [25].
However, the extensive conditioning of the transition
regions pays off quite well; in practice, HSPICE Level
28 is surprisingly fast, often faster than Level 3.
A structural problem with HSPICE Level 28 is that
it locks the user to HSPICE as a circuit simulator. This
can conict with the preferences of individual users.
In addition, there are sometimes compatibility
problems with other simulation packages; interfaces
to HSPICE may not exist in those packages, and/or the
other packages may require availability of the model
equations.
3.2.4. BSIM2. BSIM2 [26] is closely based on
BSIM, but has been modied and improved for use
with submicron MOSFET technologies. In contrast to
BSIM, one current expression is used for both the
linear and saturation regions of operation; a new
subthreshold current model is also introduced. Most
notably, an output conductance model is added; this
makes BSIM2 suitable for analog circuit design.
The BSIM2 threshold voltage model modies the
BSIM expression so that the possible negative output
conductance (which can occur in BSIM) will not
occur in BSIM2. The mobility adds a quadratic term
in V
gs
V
t
; this improves the accuracy of the
description for large vertical elds.
The drain current model modies the BSIM linear
region expression to improve the short channel
accuracy. One current equation for both the linear
and saturation region results:
I
ds

m
o
C
ox
W
eff
L
eff
?
V
gs
V
t
? V
0
ds

a
2
? V
0
ds
2
_ _
1 U
a
? V
gs
V
t
U
b
? V
gs
V
t

2
_ _

U
1
L
eff
? V
0
ds
18
Good results are produced, as shown in Fig. 7(a). A
new subthreshold current model [27] is introduced,
I
ds

m
o
C
ox
W
eff
L
eff
?
k
b
T
q
_ _
?
e
V
gs
V
t
V
off
n
? 1 e
q
k
b
T
? V
ds
_ _
19
and an extensive effort is made to parametrically
dene a well-conditioned transition region around the
weak-strong inversion transition. The results are
good, as shown in Fig. 7(b). In addition, BSIM2
adds an output conductance model, making it suitable
for analog circuit design; results are shown in Fig.
7(c). The BSIM negative conductance problem Fig.
4(c) is eliminated in BSIM2 Fig. 7(d), and the weak-
strong inversion transition is smooth Fig. 7(e).
In total, the major feature of BSIM2 is its
suitability for analog circuit design. The drain current
model is more accurate for short channels than is
BSIM, and it shows better convergence behavior. The
main problem with BSIM2 is its complexity; the
model contains 40 ``base'' parameters, and if the
geometry (length and width) parameters are counted,
the total number of parameters is 120. In addition,
with all this complexity, parameter extraction is very
demanding. BSIM2 also requires binning, and like
many of its predecessors the model is not designed to
accommodate this procedure.
Perspectives on Analytical Modeling of Small Geometry MOSFETs 239
Fig. (a)
(b)
(c)
(d)
(e)
Fig. 6. HSPICE Level 28 results for a W=L 20 mm=0:7 mm device: (a) saturation characteristics; the accuracy in the linear-saturation
transition region is improved over the BSIM results Fig. 4(a); (b) output conductance results; (c) subthreshold region; (d) detail in the
weak-strong inversion transition region, V
ds
0:1 V; note that the transition region is smooth, while in the BSIM result Fig. 4(d), there is a
``jump'' in the characteristic near V
gs
0:9 V; (e) result with a gate bias of V
gs
1:0 V; note that in contrast to the BSIM result Fig. 4(c),
there is no negative output conductance for high drain biases.
240 D. Foty
(a)
(c)
(b)
(d)
(e)
Fig. 7. BSIM2 results for a W=L 20 mm=0:7 mm device: (a) saturation characteristics; the accuracy in the linear-saturation transition
region is improved over the BSIM results Fig. 4(a); (b) subthreshold region; (c) output conductance results; (d) result with a gate bias of
V
gs
1:0 V; note that in contrast to the BSIM result Fig. 4(c), there is no negative output conductance for high drain biases; (e) detail in
the weak-strong inversion transition region, V
ds
0:1 V; note that the transition region is smooth, while in the BSIM result Fig. 4(d), there
is a ``jump'' in the characteristic near V
gs
0:9 V.
Perspectives on Analytical Modeling of Small Geometry MOSFETs 241
BSIM2 was most often used as an alternative to
HSPICE Level 28 for analog circuit design. As noted
above, this occurs due to personal user preferences in
SPICE simulators, when interfaces between the
circuit simulator and other simulation packages are
required, or when other simulation packages require
that the MOSFET model equations be available to
them.
3.2.5. Some Comments on the Second Generation
Models. The second generation models set the tone
for modern MOS modeling, in which circuit simula-
tion usage takes precedence over a physical
description of the MOSFET. Several of the out-
standing problems, involving negative conductances
and rst derivative discontinuities, were largely
solved. These models also foreshadowed third
generation developments by introducing special
mathematical conditioning of the various transition
regions.
3.3. The Third Generation Models
3.3.1. Third Generation Model Structure. The third
generation of SPICE MOSFET models has begun to
emerge in recent years. The ``original intent'' of these
models was a return to simplicity. This represented an
attempt to re-introduce a physical basis into the
models while maintaining an appropriate level of
``mathematical tness'' and re-establishing a more
concrete connection to the underlying fabrication
technology. Originally, the ``extrinsic'' structure
present in the second generation models was supposed
to disappear; however, simple realities have forced its
re-introduction. Overall, the most important dening
characteristic of the third generation models has been
the effort to condense the model equation set, so that
each device property (e.g., a terminal current or node
charge) is described by a single equation which is
valid over all regions of device operation. This is
achieved by the use of specially-designed ``smoothing
functions'' to condition the transition regions.
3.3.2. BSIM3. BSIM3 [28,29] is the rst third
generation model which has appeared on the scene.
There is presently considerable confusion surrounding
this model, as many different versions and sub-
versions have appeared. The ``original intent'' of
BSIM3 was the simplicity described above, in which
there would be a physical basis to the model equations
and parameters, and the number of model parameters
would be relatively small. Unfortunately, the rst two
versions of BSIM3, while attempting to adhere to the
``original intent'', showed a number of signicant
shortcomings. These problems have been addressed in
the third version, but this is done using a large
infusion of empirical equations and parameters.
The ``core'' of BSIM3 builds upon its second
generation predecessors; the bulk charge description
developed in BSIM and BSIM2 is used. However, the
differences between the drawn and effective channel
dimensions are functions of channel length and width;
this is a very unusual empirical addition to the model.
The threshold voltage model is greatly modied, and
includes more detailed descriptions of non-uniform
vertical and lateral doping, along with a rather
complicated accounting for short and narrow channel
effects. A new mobility model, based on the
``effective eld'' concept [30] is employed.
A new and simplied description of the carrier
saturation velocity is used; however, this leads to a
more complex expression for the saturation voltage.
The drain current model is very complicated, but
includes a number of smoothing functions and
auxiliary functions which allow it to be condensed
to a single equation for all regions of device operation.
The output conductance model is very detailed;
interestingly, it re-introduces the ``l-model'' which
appeared in Level 1 and Level 2, but in a highly
modied form.
As developed, BSIM3 is intended to be a
``global'' model; that is, it is assumed in the model
structure that a single set of parameters will provide
good results over the entire geometry range. This is a
lofty goal which, to date, no model has ever really
achieved. Personal experience indicates that BSIM3
cannot generally be made rigorously accurate over a
large geometry range with a single set of model
parameters. Practical model building must cope with
this situation, which has implications not only for DC
model accuracy, but also for model-hardware
correlation.
In BSIM3, the physical basis of the channel
dimension model is often obscure. In MOS modeling,
it is important to employ physical values for the
offsets between the effective channel dimensions (due
to process biases and underdiffusion) which should
agree with the values used in the design guidelines.
Often, BSIM3 is unable to achieve good results when
242 D. Foty
this appropriate approach is used. The ``solution'' to
this problem is to either extract these parameters from
electrical data (in which case these values will not
agree with the design guidelines), or to invoke some
or all of the ``extra'' channel dimension parameters
(in which case the channel dimensions lose physical
meaning).
While these modications may seem unimportant
compared to the goal of achieving good tting results,
the implications are quite serious. In statistical
simulations of process variations, the channel dimen-
sions are usually treated as physical, well-dened, and
in agreement with the design guideline values for a
particular fabrication technology. In this form, they
are important variables for statistical simulations. If
the channel dimensions become non-physical and/or
empirical, the situation for statistical simulations and
the description of process variations becomes unclear.
In addition, discarding the physical basis of the
channel dimension parameters causes problems with
model commonality. At this time, it is typical for a
single fabrication technology to be described by
several different types of MOS models, to meet the
differing needs of various design users. The important
``process'' parameters, which are used in statistical
simulations, should correlate with the design guide-
lines for all model types; the basic statistical
simulation results should not vary across the different
model types. If one type of model changes this
situation, the basic expectations of model behavior are
open to confusion. Finally, in very short devices, there
is always risk that a non-physical channel length will
lead to a negative effective channel length in the
``fast'' corner of the process.
If a ``global'' model is constructed, one of two
things must happen. Either rigorous accuracy will be
achieved over the entire geometry range, or the model
will ``allocate'' various portions of error over that
range. This is best described by examining sample
results comparing a ``global'' model (constructed
over a geometry range) with a ``point'' model
(constructed for one geometry). As shown in Fig.
8(a) and 8(b), the ``point'' model gives better results
than the ``global'' model. In this particular case, Fig.
8(a) clearly shows that there is difculty in providing
a description of the saturation voltage V
dsat
over a
range of channel lengths. This situation is more
clearly seen in the output conductance results of Fig.
8(c) and 8(d); once again, the ``point'' model provides
better results, and the problem with providing a
``global'' description of the saturation voltage is once
again evident.
For these reasons, the ``L-W-P'' approach to
binning is now available for use in BSIM3; this
allows the point model results of Fig. 8(b) to be
realized across the entire geometry range, within the
usual constraints of data availability. This is reection
of the simple reality that a universal and suitable
description of MOSFET behavior over geometry has
yet to be found. However, BSIM3 contains many
intrinsic expressions which are strong functions of
channel length; these expressions conict with the
``L-W-P'' terms. As a frequent consequence, the use
of ``L-W-P'' binning guarantees model continuity at
the bin boundaries; however, model behavior near the
bin boundaries is often bizarre.
(As an aside, it should also be noted that BSIM3
has some structural difculties which cause problems
when trying to model buried-channel MOSFETs.)
In summary, it should be noted that BSIM3 was
launched with an ``original intent'' of providing a
simplied, physically-based MOS model with a
small number of parameters. However, over time,
BSIM3 has evolved into a very complex, very
empirical model with a very large number of
empirical parameters. In such an empirical environ-
ment, parameter extraction is often a tedious and
complicated exercise. The use of smoothing func-
tions does provide results, particularly for the
conductances, which are much smoother than those
of earlier models; this is perhaps the most important
structural improvement that is provided by BSIM3
and the other third generation models. However, as
discussed above, the attempt to impose a ``global''
capability on BSIM3 creates a number of problems.
Of particular note, the weakening of the physical
basis of the channel dimension parameters and the
possible need to invoke the empirical ``extra''
channel dimension parameters is a cause for concern.
Binning solves some of these problems, but
introduces others. However, one of the main
attributes of BSIM3 is that it is universally available
in various simulators. BSIM3 is a very useful MOS
model if model parameters are extracted with great
care, and if circuit simulations, particularly for
analog designs, are approached with considerable
caution.
3.3.3. MOS Model 9. MOS Model 9 [31] is a more
recent third generation model. It was developed at
Perspectives on Analytical Modeling of Small Geometry MOSFETs 243
Philips Laboratories in the Netherlands, and is being
made widely and publicly available for inclusion in
popular SPICE circuit simulators. It is important to
note that MOS Model 9 is the rst analytical
MOSFET model to nd its way into the ``main-
stream'' of SPICE simulation which does not have its
origins at the University of California/Berkeley. The
structure of the model clearly shows its industrial
heritage and experience.
MOS Model 9 employs well-behaved hyper-
bolic expressions as ``smoothing functions.'' Thus,
as in BSIM3, each device property (e.g. the drain
current) is described by a single equation for all
regions of device operation. Unlike BSIM3, MOS
Model 9 uses a partial implementation of the
second generation ``extrinsic'' model structure;
this feature is available for some parameters but
not for others. Where this structure is employed,
it also allows the use of the ``reference''
geometries (as in HSPICE Level 28) to accom-
modate model ``binning''. However, some
geometries can be taken to powers, which is
very different from the approach taken in the
second generation models.
One pleasant feature of MOS Model 9 is that the
model equations are very ``clean'' and straightfor-
ward. However, a number of concerns have arisen
surrounding the ability of MOS Model 9 to t deep
submicron devices. However, for good or bad, MOS
Model 9 is not nding much use at this time, so a
detailed examination of its behavior will not be
undertaken here.
(a) (b)
(c)
(d)
Fig. 8. BSIM3 results for a W=L 20 mm=0:7 mm device; (a) saturation characteristics, ``global'' model; (b) saturation characteristics,
``point'' model; (c) output conductance results, ``global'' model; (d) output conductance results, ``point'' model.
244 D. Foty
3.3.4. The EKV Model. A very interesting recent
development is the Enz-Krummenacher-Vittoz
(EKV) model [32]. This model was developed for
low power analog circuit design; this eld of design is
very demanding, and puts the greatest pressure on
model structure and parameter extraction. Most
notably, the EKV model introduces a new approach
to MOSFET modeling, probably the rst true ``re-
thinking'' of methods of analytical MOSFET mod-
eling (which to date have been based on the original
1964 description [6]). The substrate (rather than the
source) is treated as the voltage reference; this allows
a symmetric description of the device, as the
MOSFET is often used in that fashion in analog
circuits. In this manner, the same physical description
can be used for both the weak-strong inversion
transition and the linear-saturation transition.
Smoothing functions are used, and a single drain
current equation for all regions of device operation is
developed. This model is very ``clean'' and efcient,
and is a good candidate for future use.
One particularly signicant feature of the EKV
model, particularly for analog design, is that the
model is intentionally built with a ``hierarchal
structure''that is, the model can be reduced to a
subset of equations and parameters which are suitable
for use in hand calculations for creative synthesis,
which provided a clean path back to the full circuit
simulation. For this structure to work, two things must
be available. First, it must be possible to break the
core model equations down into a simplied subset
(for weak and strong inversion); the EKV model
allows this to be done, producing suitable analytical
expressions for the currents and conductances.
Second, it must be possible to take the ``core''
model parameters (e.g. threshold voltage, low-eld
mobility, etc.) out of the full parameter set and use
them in those simplied equations; with proper
parameter extraction, the EKV model also makes
this possible. This capability provides a closed-loop
connection between hand calculations and circuit
simulation, and is a major improvement over the
present situation.
In very empirical models, the ``core'' model
parameters have lost their full physical meaning,
and thus are not suitable for removal from the main
parameter set for use elsewhere. In addition, with no
other set of simple model equations available, these
parameters are usually used with the old Level 1
equation set. Combined, these two problem make the
use of a ``modern'' MOS model for creative analog
design synthesis a virtual impossibility; the ability of
the EKV model to solve this problem is one of its best
attributes.
4. Charge and the Active Device Capacitance
4.1. Charge Conservation
In particular types of circuits and/or under certain
operating conditions, charge conservation can be a
vexing problem. The term ``charge conservation'' is
merely a statement that charge neutrality in each
MOSFET should be preserved under all DC, AC, and
transient conditions; in every situation, all the
MOSFET node charges should sum to zero:
Q
GATE
Q
S
Q
D
Q
SUBSTRATE
0 20
If (20) is violated under any circumstances, then
charge conservation is not maintained by the model.
In certain digital simulations, this can lead to the
erroneous prediction of continually increasing charge
at one or more nodes. The problem is more subtle but
more serious in analog circuits, where proper
modeling of charge takes on increasing importance.
The problem of charge conservation is easily
solved. However, it is important to note that
difculties with charge conservation are generally
not due to shortcomings in the MOSFET models. The
key general requirement to ensure charge conserva-
tion is that the circuit simulation must be charge-
based rather than simply voltage-based; that is, both
the voltage and the charge must be used as state
variables at each circuit node. Problems with charge
conservation are caused by the numerical (and thus
approximate) integration of voltage values [33];
unavoidable numerical errors introduced by the
approximate methods of numerical integration can
manifest themselves as excess charge.
In detail, three requirements must be met if charge
conservation is to be guaranteed. First, the MOSFET
charge description must be derived with the charge
neutrality condition (20) as its basis; this condition is
usually met, and is rarely the cause of trouble. Second,
the MOSFET model must communicate node
charges (rather than node capacitances) to the circuit
simulator. The MOSFET model should produce
expressions for the node charges; expressions for the
Perspectives on Analytical Modeling of Small Geometry MOSFETs 245
corresponding capacitances can be derived, but these
only have use for quick calculations and should not be
implemented in the circuit simulator. Finally, as noted
above, the circuit simulator must use charge rather
than voltage as its state variable.
Some important comments on the nature of these
requirements should be made. It must be noted that
charge conservation is a problem at the circuit
simulation level (rather than at the MOSFET model
level). Also, charge conservation is really an imple-
mentation problem, rather than a modeling problem.
Finally, it must be clearly understood that charge
conservationis guaranteedbythe appropriate construc-
tion of the circuit simulator; however, even if charge
conservation is maintained, it provides no guarantee
that an accurate description of the charge behavior of
the device has been created. Charge conservation
ensures that the simulation does not violate the laws of
physics, but does not address the quality of the
underlying description of the node charges.
4.2. The Zero Bias Capacitance
With no biases applied to the MOSFET terminals,
there will still be a capacitance between the gate and
the source/drain diffusions. In very large MOSFETs,
this capacitance is relatively small and can be
neglected; under strong inversion, the active gate
capacitance is easily computed from
C
GATE
W
eff
? L
eff
? C
ox
21
In smaller MOSFETs, however, the zero bias gate-
diffusion capacitance must be included. In SPICE,
this is done by including the model parameters
CGDO and CGSO, which represent, respectively,
the zero bias gate-drain and gate-source capacitance.
At zero bias, the gate capacitance is computed from
C
GATE;zb
W
eff
? CGDO W
eff
? CGSO
22
Under strong inversion, this zero bias contribution is
merely added to the active gate bias, so (21) becomes
C
GATE
W
eff
? L
eff
? C
ox
W
eff
? CGDO
W
eff
? CGSO 23
A more detailed analysis indicates that the zero bias
gate-diffusion capacitance should be divided into
three components, as shown in Fig. 9(a). In practice,
the ``direct overlap'' capacitance C
1
and the ``outer
fringe'' capacitance C
2
show little bias dependence;
however, the ``inner fringe'' capacitance C
3
is
actually screened out when an inversion layer is
present. Thus, the approach of simply including
constant terms to describe the additional capacitance
contribution, as was done in (22) and (23) is not
accurate. In fact, in modern MOSFETs, if measured
zero bias capacitance values are used for CGDO and
CGSO, the resulting model will overpredict the total
gate capacitance at high gate biases, as shown in Fig.
9(b). Note carefully that this is a structural short-
Fig. 9.
b
The gate-diffusion capacitance; (a) the gated MOSFET
diffusion structure, showing the direct gate-diffusion capacitance
C
1
, the ``outer fringe'' capacitance C
2
, and the ``inner
fringe'' capacitance C
3
; (b) the result of adjusting the zero bias
capacitance parameters CGDO and CGSO in a 10/0.25 device to
compensate for the inability to account for the screening out of
the ``inner fringe'' capacitance C
3
at high gate biases. If this
approach is adopted, CGDO and CGSO will not agree with
measurements of the zero bias gate-diffusion capacitance.
(a)
246 D. Foty
coming of present gate capacitance models that
remains to be properly addressed.
A typical semi-empirical ``x'' for this problem is
also shown in Fig. 9(b). The values of the model
parameters CGDOand CGSOare adjusted to provide
agreement with the high gate bias regions since this
represents the largest fraction of the operating range;
this is done at the price of forfeiting accuracy in the
low gate bias (subthreshold) region. An approach of
this sort is often used at the circuit level, where
CGDO and CGSO are adjusted to match ring
oscillator results. Note, though, that in low voltage
circuits (where the power supply voltage has
decreased but the threshold voltage has not [1]), the
subthreshold region, where this approach forfeits
accuracy, represents a larger relative fraction of the
operating range; in such a situation, these short-
comings of the gate-diffusion capacitance model
become more dangerous.
5. Accounting for Systematic Process Variations
5.1. Basic Considerations
In examining the mathematical structure of the
various analytical MOSFET models that are available
in SPICE, it becomes clear that these models were
constructed to describe individual device character-
istics. With this base, the amount of empirical
character a model possesses is unimportant; any
mathematical formulation which is able to describe
the device behavior will be adequate. In an ideal
world, every MOSFET and every die on every wafer
would be absolutely identical; this type of description
would work very well.
Unfortunately, in practice this is not the case. Even
if a fabrication process is stable and well behaved,
there will be random variations which will produce a
statistical distribution of results. In an industrial
circuit design environment, an accounting for these
effects is very important. For example, a description
of the ``slow'' extreme of the process is required to
ensure that designed circuits will function, while a
description of the ``fast'' extreme of the process is
used to avoid timing problems. In all cases, the
description of statistical process variations should be
sufcient to ensure proper circuit operation, while not
going to the point of ``overdescribing'' the situation,
which will cause a design to cope with statistical
variations which will not in fact occur (this
unnecessarily limits the aggressiveness of the design).
If MOSFET model descriptions were completely
physical, the statistical requirements would very
easily be met, and this topic would now be of little
concern. All the model parameters would be collected
and compiled during routine fabrication characteriza-
tion, and subject to statistical analysis. This
information would be used in the MOSFET model,
and the task would be complete. However, as noted
above, the MOSFET models were developed to
describe ``single'' device characteristics rather than
statistical behavior. Instead, the statistical aspects are
imposed on the basic model structure in a rather ad
hoc fashion. The reader should note that this issue is
still largely unaddressed in MOSFET model devel-
opment.
Since the MOSFET model structures are empirical
and decoupled from routine fabrication characteriza-
tion, the obvious solution would be to carry out a
massive (``statistically signicant'') number of
parameter extraction runs and compile a statistical
database of parameters. However, this option is
impractical, as human intervention is required for
proper parameter extraction, and modern MOS
models require considerable CPU time for extraction
of a model parameter set. A more practical method
would be to nd some way to make use of the routine
fabrication characterization data that is available.
The usual approach is to deem certain ``fabrication''
parameters as being responsible for process varia-
tions and use them to describe the situation. A
commonly-used set, each member of which is usually
available in statistical form from routine fabrication
characterization, includes the oxide thickness t
ox
,
the channel length and width, the variation of the
threshold voltage from its mean DV
t
, and the
diffusion sheet resistance. It is a simple matter to
compile typical, +3s, etc. values of these para-
meters, and construct the process ``skew'' le which
usually accompanies a basic model parameter set. An
additional advantage of this method is that a basic set
of ``fabrication'' parameters appears in all the
different types of models; thus, if properly con-
structed, a ``skew'' parameter set should be
``portable'' across all the different types of
MOSFET models which are available for a single
fabrication technology.
In its simplest form, values are compiled indepen-
dently for nFETs and pFETs; the +3s limits dene
Perspectives on Analytical Modeling of Small Geometry MOSFETs 247
the ``fast'' and ``slow'' corners of the process. In
practice, however, this approach usually overpredicts
the +3s extremes of actual circuit performance; if
used ``as-is,'' this causes circuit designs to be less
aggressive than they should be. A typical ``engi-
neering'' solution which is commonly employed is to
measure the +3s circuit results and nd a number of
``articial'' process sigmas (e.g. +2.5s) which
matches the +3s circuit results; this ``articial''
process sigma value is then used for statistical
simulations. Experience with this method has shown
that the specic number of ``process'' sigmas tends to
vary for different types of circuits; a different
``articial'' process sigma value must be determined
for each circuit ``family,'' which by denition limits
the predictive capacity of this approach. In addition,
this method requires that circuits be available for the
determination of the ``articial'' process sigma
values. In many situations, this sort of circuit
information is not available. Often, this ``articial
sigma'' method is instead adjusted to produce the
+3s values of I
dd
.
5.2. Creating a ``Design Window''
Consider the potential mismatch between nFET and
pFET behavior; for this example, the drain current at
V
gs
V
ds
V
dd
will be employed to illustrate the
basic points. If the nFET and pFET behavior
correlated perfectly, each could be characterized
separately, and a simple straight line description
would be produced, as shown in Fig. 10(a). However,
this correlation will not be perfect; the description of
Fig. 10(a) does not provide adequate information to a
circuit designer employing this technology. If nFET
and pFET behavior was completely uncorrelated, one
type of FET could be very slow while the other is very
fast; this results in a modication to Fig. 10(a),
leading to the design ``window'' of Fig. 10(b). A
design ``window'' of this type is frequently used in
the industry; nFETs and pFETs are characterized
independently, and the diagram of Fig. 10(b) is
created. Obviously, this design ``window'' will
encompass all possible combinations of nFET and
pFET currents. However, this design ``window'' is
too large; it forces the designer to account for two
fast-slow corners which in practice will not be
populated.
In reality, some degree of correlation between
nFETs and pFETs does exist. A much improved
description of the situation may be found in Fig. 10(c).
Here, partial correlation is included. To create such a
design window, the nFETs and pFETs must be
characterized separately; then, the mismatch correla-
tion between them must be examined. This requires
additional measurements and analysis, but provides
the circuit designer with a much more realistic
description of the statistical device behavior. A
practical drawback to this approach is that there are
now six (rather than four) process ``corners'' to
simulate; however, the unrealistic extreme corners are
eliminated. In addition, a good ``window'' description
can be put to use; for example, if a ``window'' like
that in Fig. 10(c) is well described, a design can be
pushed toward the ``fast'' corner, with the intent of
giving up some yield in order to produce a larger
number of faster parts.
5.3. Principal Component Analysis
A possible solution to the rather ad hoc nature of
statistical MOS modeling is Principal Component
Analysis (PCA) [34,35]. Principal Component
Analysis provides a mathematically rigorous descrip-
tion of the statistical variations of the model
parameters and their correlations; it is able to produce
an accurate description of the statistical behavior of
all the parameters in the model, both individually and
as a collective group. While this approach is very
accurate, it introduces a tremendous addition to the
amount of work that must be done; in an industrial
environment, this additional load can be prohibitively
``expensive'' of both time and energy. A very large
amount of data must be collected, and a very large
number of parameter extraction ``runs'' must be
performed to create a statistical data base for all the
model parameters.
While it provides a rigorous description of process
variations, PCA causes an enormous expansion of the
model building workload; the implementation of PCA
in industrial circuit design is probably unworkable in
the present environment. This method only becomes
tractable if efforts in model simplication become a
reality.
248 D. Foty
5.4. Matching
Another topic of strong interest, especially to analog
designers, is the mismatch between supposedly
identical transistors which are placed near each
other. Several years of study have demonstrated that
the popular ``Pelgrom model'' [36] of mismatch, in
which parameter variation is described by
DZ AZ?
1
L
eff
? W
eff
_ _1
2
24
provides a good description. However, this simple
description has rarely been implemented in the
structure of MOS models; only the EKV model
explicitly implements this approach with the appro-
priate AZ parameters.
5.5. Conclusions
The issue of modeling statistical process variations is
very important in industrial circuit design, but has not
received the attention it deserves; this is not a well-
(a)
(b)
(c)
Fig. 10. Combined nFET vs. pFET current for some CMOS technology, for xed values of drawn channel length and width at some given
temperature: (a) perfect correlationthe model follows a diagonal line; (b) no correlationthe model describes a rectangle encompassing
all possible nFET and pFET current values; (c) the construction of a compromise method, based on the rectangle method of (b), but which
eliminates the wasteful ``fast-slow'' corners; note that this method leads to six process corners.
Perspectives on Analytical Modeling of Small Geometry MOSFETs 249
explored topic. While a ``physically based'' model is
not required to describe individual transistor char-
acteristics, the development of such a model would
allow for a much improved description of the effect of
process variations on device and circuit behavior. It is
interesting to note that an improved description of
statistical process variations could provide a large
source of competitive advantage without changing the
underlying process technology, as it would allow
designs to assume the proper level of aggressiveness.
6. The Present and Future Modeling Situation
At this time, no particular model has been able to
demonstrate clear superiority for all possible design
alternatives. Thus, while the development of such a
``golden'' MOS model is a laudable objective, this
has yet to occur. While the coexistence of several
MOS models may seem messy, the use of a single
``one-size-ts-all'' model cannot be imposed on the
industry. The circuit design ``marketplace'' will (and
should) make these kinds of choices.
6.1. Future Model Forms
While predicting the future is always risky, there are
many obvious trends in the development of analytical
MOSFET models which provide guidance. It must
always be kept in mind that the basic goal of these
efforts is to provide MOSFET models for circuit
design and simulation. Philosophically, it would be
advantageous if the models could also be used for
process characterization/development; however, that
issue is clearly secondary, and must be sacriced if
attempts to do ``double duty'' degrade the description
which the circuit designer receives.
It should be clearly noted that as CMOS fabrication
technology becomes more generic (and cost-driven),
the driving force behind MOS modeling is not the
description of new process technology ``innovations''
and problems, but rather is the more innovative,
clever, and detailed use of MOS properties/behavior
in circuit design. Viewed in this light, it is clear that
analytical MOS modeling serves a circuit design
function (rather than a ``process characterization''
function). The very weak physical nature of present
MOS models is an important problem; however, it
should be carefully noted that the objective of such an
effort is to create a workable, accurate, and predictive
description of statistical process variations for use in
circuit design.
There are even serious discussions of developing a
``fully integrated'' simulation environment, which
would allow designs to be optimized by actually
``ne-tuning'' the process technology. While this is a
very worthwhile topic of study, several practical
problems are encountered. Despite numerous suc-
cesses, a completely accurate and robust simulation of
every facet of CMOS process technology has yet to be
reached, due to the extreme complexity of the
underlying process physics
1
. In addition, as process
development engineers are well aware, even suppo-
sedly ``well conditioned'' CMOS processes behave
non-linearly with respect to even ``minor'' changes; a
``minor change'' often causes a cascade of side
effects, which can be devilish to remedy. A nal
problem is that if numerous designs ``ne-tune'' a
process several times, process and manufacturing
engineers will nd themselves in the unhappy position
of supervising an unruly collection of ``sub-pro-
cesses,'' each of which requires considerable time and
attention.
Finally, it should be noted that most analytical
MOS models are still based on the ``original'' 1964
analytical MOSFET description, with an increasing
number of ``corrections'' added as time has passed.
Signicantly, new ideas are beginning to enter
consideration. For example, it is now being recog-
nized that various ``transition points'' (such as the
saturation voltage V
dsat
) are causing many of the
mathematical difculties which are being encoun-
tered. These ``transition points'' were easy to dene
in ``old'' MOS technology; however, their description
in modern MOS devices has become quite murky and
open to signicant interpretation. Attempting to
impose what may be archaic notions of MOS behavior
on ``new'' MOS technology is proving to be the
source of many of the present problems. Newer
models are putting considerable effort into the
elimination of these transitions, using various math-
ematical ``conditioning'' functions. A common
solution now being introduced is to provide a single
equation for a particular device property which is
valid for all regions of device operation. In practice,
this is the simplest way to guarantee that an equation
and its derivative will always be continuous.
However, even this approach is somewhat clumsy.
A more physically-correct description of the
250 D. Foty
MOSFET would use a surface-potential-based
description [37]; this is an important topic for future
study.
In the longer view, the use of a ``base'' model with
an growing collection of ``corrections'' is increasing
both the complexity and the empirical content of
models. It could be suggested that the time is ripe for
a re-thinking of analytical MOSFET models, with a
fresh start on the description of contemporary
devices.
7. Final Comments
A recent paper [38] provided an excellent overview of
the present situation in analytical MOSFET modeling
from the point of view of an analog circuit designer.
As noted in that paper, designers are often forced to
use models which provide relatively poor descriptions
of the process technology with which the nal circuits
will eventually be fabricated.
However, this author is less sanguine about the
level of awareness of these deciencies among circuit
designers. Unfortunately, from experience, many
circuit designers are ``uneducated model consu-
mers''; models are not examined in detail before
and during their use, and questions are only asked
when trouble develops. The most common approach
seems to be to use models with blind faith
2
, and not
delve into the ugly details of model behavior until the
circuits are fabricated and perform nowhere near the
simulated predictions.
Circuit designs can be greatly improved by
changing this situation. The circuit designer should
become an ``educated model consumer'', and care-
fully examine MOSFET models before their use. A
designer should ask (and be able to answer) questions
such as:
*
Is this type of model appropriate for the intended
circuit design usage?
* For this type of model, is the result the best that
parameter extraction can make possible, or can it
be improved?
*
If the model is ``binned'', has binning been
implemented properly?
This kind of discussion should precede the beginning
of circuit design. This is important, as the presently
available ``infrastructure'', which circuit designers by
denition must employ, can be made to serve most
present circuit design needs.
It is also important that new model development
activities focus very clearly on future circuit design
requirements. In this light, a change in MOSFET
modeling activities may be required. For historical
reasons, MOSFET modeling has traditionally been
closely associated with process development efforts.
This reects the use of models which were ``physi-
cally-based'', at least in name. However, to serve
circuit design needs, models have become more
empirical, and are now very much decoupled from
process development and characterization activities.
It is now time to undertake a change, in which
MOSFET modeling is thought of as a circuit design
activity. Closer interactions between model building
and circuit design can allow for MOSFET descrip-
tions which are more carefully tailored to specic
circuit design needs.
Acknowledgments
The author wishes to thank many individuals for
continuing discussions of MOSFET modeling issues
for circuit simulation, including Narain Arora, Peter
Bendix, Matthias Bucher, Christian Enz, Gennady
Gildenblat, Mohammed Ismail, Richard Kaul, Ann
Spratt, Yannis Tsividis, Eric Vittoz, and Jared Zerbe.
The data used in the parameter extraction examples in
this paper were provided by Paul Findley, Morgan
Smith, Ali Rezvani, and their colleagues at VLSI
Technology; this contribution is gratefully acknowl-
edged.
Notes
1. At a conference several years ago, the author overhead a
comment that ``Process modeling simulates yesterday's tech-
nology, tomorrow.'' While the situation may be better than this
description would indicate, it illustrates the empirical nature of
process simulation, which limits its predictive capacity.
2. As an aside, the author notes that ``Blind Faith'' is the name of a
popular northern Vermont ice climbing route; perhaps signi-
cantly, it is located near another route known as ``The Grand
Illusion.''
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