Towards A Versatile Wireless Platform For Low-Power Applications

International Journal of Digital Information and Wireless Communications (IJDIWC) 1(2): 401-414 The Society of Digital Information and
Wireless Communications, 2011(ISSN 2225-658X)
Towards a Versatile Wireless Platform for Low-power Applications Sndor Szilvsi and Benjmin Babjk and kos Ldeczi and Pter Vlgyesi Institute for Software Integrated Systems, Vanderbilt University 1025 16th Ave South Suite 102, Nashville, TN 37212, USA peter.volgyesi@vanderbilt.edu Over the past decade the prevailing trend in wireless sensor network (WSN) node design has been to combine common off-the-shelf (COTS) microcontrollers with CMOS short range radio transceivers. This convenient and lowrisk approach is supported by several semiconductor companies (e.g., Texas Instruments, Atmel, Microchip, Cypress Semiconductor), many of whom provide these components as chipsets with readily available reference designs. The abundance of these low-cost hardware options enabled the WSN research community to design, prototype and build a vast array of successful "mote" class sensor nodes, such as the [11], XSM [6] and Telos [22] devices, fostering academic research in lowpower sensing and wireless communication. While this almost "ready to eat" design pattern lowered the bar for sensor node design, it also made a huge impact on the variety of research topics within the community. Two notable areas where the implicit constraints inherent in these hardware platforms prevent progress are: low-power signal processing and innovative RF/wireless technologies for communication and other middleware services. Albeit our research team was deeply involved in the development of TinyOS [10][16] - a characteristic WSN operating system targeting COTS hardware platforms, we repeatedly 401
ABSTRACT
Traditional wireless sensor network architectures are based on low-power microcontrollers and highly integrated short range radio transceiver chips operating in one of the few ISM bands. This combination provides a convenient and proven approach to design and build inexpensive sensor nodes rapidly. However, the black box nature of these radio chips severely limit experimentation and research with novel and innovative technologies in the wireless infrastructure. Our team previously proposed a revolutionary architecture for wireless nodes based on Flash FPGA devices. This paper shows the initial results of our work through the implementation and evaluation of a simple baseband FSK modem in the SmartFusion FPGA fabric. We also demonstrate how we could leverage existing software radio projects to use the baseband modem in a wide range of radio frequency bands. Finally, the paper describes our approach and implementation of power management and instrumentation, a key building block in our modularized low-power software radio platform.
KEYWORDS
Wireless Communication, Low-power Design, Software-defined Radio, FPGA
1 INTRODUCTION
International Journal of Digital Information and Wireless Communications (IJDIWC) 1(2): 401-414 The Society of Digital Information and Wireless Communications, 2011(ISSN 2225-658X)
encountered these shortcomings of the MCU + RFIC recipe. Using the TinyOS ecosystem we developed and successfully demonstrated several novel applications and key technology components, such as a shooter localization system [26], structural health monitoring application [15], highly accurate time synchronization and time stamping services [17][12] and a localization method with radio interferometric ranging [18]. In these efforts we either had to extend the traditional hardware architecture with custom designed and built components (e.g., FPGA-based cards for parallel signal processing of acoustic emissions, bullet shock waves and muzzle blasts) or we realized that our ideas yielded much higher accuracy and overall performance only if we would have more access to and control over some parts of the RF signal chain (e.g.: radio interferometry, time stamping). We firmly believe that by breaking up the traditional packetoriented boundary between the radio and the processor a deluge of new research topics will emerge within the WSN scientific community. Innovative media access protocols and ranging technologies, like [13] could be pursued and explored in much more detail. Developing a radically new wireless platform, which can be picked up and worked with by others is a serious undertaking. Many design decisions have to be made with little or no prior knowledge of usability, extensibility, robustness of the various alternatives. The primary goal of our platform is to support experimentation and education in wireless sensor network research. For all these reasons we are following a modular approach in our new WSN node
architecture by separating key components with well-defined hardware and software interfaces: (1) power management and instrumentation, (2) digital processing using a Flash FPGA and analog-digital conversion chips, (3) analog radio frontends supporting various RF bands with integrated mixers, filters, amplifiers. Such a clear separation of concepts lower the overall risk in hardware development, enables the overlapping of design and implementation tasks and keeps the platform open for further ideas. 2 RELATED WORK Our approach and motivation is not entirely new. The mainstream wireless research and development community has long embraced software-defined radio (SDR) architectures, such as the Universal Software Radio Peripheral [8] and GNURadio [9]. This and similar platforms provide the necessary datapaths and computational power for acquiring, processing and emitting sophisticated analog signals tens of megahertz wide selected in an even much wider radio frequency band. Signal processing tasks are implemented on a PC class hardware running desktop operating systems and using standard programming languages and open software frameworks. The performance of the state of the art SDR platforms is sufficient enough to implement WiFi access points, GSM base stations [21] and GPS receivers [5]. Traditional SDR architectures enabled us to experiment with and evaluate new ideas in our WSN research. In these scenarios the SDR platforms provided instrumentation and served as quick 402
prototyping and proof-of-concept vehicles. However, these platforms are not suited well for implementing and deploying WSN applications due to the dependency on PC hardware, large FPGA devices and magnitudes of higher power requirements than it is available on a typical sensor node. Field Programmable Gate Array (FPGA) devices are key elements of SDR platforms: these provide the low-level plumbing infrastructure and implement preliminary signal processing tasks (digital up and down conversion, filtering, etc.). The Agile Radio project at Kansas (KUAR) [20] uses an embedded PC based platform augmented with a Xilinx Virtex-II Pro FPGA. Rice University's Wireless Open-Access Research Platform (WARP) [2] also uses the same FPGA as its baseband processor. Berkeley's Waldo localization platform uses a Xilinx Spartan 3 XC3S1000 FPGA [14]. The WINC2R SDR hardware [19] from the WINLAB group at Rutgers has an embedded CPU and two high-end Xilinx FPGAs, one for baseband processing and another for the network layer. Unfortunately, mainstream CMOS / SRAM-based FPGA architectures (Xilinx Virtex and Spartan and the Altera Stratix and Cyclone families) are not suited well for battery-based operation, mostly due to their significant static power requirements, which cannot be mitigated easily with duty cycling techniques [27]. Recent developments in Flash-based FPGA architectures [1] and a revolutionary new mixed signal device family (Actel SmartFusion [23]) removed most of such barriers. Integrated and configurable analog
components provide ideal support for interfacing with various sensor types, the FPGA fabric can be configured for sensor and baseband radio signal processing tasks and the integrated ARM Cortex-M3 processor executes higherlevel algorithms and system integration routines. Based on our prior knowledge of the potential benefits and drawbacks of traditional FPGAs in WSN research we quickly embraced the new architecture for building the first compact and low-power software defined radio platform targeting wireless sensor networks [7]. Designing and building such a new platform is a complex endeavor with many unknown challenges and risks. Therefore, we embarked on a more incremental approach, where we could leverage existing and proven hardware and software components. On the analog RF side we already had several URSP radio front-ends in the 433 MHz and 2.4 GHz ISM bands. The new SmartFusion device family is also supported by a readily available low-cost evaluation kit and a more sophisticated development kit. Thus, with the help of a custom designed ADC/DAC and signal conditioning interface circuit board we were able to build the first prototype of the new architecture and to start experiments with the capabilities of the SmartFusion device in RF baseband signal processing. This paper describes the initial results of this work. 3 IMPLEMENTATION We selected a low-power Frequency Shift Keying (FSK) modulator / demodulator (modem) as the initial evaluation tool on the Flash FPGA 403
platform. In the simplest variation of this modulation scheme (binary FSK) the digital information is transmitted using a pair of discrete frequencies around the carrier (center) frequency. Our design was heavily influenced by a similar project for mixed signal microcontrollers [24]. The primary design requirement for the FSK modem was to minimize power consumption and resource utilization of the overall system. A well known technique, often utilized in low-power microcontroller based systems, is precise clock management via clock scaling and duty cycling. Another effective, yet completely different, approach for power reduction in FPGAs is minimizing the amount of FPGA fabric resources used. This can be achieved by creating designs that are aware of the internal structure of the FPGA. System on Programmable Chips (SoPC) offer further possibilities by taking advantage of their non-general purpose circuitry. These integrated hardcore modules, such as processors and digital communication interfaces, consume less power compared than the FPGA fabric. Furthermore, the programmable analog and interfaces eliminate the need for external DACs and ADCs, which also saves power.
of the baseband FSK design is shown in Figure 1. The transmitter and receiver data paths use only the FPGA fabric and the programmable analog parts of the SmartFusion SoPC, whereas the testbed is entirely implemented in software in the Microcontroller Subsystem, that is built around the embedded Cortex-M3 microprocessor. The baseband FSK data paths are connected to the testbed through the AMBA bus matrix. 3.1 Testbed The testbed has three main tasks to perform, such as test-vector generation, result-vector comparison and error logging. In the case of the baseband FSK testbed test-vector generation translates to preparing packets with a well defined payload and feeding them into the transmitter data path, see the upper data path in Figure 1. Result-vector comparison works the other way, the payload of the received packet is retrieved from the receiver data path, as shown on the lower data path in Figure 1, and matched against the original payload. The number of mismatching bits in the payload are then stored after each transaction. Since none of these tasks are time critical and test-vector generation and matching call for complex sequential logic, the entire testbed is realized in software in the Cortex-M3 microprocessor. The processor sets the transmit and receive parameters, sets the transmit payload and gets the received payload via an APB interface defined on the AMBA bus matrix. As the corresponding peripheral registers are mapped into the Cortex-M3 memory space, these transactions are simple register read and write operations. Upon
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Figure 1. Block diagram of the baseband FSK SmartFusion design.
Combining the above mentioned techniques, the high level block diagram
reception of a packet, a bit error rate (BER) counter is incremented according to the mismatches in the transmitted and received payload bits. This BER counter becomes of primary importance when executed in a loop for a large set of different test-vectors as it characterizes the overall BER for the actual transmit and receive parameters.
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3.2 Transmitter data path The transmitter data path resides in FPGA fabric and the Programmable analog blocks of the SmartFusion SoPC as shown in Figure 1. The purpose of the AMBA TX interface is twofold. First, it handles address decoding for registers accessible from the processor AMBA bus, such as the control, status, baud rate, delta phase low, delta phase high and data registers. Second, it implements a simple state machine that sets the delta phase input and the enable signal of the digitally controlled oscillator (DCO) according the bit values in the data register, using the timing information in the baud register. The DCO acts blindly, as it increments its phase accumulator by the delta phase amount set on its input when enabled and zeros the phase accumulator otherwise. The phase accumulator width is extended to 32 bits in order to reduce phase jitter, however, only the upper 16 bits are used to address the CORDIC module acting as a sine look-up-table. The CORDIC module is a word-serial implementation of the original algorithm presented by J. Volder [25]. The sine output of the CORDIC module is then fed into a - modulator that generates the high-speed, low-resolution input for the 1-bit DAC. This 1-bit DAC also contains a 3rd order low-pass filter with a cut-off frequency at 300 kHz. Note that this analog filter in conjunction with the 1-bit DAC and the - modulator form a low-hardware cost, high-speed, highresolution - type ADC. 3.3 Receiver data path The output of the baseband FSK transmitter is looped back to the Analog
comparator found in the Programmable analog block and serves as input for the receiver data path. The receiver data path is depicted in the bottom part of Figure 1. The digital 1-bit output of the Analog comparator is connected to the Correlator block. The Correlator block calculates the XOR combination of the input signal and its delayed samples. The precise selection of this delay is crucial to achieve robust discrimination of logical values, a programmable length delay line is utilized. The maximum length of this delay line ultimately limits the achievable maximum delay time of the samples. To extend the maximum delay length, a decimator with programmable down-sampling rate is also incorporated in the Correlator block. One should note, that decimating the signal, that is lowering the sampling frequency, creates a trade-off between the achievable maximum delay time and the time resolution. The comparator output is fed to a 2-stage CIC filter. The differential delay length of the filter is also programmable, thus allows for flexible adjustment of the cut-off frequency. The Bit decision logic utilizes a timer-based state machine and a thresholding logic to recover the bit values of the payload. These received data bits along with the ready signal are connected to the AMBA RX interface module, which in return, makes them accessible for the testbed through the AMBA bus via the data and status registers, respectively. The AMBA RX interface module implements the decoding logic for the rest of the registers holding parameters, such as the baud rate, decimation ratio, correlation delay and differential delay.
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4 SIMULATIONS Accurate high level simulation of the data paths was a critical step of the design process as it does not just provide a proof of concept, but also serves as a golden reference model when validating the FPGA fabric design. Figure 2 shows the Matlab simulated signals along the receiver data path. The signal in Figure 2(a) shows the baseband FSK signal (fcenter = 10 kHz, fseparation = 5 kHz) for a 2400 baud byte transmission of value '01001010'. This waveform is quantized by the Analog comparator resulting in a signal shown in Figure 2(b).
Figure 2. Simulated FSK TX and RX signals
The comparator ouput is correlated by its delayed samples, see Figure 2(c) to separate the two logic levels. The Correlator output stays low for when the high frequency signal is received and stays high (for most of the time) when the low frequency FSK signal is detected. Thus, averaging it with a lowpass filter results in a smooth waveform depicted in Figure 2(e).Clearly, a simple threshold logic can effectively separate the two logic levels at the decision points as shown by the rectangles in Figure 2(d). Note, that the decision points yield the byte '10110101', which is exactly the bit-inverse of the transmitted byte, thus can be compensated.
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5 RADIO FREQUENCY FRONTENDS Just like practically all modern softwareradio architectures our implementation follows the partitioning shown on Figure 3. On the software side the radio signals are represented in digital form enabling sophisticated and flexible digital signal processing approaches, on the far end the signals are in the analog domain, where conventional analog signal processing and signal conditioning takes place. And just as the mighty beaver connects opposing river banks with its dam, so does our domain conversion card (BeaverBoard) connect the two signal domains.
The challenge in designing a board that the would connect these off the shelf devices lied in the fact that the radio frontends were developed with a more sophisticated CODEC chip (AD9862) in mind. The AD9862 is a fairly complex mixed-signal front-end processor IC on the USRP, which is capable of 64 MSPS A/D conversion and 128 MSPS D/A conversion. Furthermore, the FPGA on the USRP is an Altera Cyclone EP1C12 device with plenty of free pins dedicated to frontend I/O control. The built-in ADCs and DACs in the Actel SmartFusion A2F200 device were not sufficient for interfacing with the baseband analog signals, and the evaluation board provided only a more limited number (25) of general purpose pins on its mixed signal connector interface. By carefully checking each I/O pins for the radio frontends and their current use we managed to restrict these to fit in the 25 pins of the mixed signal connector interface. The issue of A/D and D/A conversion proved to be more demanding. First, we had to decide on sampling rate. Since our intention is to build a lowpower platform and we need to to execute all signal processing tasks on the SmartFusion FPGA, we had to restrict ourselves to few MSPS and 12 bits sampling. These constraints meant that the sampling frequency could not be nearly as high as with the USRP. We ended up choosing the Analog Devices AD7357 4.2 MSPS ADC [4] with two channels, and 14 bits of resolution. For the other direction we used the Analog Devices AD5449 2.47 MSPS DAC [3],
Figure 3. Experimental low-power SDR architecture
Digital signal processing tasks are implemented on the SmartFusion evaluation board, while the analog domain is covered by various radio frontend daughter board cards available for the first generation Universal Software Radio Peripheral (USRP). These cards include the LFRX (DC-30 MHz receiver), LFTX (DC-30 MHz transmitter), and the RFX400 (400-500 MHz transceiver). While the first two boards are fairly simple providing only minimal filtering and gain, the RFX400 is much more sophisticated with built-in mixing and quadrature modulation / demodulation capabilities.
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which had two channels, and 12 bits of resolution. Due to limited board space proper analog filtering was not implemented, only simple, operational amplifier based first order low pass filters made it into the design. The operational amplifiers also provided a convenient way to set bias voltages.
produce a fraction of the required current at the DAC output. A single stage, common-source, PMOS amplifier at the DAC output proved to be unusable in our case because the current range had to go from 0 to 20mA. That range would have resulted in significant nonlinearity at the output of the single stage amplifier.
Figure 5. Beaverboard prototype

(a)
(b) Figure 4. LTspice simulation of the DAC and amplifiers
In designing the mixed signal interface circuit the primary challenge was to match the output current capabilities of the new DAC with the input current requirements of the RF frontend boards. The original high speed DACs on the USRP provide current outputs form 0 to 20mA. For the AD5449 DAC that is a R-2R ladder configuration with a typical R of 10k that would mean a supply voltage of 200V. Clearly we could only
The circuit shown in Figure 4(a) aims at solving this mismatch. The DAC output was converted from current to voltage with a simple operational amplifier stage, then the circuit as seen on the figure was used to generate the current output. The operational amplifier will always regulate its output so that the two op amp inputs have minimal voltage difference. Or in other words, the voltage measured at the inverting input of the amplifier will appear at the noninverting input as well. That on the other hand is the voltage that can be measured at the bottom of the resistor. The upper part is at supply voltage level, thus the voltage difference is known, thus the current flowing through the transistor is known. Note that current is not flowing into the non-inverting input only through the PMOS transistor. On might think that the transistor is not needed, because the output of the amplifier could be connected to the bottom of the resistor.
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However, in that case - although the voltage would be the same as in the previous case - current would flow into the amplifier through its output, meaning that the current flowing out of the resistor would not necessarily be the output current for the whole circuit. 6 POWER MANAGEMENT AND INSTRUMENTATION In Section 1 we briefly explained the rationale behind a modular architecture of our platform. Power management is one of those key areas where no silver bullet exists. To accommodate viable alternatives and unforeseeable future directions, power management and instrumentation was implemented on a standalone PCB with a simple yet flexible interface to the rest of the system. We hope that revolutionary energy harvesting and storage technologies can be easily adopted later by replacing this single circuit board only. The photo of our current power management board is shown in Figure 6.
fine grained power gating, enable accurate measurements on each power rails and provide simple data collection, communication and remote management services for the rest of the platform. Currently, we support USB and "wall adapter" input sources. The wall adapter connector serves as a general purpose input source with reverse polarity and overcurrent protection. On the USB power line the board abides the strict rules governing the maximum allowed current drain in various states of the bus. Both input sources can provide power for the entire system and/or charge a LiIon battery (following a strict charging profile and using thermal protection). The same battery - when charged - can be used as a sole energy source also. There are six (6) power rails supported by the power management system. An always-on 3.3V supply rail provides power for components of the management circuit. The rest of the power lines can be turned on/off by the board---typically by following remote commands, implementing duty cycling or if the remaining power seems critically low. A single linear 3.3V regulator (max. 1A) provides power for both digital and analog domains on other boards. The analog and digital rails are joined at a single point and separated by an RF bead. In a similar fashion the board synthesizes digital and analog 1.5V (600mA) supply voltages. The FPGA core - one of the most dominant power consumers - is fed from this lower voltage line, thus we selected a more efficient switched DC-DC regulator for these rails. Finally, the unregulated source supply (wall, USB or battery) is made available for the rest of the system
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Figure 6. Photo of the Powerboard
Our primary goals with the current implementation were to support readily available power sources (USB, wall adapters, batteries), provide selective
to enable custom power regulation on other boards. Accurate current and energy measurement are equally important for experimentation and education. Our belief is that significant portion of current wireless sensor network research is based on inaccurate or outright false presumptions of power requirements of various subsystems. This is partly due to the highly integrated nature of current off-the-shelf components. We seek better and deeper understanding of power consumption characteristics of various parts of the WSN node. The instantaneous current on all six power rails are measured by MAX9938 precision current-sense amplifiers with 50m sense resistors. These series resistors causes a small currentdependent voltage drop on the rails, but by considering typical current figures, this should be negligible in most cases. An LTC2942 coulomb counter is used for tracking the remaining charge in the battery, measure charge and overall load currents and the battery voltage level. At the heart of the management board is an ARM Cortex-M3 (STM32) microcontroller. This governs the power rail switches, the charging logic and collects consumption data. The currentsense amplifiers are connected the ADC inputs of the chip, whereas the battery gauge is monitored via an I2C communication line. The microcontroller provides a USB 2.0 communication interface to provide remote instrumentation services, such as communication, programming and debugging of the main FPGA component.
Although the current power board is not the most complex component of our architecture, key design decisions had to make when we created the initial prototype. The dimensions of the board (90mm x 56mm) and the connector (64 pos mezzazine) determine the overall form factor of the other boards and that of the entire node. On the connector the various signal groups are shielded by several ground wires while the analog and digital supplies are relegated to the opposite ends. This arrangement minimizes capacitive and inductive crosstalk and promotes the physical separation of these domains on higher boards as well. Beyond the supply networks the management board provides I2C, SPI and GPIO (JTAG) communication interfaces for the main circuit board housing the FPGA component. 7 RESULTS The performance of the baseband FSK transmitter and receiver was evaluated using the BER metric with a fixed set of transmitted vectors. The testbed, described in Section 3.1, was set up to transmit and receive 1000 bits in byte size packets with randomly selected payload. Such a set of transmissions was repeated for baud rates in the range of 2400 to 19200 and for fseparation values of 200 Hz to 6000 Hz, whereas fcenter was set to constant 50 kHz. The BER results plotted in Figure 7, which clearly shows that a minimum bandwidth of approximately 1600 Hz is required for reliable transmission at any baud rate. Above that lower fseparation limit, communication at baud rates 2400, 4800 and 7200 perform with a BER 411
below 1%. Setting the baud rate to 9600, the BER increases roughly to 6%. This BER may be acceptable in certain applications, however, faster symbol switching rates quickly move the BER to unacceptable levels.
Figure 7. Bit error rate as a function of frequency separation for different baud rates
resources each. The former requires large amount of FPGA fabric mainly due to the 32-bit registers and their address decoding logic in it, while the latter needs significant storage area, comparator and counter logic. The Lowpass filter utilizes only one quarter of the receiver logic despite it being a FIR filter with long delay lines. This is due to the hardware-friendly nature of CIC topology and the use of embedded block RAMs. The Correlator block is responsible for approximately one tenth of the receiver data path resource usage, thus it is almost negligible. Note, that as the Microcontroller Subsystem and the Programmable analog blocks are not included as they are not realized in FPGA fabric.
The baseband FSK design comes at a price. That price can be expressed in terms of resource utilization and power consumption. Figure 8 introduces the FPGA fabric usage breakdown among the different design blocks. The overall design takes 85% of the SmartFusion A2F200 device. 2% of that is used for common AMBA bus interface, while 40% and 43% is occupied by the transmitter and receiver interfaces, respectively. The CORDIC module gives almost one third of the transmitter resource usage, which could be reduced by sacrificing bit precision. The TXAPB interface is responsible for almost half of the transmitter resources. The main contributors to this surprisingly large value are the six 32-bit registers and the accompanying address decoding logic. Compared these, the resource need of the - modulator and the DCO is negligible. In the receiver data path, the main contributors are the RX-APB interface module and the Bit decision logic, claiming one third of the receiver
Figure 8. VersaTile (FPGA fabric) resource usage of the baseband FSK SmartFusion design
The power consumption of the SmartFusion device is estimated assuming no duty cycling and 80 MHz and 40 MHz clock rates in the Microcontroller Subsystem and the FPGA fabric, respectively. The distribution of the 212 mW total power consumption is shown in Figure 9. According to the chart, the vast majority, 86% of the power is used by the
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Microcontroller Subsystem, that is by the testbed. The remaining 14% is divided among the transmitter and receiver data paths and the clock network driving them, which corresponds to 12 mW, 7 mW and 10mW, respectively. Comparing the power and resource usage of the individual blocks it becomes evident that the power consumption is not simply a linear function of the resource utilization. Rather it is heavily dependent on the frequency at the registers and nets change. Thus, the power consumption of the APB interfaces is relatively low, while that of the DCO and CORDIC blocks - operating with wide registers at high speed - is reasonably high.
1.
Figure 9. Power usage breakdown of the baseband FSK SmartFusion design (212mW)
8 ACKNOWLEDGEMENTS This work was supported by the National Science Foundation awards 0964592 "CNS-NeTS" and 1035627 "CNS-CPS".
6 REFERENCES
Actel Corporation. Competitive programmable logic power comparison. White paper, April 2008. 2. Kiarash Amiri, Yang Sun, Patrick Murphy, Chris Hunter, Joseph R. Cavallaro, and Ashutosh Sabharwal. Warp, a unified wireless network testbed for education and research. In MSE '07: Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education, pages 53--54, Washington, DC, USA, 2007. IEEE Computer Society. 3. Analog Devices. AD5449: Dual 12-Bit, High Bandwidth Multiplying DAC with Serial Interface. http://www.analog.com/en/digital-to-analogconverters/daconverters/ad5449/products/product.html. 4. Analog Devices. AD7357: Differential Input, Dual, Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC. http://www.analog.com/en/analog-to-digitalconverters/adconverters/ad7357/products/product.html. 5. K. Borre, D.M. Akos, N. Bertelsen, P. Rinder, and S.H. Jensen. A SoftwareDefined GPS and Galileo Receiver. Springer Verlag, 2007. 6. Prabal Dutta, Mike Grimmer, Anish Arora, Steven Bibyk, and David Culler. Design of a wireless sensor network platform for detecting rare, random, and ephemeral events. In Proceedings of the 4th International Symposium on Information Processing in Sensor Networks, IPSN '05, Piscataway, NJ, USA, 2005. IEEE Press. 7. Prabal Dutta, Ye-Sheng Kuo, Akos Ledeczi, Thomas Schmid, and Peter Volgyesi. Putting the software radio on a low-calorie diet. In Hot Topic on Networks, 2010. HotNets-IX. Ninth ACM Workshop on, page 20, 2010. 8. Ettus Research LLC. http://www.ettus.com, 2008. 9. GNU Radio website. http://gnuradio.org, 2008. 10. J. Hill, R. Szewczyk, A. Woo, S. Hollar, D. Culler, and K. Pister. System architecture directions for networked sensors. In Proc. of ASPLOS-IX, November 2000. 11. Jason Hill and David Culler. Mica: a wireless platform for deeply embedded networks. IEEE Micro, 22(6):12--24, 2002.
413
12. Branislav Kusy, Prabal Dutta, Phil Levis, Miklos Maroti, Akos Ledeczi, and David Culler. Elapsed time on arrival: a simple and versatile primitive for canonical time synchronization services. International Journal of Ad Hoc and Ubiquitous Computing, 2(1), 2006. 13. S. Lanzisera, D. T. Lin, and K. Pister. RF time of flight ranging for wireless sensor network localization. In Proceedings of the Workshop on Intelligent Solutions in Embedded Systems, WISES '06, 2006. 14. Steven Lanzisera. RF Ranging for Location Awareness. Dissertation, University of California, Berkeley, 2009. 15. Akos Ledeczi, Thomas Hay, Peter V olgyesi, Robert Hay, Andras Nadas, and Subash Jayaraman. Wireless Acoustic Emission Sensor Network for Structural Monitoring. IEEE Sensors Journal, 2009. 16. P. Levis, S. Madden, J. Polastre, R. Szewczyk, K. Whitehouse, A. Woo, D. Gay, J. Hill, M. Welsh, E. Brewer, and D. Culler. Tinyos: An operating system for wireless sensor networks. Ambient Intelligence, Sprinter-Verlag, 2005. 17. Miklos Maroti, Branislav Kusy, Gyula Simon, and Akos L edeczi. The flooding time synchronization protocol. In Proc. of ACM SenSys, pages 39--49, November 2004. 18. Miklos Maroti, Peter Volgyesi, Sebestyen Dora, Branislav Kusy, Andras Nadas, Akos Ledeczi, Gyorgy Balogh, and Karoly Molnar. Radio interferometric geolocation. In Proceedings of the 3rd International Conference on Embedded Networked Sensor Systems, SenSys '05, pages 1{12, New York, NY, USA, 2005. ACM. 19. Zoran Miljanic, Ivan Seskar, Khanh Le, and Dipankar Raychaudhuri. The winlab network centric cognitive radio hardware platform. Mobile Networks and Applications, 13(5):533--541, Oct 2008. 20. G.J. Minden, J.B. Evans, L. Searl, D. DePardo, V.R. Petty, R. Rajbanshi, T. Newman, Q. Chen, F. Weidling, J. Guffey, D. Datla, B. Barker, M. Peck, B. Cordill, A.M. Wyglinski, and A. Agah. Kuar: A flexible software-defined radio development platform. In New Frontiers in Dynamic Spectrum Access Networks, 2007. DySPAN 2007. 2nd IEEE International Symposium on, pages 428{439, April 2007.
21. The OpenBTS Project. http://openbts.sourceforge.net/. 22. Joseph Polastre, Robert Szewczyk, and David Culler. Telos: Enabling ultra-low power wireless research. In Proc. of IPSN/SPOTS, April 2005. 23. Actel SmartFusion FPGA Device Family. http://www.actel.com/products/SmartFusion /default.aspx. 24. Todd Dust, Cypress Semiconductor. AN60594 - PSoC 3 and PSoC 5 - 1200 Baud FSK Modem. Application Note, Feb 2011. 25. Jack Volder. The cordic computing technique. In Papers presented at the the March 3-5, 1959, western joint computer conference, IRE-AIEE-ACM '59 (Western), pages 257--261, New York, NY, USA, 1959. ACM. 26. Peter Volgyesi, Gyorgy Balogh, Andras Nadas, Christopher Nash, and Akos Ledeczi. Shooter localization and weapon classication with soldier-wearable networked sensors. In Proc. of the 5th International Conference on Mobile Systems, Applications, and Services (MobiSys), 2007. 27. Peter Volgyesi, Janos Sallai, Sandor Szilvasi, Prabal Dutta, and Akos Ledeczi. Marmot: A novel low-power platform for WSNs. In Networked Digital Technologies, 2010. NDT 2010. Second International Conference on, pages 274--280, 2010.
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International Journal of Digital Information and Wireless Communications (IJDIWC) 1(2): 401-414 The Society of Digital Information and

Wireless Communications, 2011(ISSN 2225-658X)

Figure 1. Block diagram of the baseband FSK SmartFusion design.

Figure 2. Simulated FSK TX and RX signals

Figure 3. Experimental low-power SDR architecture

Figure 5. Beaverboard prototype

(b) Figure 4. LTspice simulation of the DAC and amplifiers

Figure 6. Photo of the Powerboard

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