Lecture9 Latches Flipflops

In this lecture:
Lecture 9: Latches & Flip-flops
Dr Pete Sedcole • Introduction to sequential circuits

Department of Electrical & Electronic Engineering
Imperial College London • Synchronous and asynchronous circuits
http://cas.ee.ic.ac.uk/~nps/ • Overview of flip-flops and latches
(Floyd 7.1 – 7.3)
(Tocci 5.1 – 5.10)
E1.2 Digital Electronics 1 9.1 13 November 2008 E1.2 Digital Electronics 1 9.2 13 November 2008
General digital system diagram Properties of sequential circuits
• In the last eight lectures we have covered combinational logic

– the outputs of the circuit depend only on the current values of the
input variables
• In this lecture we will look at sequential logic circuits
– the outputs can depend on the present and past values of the
inputs and the outputs
• At any moment in time, a sequential circuit exists in one of a number
of predetermined states
– it moves through a defined sequence of transitions from one
state to the next
– the output variables are used to describe the state of a
sequential circuit, either directly or through derived
state variables
Example Synchronous and asynchronous
• Synchronous sequential logic:

• This binary counter – the time at which transitions between circuit states occurs is
A
counts the number of A controlled by a common clock signal
times a pulse occurs – changes in all variables occur simultaneously
C[7:0] C[7:0] 0 1 2 3
on input A • Asynchronous sequential logic:
• The outputs C[7:0] – state transitions occur independently of any clock, and normally
depend on the past depend on the time at which input variables change
• The state of the circuit – outputs do not necessarily change simultaneously
in this case is the • Clock
value of C[7:0]
– a clock signal is a square wave of a fixed frequency
– it is used to trigger state transitions at fixed times in synchronous
circuits
Flip-flops and latches Flip-flops and latches
• Flip-flops and latches are the fundamental elements of sequential

circuits Q = 1 is the
SET state
– bistable (two stable states)
Q normal output Q = 0 is the
• Flip-flops and latches are essentially 1-bit storage devices inputs: FF RESET state
– outputs can be set to store either 1 or 0 depending on the inputs or
data/control latch
– even when the inputs are deasserted, the outputs retain their
Q inverted output
prescribed values
• Flip-flops and latches (normally) have 2 complementary outputs
– usually denoted Q and Q
• Three main types: latches and flip-flops are bistable circuits
– R-S J-K D-type
A S-R latch built from NAND gates S-R latch: SET operation
1 1
1 1
SET 0 Q SET 1 Q 0 0
1 t0 t1 1 t0 t1
0 SET Q 0 SET Q
t0 t1 t0 t1
Q Q
1 1
RESET 1 RESET 0
Q Q
RESET RESET
1 1 1 1
0 0
This NAND gate latch has two possible stable states when t0 t1 t0 t1
SET = RESET = 1
A negative pulse on SET puts the latch in HIGH (SET) state
S-R latch: RESET operation Set-Reset latch symbol and truth table
1 1
0 0 SET Q S R Output
S Q 1 1 No change
1 t0 t1 1 t0 t1
SET Q SET Q 0 1 Q=1
1 0 Q=0
Q R Q 0 0 Invalid
RESET
1 Q 1 Q
0 RESET 0 RESET
1 1 SET
t0 t1 t0 t1
0 0
t0 t1 RESET
t0 t1
A negative pulse on RESET puts the latch in LOW (RESET) state Q
S-R latch to debounce a switch A NOR gate S-R latch
SET Q S R Output
S Q 0 0 No change
1 0 Q=1
0 1 Q=0
Q R Q 1 1 Invalid
RESET
SET
RESET
D latch (transparent latch) D latch timing
Clock signals and flip-flops Set-Reset (S-R) flip-flop
Synchronous digital systems: “positive edge” or
“positive-going transition” (PGT) S R CLK Output
S Q
• the state bits of the circuit all Clocked flip-flop: 0 0 ↑ No change
change simultaneously 1
the output only CLOCK CLK 1 0 ↑ Q=1
• the changes occur at fixed 0 changes at the 0 1 ↑ Q=0
points in time “negative edge” or positive edges of R Q 1 1 ↑ Invalid
• the control signal which “negative-going transition” (NGT) the clock
indicates it is time to change is
called the clock Flip-flops are CLOCK
sometimes called
Q Q
data and edge-triggered S
Flip-flop control inputs
symbols:
R
CLK CLK
Q Q
CLK is activated by Q
a positive edge CLK is activated by
E1.2 Digital Electronics 1 9.17 a negative edge 13 November 2008 E1.2 Digital Electronics 1 9.18 13 November 2008
Internal circuitry of a S-R flip-flop

S-R latch
J-K flip-flop
S SET
This is a simplified Q
diagram of the inside
of a S-R flip-flop
edge
CLK
detector
CLK*
Q
R
RESET
X CLK X
CLK
CLK* CLK*
Edge detector
circuits for both
positive-edge CLK CLK
and negative-
edge flip-flops X X
CLK* CLK*
Internal circuitry of a J-K flip-flop D flip-flop
D flip-flop from a J-K flip-flop Setup and hold times
CLOCK
DATA
time
tS tH
The data/control inputs to
the flip-flop must be stable: DATA D Q
For a time tS before the clock

edge (the setup time)
CLOCK CLK
For a time tH after the clock Q
edge (the hold time)
Applies to all types of flip-flop
Asynchronous PRESET and CLEAR Application: a frequency divider
• The S, R, J, K and D inputs are called synchronous inputs because
their effects on the output are synchronised with the CLK edge
• A frequency divider circuit takes a square-wave signal at a fixed
• Asynchronous inputs operate independently of the clock and other frequency f and outputs a square-wave signal at a lower frequency
inputs (they are “override inputs”)
• Example: a “divide-by-2” frequency divider, produces an output
• Generally used to put the FF in SET or RESET state immediately
which is
f
2
D Q CLOCK1
Q
CLOCK1 CLK CLOCK2
Q Q
Parallel data transfer using D FFs
E1.2 Digital Electronics 1 9.27 13 November 2008

Lecture9 Latches Flipflops

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Lecture9 Latches Flipflops

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In this lecture:

Lecture 9: Latches & Flip-flops

Dr Pete Sedcole • Introduction to sequential circuits

General digital system diagram Properties of sequential circuits

• In the last eight lectures we have covered combinational logic

• Synchronous sequential logic:

Flip-flops and latches Flip-flops and latches

• Flip-flops and latches are the fundamental elements of sequential

A negative pulse on RESET puts the latch in LOW (RESET) state Q

D latch (transparent latch) D latch timing

Internal circuitry of a S-R flip-flop

D flip-flop from a J-K flip-flop Setup and hold times

For a time tS before the clock

Parallel data transfer using D FFs

E1.2 Digital Electronics 1 9.27 13 November 2008

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