ETR 279

Sequential Circuit Design using PLDs

Objective:
The objective of this laboratory is to introduce the student to the use of sequential circuit design using Programmable Logic Devices (PLDs). Students using state equations and D flip-flops will design sequential circuits. The circuits will be constructed and tested using a PLD.

MaterialsRequired:
Breadboard 5V Power Supply ALLMax Universal Programmer PLDShell 5.0 Software GAL22V10 Programmable Logic Device (PLD)

Introduction: Sequential circuit design considerations

An important topic to consider when designing sequential circuits is the method to be used. There are several possible methods, including the excitation table method and design by state equations. Another important considerations is which type of flipflop to use in the design: SR, JK, D, or T. The JK flip-flop is the most versatile and typically yields the simplest circuit to implement. If a sequential circuit design is to be implemented using PLDs where the number of gates required and the type of flip-flop to be used is not of great concern, it may be advantageous to simply use the simplest design method rather than the most efficient. The simplest design method is in many cases to use state equations with D flip-flops. The general form of the state equation for a D flip-flop is: Q(t +1)=D So the input for each D flip-flop is simply determined by finding an expression for the next state for that flip-flop. An example using this method is shown on the following pages. Furthermore, the example has been implemented using PLDShell 5.0 and is shown in the handout to be provided by the instructor entitled GAL3.PDS.

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Example: Design a 4-bit counter using D flip-flops.
A 4-bit counter, also called a modulo-16 counter, counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and repeats. The state diagram is shown in Figure 1 below.
15
14

1
2

13

12

11

10

Figure 1: State diagram for a 4-bit counter

The corresponding state table is shown in Figure 2 below. Note that the state is shown in decimal form in the state diagram, whereas it is shown in binary form in the state table with bit D as the MSB. Present State C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next State C B A 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0

D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

Figure 2: State table for a 4-bit counter

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The characteristic equation for a D flip-flop is very simple: Q(t + 1) = D. So the expression for the next state is simply connected to the D input on the flip-flop. Expressions for the next state for each of the four flip-flops is determined using Karnaugh maps shown in Figure 3 below.
BA DC 00 00 0 01 11 10
D(t + 1)

01 0

11 0

10 0

BA DC 00 00 0 01 11 10

C(t + 1)

01 0

11 1

10 0

BA DC 00 00 0 01 11 10

B(t + 1)

01 1

11 0

10 1

BA DC 00 00 1 01 11 10

A(t + 1) 01 0 11 0 10 1

0 1 1

0 1 1

1 0 1

0 1 1

1 1 0

1 1 0

0 0 1

1 1 0

0 0 0

1 1 1

0 0 0

1 1 1

1 1 1

0 0 0

0 0 0

1 1 1

Figure 3: Karnaugh maps for the state equations for the 4-bit counter

Minimal SOP expressions for each output yield the state equations shown below in Figure 4:
D(t + 1) = D C + D B + D A + D C B A C(t + 1) = C B + C A + C B A B(t + 1) = B A + B A A(t + 1) = A
Figure 4: State equations for the 4-bit counter

The state equations above are implemented in the circuit shown below in Figure 5.

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D C D B D A D C B A C B C A C B A

D(t + 1)

DD QD QD D

D (MSB)

C(t + 1)

DC QC QC C

B A B A

Count (DCBA) B

B(t + 1)

DD QB QB B

A(t + 1)

DA QA QA A

Clock

Figure 5: Logic Diagram for the 4-bit counter

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Implementing the 4-bit counter using PLDShell The logic diagram in Figure 5 requires 16 gates or flip-flops. It can be easily implemented using a single PLD. The state equations in Figure 6 can be rewritten in the appropriate format for PLDShell. Also note that each term is ANDed with CLR, the clear input. The counter will only count when CLR is HIGH. The state equations for the 4-bit counter as shown previously in Figure 6 are repeated below in order to compare them to the form of the state equations used in PLDShell as shown in Figure 7 below.
D(t + 1) = D C + D B + D A + D C B A C(t + 1) = C B + C A + C B A B(t + 1) = B A + B A A(t + 1) = A

Figure 6: State equations for the 4-bit counter (shown for a second time)

QD := CLR QD / QC + CLR QD / QB + CLR QD / QA + CLR / QD QC QB QA QC := CLR QC / QB + CLR QC / QA + CLR / QC QB QA QB := CLR QB / QA + CLR / QB QA QA := CLR / QA
Figure 7: State equations for the 4-bit counter in PLDShell format

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Preliminary Work:
1. Each student (no teams) should redesign the counter used in the Repeating counter lab. In order to make the counter "self-starting", let all unused counts go to the first count in your sequence. Your Design should include the following: a state diagram (be sure to include all 16 counts) a state table the K-maps used to generate the state equations the state equations the .PDS file used to implement the counter using PLDShell 5.0 using an GAL22V10 PLD. The PDS file should be well documented. Include a SIMULATION section that initiates the counter to count 0 and cycles the counter through 2 full cycles (20 counts). the corresponding .RPT file the corresponding .HST file (waveform file) with a vector COUNT displaying the count the corresponding JEDEC file (.JED) on a floppy disk ready to download into the PLD programmer at the beginning of the lab. You do not need to print this file. 2. If the counter were to be implemented using D flip-flops, 2-input AND gates, 2-input OR gates, and INVERTERS, draw the logic diagram. Include the input clock. Label the output count. What is the total number of gates required? Note that only one PLD will be used to replace this circuit.

Laboratory Work:
Program the PLD using the JED file generated in the Preliminary Work. Construct the circuit used to test the PLD according to the wire-list generated in step 3 of the Preliminary Work. Use a debounced switch on the trainer to clock the counter and verify the count sequence.

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Circuit Title: File Name: Revision: Author: Course: Date: CHIP GAL2 Example 4-Bit Counter GAL3.PDS 1 Student Name ETR 279, Digital Logic Lab 3-1-98 GAL22V10 ;Lattice's GAL22V10 is a 24 pin PLD

;The following detailed description is not required for student projects: ; ;Lattice's GAL22V10 is a 24 pin EECMOS PLD (electrically erasable (E) ;programmable logic device) with the following features: ; Electrically erasable in under 100 ms ; 10 output logic macrocells (OLMC) ; Programmable architecture with up to 21 inputs or 10 outputs ; 4 ns propagation delay - counter frequencies up to 250 MHz ; 20 year retention of programmed data specified ; 100 erase/write cycles specified ; ; Purpose Pins(s) / Notes ; -------------------------------------------------------------; VCC 24 ; GND 12 ; Input or clock 1 ; Inputs only 2-11, 13 ; Outputs or inputs 14 - 23 The number of product terms ; for outputs varies as follows: ; 14, 23 8 product terms ; 15, 22 10 product terms ; 16, 21 12 product terms ; 17, 20 14 product terms ; 18, 19 16 product terms ; pin assignments PIN PIN PIN PIN PIN PIN 1 2 CLK CLR QA QB QC QD ; clock ; clear the counter - reset to count 0000 (active-HIGH) ; LSB for the 4-bit counter ; MSB for the 4-bit counter

; Boolean equations for registers EQUATIONS ;see attached sheet for the development of these equations

;note that registered equations use := ;whereas combinational equations use = QA := CLR * /QA QB := CLR * QB * /QA + CLR * /QB * QA ; state equation for D-register (D flip-flop) A ; state equation for D-register (D flip-flop) B

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QC := CLR * QC * /QA ; state equation for D-register (D flip-flop) C + CLR * QC * /QB + CLR * /QC * QB * QA QD := + + + SIMULATION ; set up vector and trace ; set to known state, preload registers (all low) VECTOR COUNT := [ QD, QC, QB, QA ] TRACE_ON CLR CLK SETF CLR /CLK PRLDF /QD /QC QD QC QB QA ; ; ; ; ; ; ; display the count when the waveforms are generated with D as the MSB show these 6 waveforms on the trace set CLR to 1 (enable the counter) set CLK to 0 (disable the clock for now) initialize the counter to count 0000 CLR CLR CLR CLR * * * * QD * /QA ; state equation for D-register (D flip-flop) D QD * /QB QD * /QC /QD * QC * QB * QA

/QB

/QA

; count 20 times FOR X := 0 TO 19 DO BEGIN CLOCKF CLK END

; clock the counter 20 times

; disable counting, then try 4 more times SETF /CLR FOR X:=0 TO 3 DO BEGIN CLOCKF CLK END ; set CLR to 0 so the counter is disabled

; enable counting, then count 4 times SETF CLR FOR X:=0 TO 3 DO BEGIN CLOCKF CLK END TRACE_OFF ; end of simulation

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