Sie sind auf Seite 1von 28

Field Effect Transistors (FETs) ( )

Two types of FET


1. Junction Field Effect Transistors (JFETs)
2. Metal Oxide Semiconductor FET (MOSFET)
Typical applications:
1 Integrated circuits (digital and analogue) 1. Integrated circuits (digital and analogue)
2. Power amplifiers
3 i i i i 3. High input impedance and low noise
amplifiers (ie for optical communications)
1
Important FET properties
Small size - about 30% smaller than equivalent
BJ T inintegratedcircuit BJ T in integrated circuit.
Can be used as a voltage controlled resistor,
hi hi ll th ti l i i t which is smaller than a conventional ic resistor
High input impedance (10
14
), low noise
Large input time constant (RC) - used as a
memory device (ROM/RAM)
High power dissipation and ability to switch
large currents quickly (ns) - much faster than
2
gecu e squc y( s) uc se
BJ T
Types of FET
Drain
Gate
JFET
Gate
Source
n-channel
D
MOSFET
G
S
sub n-channel
depletion
S
D
b
MOSFET
n-channel
3
G
sub
S
n channel
enhancement
FET compared with BJT FET compared with BJT
C
I
C
BJT is a current controlled current
I
C
B
I
B
I
E
BJT is a current controlled current
source (I
B
controls I
C
)
E
I
E
D
FET is a voltage controlled
I
DS
G
V
DS
current source (V
GS
controls I
DS
)
4
S
V
GS
n-channel JFET structure
p+
Gate
D i
depletion region
E ilib i
n
Source
Drain
Equilibrium
V
DS
p+
G
V
DS
Increasing V
DS
until
channel saturates
n
n
D S
channel saturates
(V
DS
> V
P
)
5
electron flow
channel filament
n-channel JFET structure
p+
Gate
D i
depletion region
E ilib i
n
Source
Drain
Equilibrium
V
DS
p+
G
V
DS
Increasing V
DS
until
channel saturates
n
n
D S
channel saturates
(V
DS
> V
P
)
6
electron flow
channel filament
JFET characteristics
I
DS
V
GS
= 0V I
DS
Ohmic
region
I
DSS
V
GS
0V I
DS
(for V
DS
> V
P
)
V
GS
I
DSS
Saturation region
note wide spread of
characteristics
V
DS
V V
V
V
GS
V
DS
V
GS
=
-
V
P
V
P
Output characteristic
-
V
P
Transfer characteristic
7
NJFET Basic Operation p
Maintain constant V
GS
and vary V
DS
- Set Source and Gate to ground
- Increase V
DS
- electrons flow from Source to
Drain so current I
D
flows from Drain to
Source
Here the JFET operates in the OHMIC
8
e e e J ope es e O C
REGION
- Further increase V
DS
- n-channel p-gate
junction becomes reverse biased creating a junction becomes reverse biased creating a
depletion region which grows as V
DS
increases increases
note that gate current I
G
is negligible
- Further increase V
DS
- the depletion region
increases until it nearly blocks the n-channel y
conduction region
- then I
DS
remains constant (I
DSS
) when V
DS
then I
DS
remains constant (I
DSS
) when V
DS
increases
Here the JFET operates in the
9
Here the JFET operates in the
SATURATION REGION
Consider other values of V
GS
0V
- this increases the depletion region thus
reducing values of I
DS
(and I
DSS
)
- at a critical value of V
GS
(= -V
P
) the
depletion region extends across the p g
conduction channel and only negligible
current flows
Here the channel is said to be PINCHED-
OFF OFF
V
P
is the same value as V
DS
at which the
conduction channel saturates for V = 0V
10
conduction channel saturates for V
GS
= 0V
JFET characteristic equations
Ohmic region

2
2
V I
( )

=
2
2
2
2
DS
P GS DS
P
DSS
DS
V
V V V
V
I
I
P
where I
DSS
= saturation
current current
Saturation region
2

1

=
P
GS
DSS DS
V
V
I I
11
P
V
Transconductance (g
m
)
I
DS 2
1

GS
V
I I 1

=
P
GS
DSS DS
V
I I

GS DSS DS
V I I
1
2
V
GS

=
P
GS
P
DSS
GS
DS
m
V
V
V
I
V
I
g 1
2
Transconductance gm=slopeof transfer characteristic
12
Transconductance gm = slope of transfer characteristic
JFET DC biasing
(Remember that for a BJ T biasing is used to
reduceeffectsof changesin andtemperature) reduce effects of changes in and temperature)
Similarly biasing is required for FETs which
alsomaintainacfeaturessuchashighinput also maintain ac features such as high input
impedance.
3t f FET bi i - 3 types of FET biasing
(i) Fixed biasing
(ii) Self-biasing
(iii) Potentiometer biasing
13
(iii) Potentiometer biasing
Fixed biasing
V
DD
R
I
DS
Fix V
GS
which sets I
DS
R
D
I
G
0
V
DS
V
GS
R
G
V
V
o
I
G
V
GS
= V
GG

2
V
GS V
i
V
GG
I I
V
V
D
S
DSS
GS
P
=

1
V V I R
DS DD DS D
=
14
Self-biasing
V
DD
R
I
DS
I
G
0 thus V
G
= 0
R
D
R
S
creates -ve V
GS
without V
V
DS
V
GS
R
G
V
V
o
I
G
without V
GG
V = V + I R
V
GS V
i
V
G
R
S
V
G
= V
GS
+ I
DS
R
S
Thus the self-bias line is
V I R V
GS
=
-
I
DS
R
S
2
1

GS
V
I I
as before
15
1

=
P
GS
DSS DS
V
I I
as before
Q-point analysis
1. Substitute Bias Line equation for V
GS
in I
DS
equation and solve for I
DSQ
q
DSQ
OR
2 DetermineI graphically: 2. Determine I
DSQ
graphically:
(i) Plot transfer characteristic using:

2
I I
V
V
DS DSS
GS
P
=

1
(ii) Plot self-bias line using:
V I R
GS DS S
=
16
V
GS DS S
Example of self-biasing Q-point analysis
V
DD
I
D
I
DSS
= 10mA
(i) Plot transfer characteristic
V
GS
(V) I
DS
(mA)
0 10
DSS
V
P
=
-
4V
5.1k
-1 5.625
-2 2.5
-3 0.625
-4 0
V
GS
10M
0
(ii) Plot self-bias line
V
GS
(V) I
DS
(mA)
0 0
V
GS
1k
0 0
-4 4
V
GSQ
= -2.2V I
DSQ
= 2.2mA
17
Potentiometer biasing
V
DD
R
I
DS
Allows greater adjustment
of Q point and al e of R
R
D
R
G2
of Q-point and value of R
S
V
DS
V
GS
R
G1
V
V
o
I
G
V
G
= V
GS
+ I
DS
R
S
R
V
GS V
i
V
G
R
S V
R
R R
V
G
G
G G
DD
=
+
1
1 2
I I
V
V
D
S
DSS
GS
P
=

1
2
Use graphical technique
to determine Q-point
18
V
P

to determine Q-point
FET small signal analysis (low frequency)
Common-source amplifier: - has largest
voltage gain - often used - R
s
is bipassed for ac
purposes - high input impedance - variable
output impedance - low noise applications.
Common-drain amplifier: - non-inverted
output voltage - voltage gain near unity - very p g g g y y
high input impedance and low output
impedance. p
Common-gate amplifier: - non-inverted output
voltage- lowinput impedance- voltagegain
19
voltage low input impedance voltage gain
and output impedance similar to CS amplifier.
FET equivalent AC circuit model
G D
D
G D
V
gs
g
m
V
gs
r
ds
V
ds
G
S
S
ds
S
g
m
is transconductance (typically
1ms) 1ms)
r
ds
is drain-source o/p resistance (typically 100k)
Typically r
ds
>> R
load
thus effect of r
ds
is negligible & ignored
20
yp y
ds load ds
g g g
Circuit is a voltage controlled current source (I
DS
= g
m
V
gs
)
Common-source (self-biased) amplifier
V
DD
R
D
I
DS
V
GS
R
G
V
i
V
o
R
S
21
Common-source amplifier
ll i l i l i i small signal equivalent circuit
A (i) ll it i fi it d id l Assume (i) all capacitors are infinite and ideal
(ii) r
ds
>> R
D
and has negligible effect
G D
V
i
= V
gs
g
m
V
gs
R
D
V
o
= V
ds
R
G
S
22
Common-source amplifier
equivalent circuit analysis
V
o
=
-
g
m
V
gs
R
D
V
i
= V
gs i gs
A
v
= V
o
/V
i
=
-
g
m
R
D
R
in
= R
G
R
out
= R
D
23
Common-source amplifier with
source resistor source resistor
V
DD
R
D
I
DS
V
GS
R
V
i
V
o
R
S1
R
G
R
S2
24
Common-source amplifier with source resistor
Small signal equivalent circuit Small-signal equivalent circuit
Assume (i) all capacitors are infinite and ideal
(ii) r
ds
>> R
D
and has negligible effect
G D
V
i
g
m
V
gs
R
V
o
R
G
S
R
D
R
G
R
S1
V
GS
Note the location of S with respect to R
25
Note the location of S with respect to R
S1
Common-source amplifier with source resistor p
Equivalent circuit analysis
V
o
=
-
g
m
V
gs
R
D
V
i
=V +g V R
S1
=V (1+g R
S1
) V
i
V
gs
+ g
m
V
gs
R
S1
V
gs
(1 + g
m
R
S1
)
A V /V R /(1 + R ) R /( + R ) A
v
= V
o
/V
i
=
-
g
m
R
D
/(1 + g
m
R
S1
) =
-
R
D
/(r
m
+ R
S1
)
where r
m
= 1 / g
m
R
in
= R
G
and R
out
= R
D
as before
26
JFET current source
For ideal operation assume that output
resistance is infinite
Set V
GS
= 0V and I
DS
= I
DSS
I
DS
V
GS
27
FET characteristics
MOSFET
MOSFET
I
DS
I
DS
MOSFET
(depletion)
I
DS
MOSFET
(Enhancement)
JFET
I
DSS
V
GS
0
I
DSS
-V
P
-V
T
V
GS
V
T
28
V
GS
< 0V
V
GS
is +ve or -ve V
GS
> 0V