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Department of Electrical Engineering, IIT Kanpur

ESc 201: Introduction to Electronics

4th November, 2013 Home Assignment 12


1. In a certain chemical process control application, a particular relay must operate for certain input conditions. There are three input variables A, B and C, where A is the MSB and C is the LSB. The requirements are as follows: Relay must be ON for 010, 011 and 100. Relay must be OFF for 000, 001 and 110. The remaining input condition will never occur. (a) Obtain a minimum expression for the above relay function using K-map. (b) Realize the above expression using NAND gates only. A 4-input NAND gate is defined by the function f (w, x, y, z ) w.x. y.z . Design a 4-input NAND gate using 2-input NAND gates only. A combinational circuit has 3 outputs F1, F2 and F3 as follows: F1 x. y.z x.z

2.

3.

F 2 x. y.z x. y F 3 x. y.z x. y Design the circuit with decoder and external gates.
4. BCD (binary coded decimal) is a representation of decimal digits using four bits. The decimal digit can have values within 0 to 9. The four bit binary number represents a decimal number N, where N 23 b3 22 b2 21 b1 20 b0 , and b3b2b1b0 is binary number having four bits. We want to use a seven-segment display as shown below to display the decimal number corresponding to 4-bit BCD input. Each segment of display is an LED which glows when logic is 1. Determine the Boolean expression representing logic for each element of display. Minimize the expression using K-map.

b a e g
5. The four bit binary number represents a decimal number A, where A 23 a3 22 a2 21 a1 20 a0 , and a3a2 a1a0 is binary number having four bits. Design a circuit using 16 to 1 MUX to check whether A is prime number or not. Recall that a number A is prime number if it is a natural number greater than 1 that has no other divisors except 1 and the number itself.

c f

Department of Electrical Engineering, IIT Kanpur 6.

ESc 201: Introduction to Electronics

Construct an 8-to-1 MUX using minimum number of 4-to-1 and 2-to-1 MUXs as building blocks. Design the circuit using an 8 x 1 Multiplexer to implement the logic function f ( A, B, C, D) m(2,5,6,8,9,10,11,13,14) . Implement half-adder using 2-input NOR gates only. Implement full adder using two 4 x 1 Multiplexers.

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