Experiment:1

date:12/08/2013

Reg.No : 13MVD0096

Exp.No.1 Design and Implementation of Combinational Circuits

Aim: To design and implement the following combinational circuit. a. Basic Gates Using Dataflow, Structural, Behavioral Modeling b. Half-Adder and Full-Adder using structural and dataflow Modeling c. Half-Subtractor and Full-Subtractor using dataflow and structural modeling. d. Decoder and Encoder using structural and dataflow modeling. e. f. Code Convertor & parity generators using structural and dataflow modeling Multiplexer and De-multiplexer using structural, dataflow and behavioral modeling

Software Details: For design Functional Simulation: ModelSim For design Synthesis: Quartus II For design Implementation: Quartus II Hardware Details: Family: Cyclone II Device: EP2C Package: FBGA Pin count: 484

a. Basic Gates Using Dataflow, Structural, Behavioral Modeling

RTL Code for AND gate: Data Flow Modeling module and_gate(a,b,y); input a,b; output y; wire y; assign y=a & b; endmodule Structural Modeling: module and_gate (a,b,y); input a,b;
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output y; wire y; and(y,a,b); endmodule Behavioral Modeling: module and_gate(a,b,y); input a,b; output y; reg y; always @(a,b) y=a&b; endmodule Test Bench for AND gate module and_gate_tst(); reg a,b; wire y; and_gate m1(a,b,y); initial begin a=1'b0; b=1'b0; #100; a=1'b0; b=1'b1; #100; a=1'b1; b=1'b0; #100; a=1'b1; b=1'b1; #100; $stop; end endmodule

Functional Simulation of AND gate:

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Inference: From the above analysis for AND gate functional verification is performed

RTL Code for OR gate: Data Flow Modeling module or_gate (a,b,y); input a,b; output y; wire y; assign y= a | b; endmodule Structural Modeling: module or_gate(a,b,y); input a,b; output y; wire y; or(y,a,b); endmodule Behavioral Modeling: module or_gate(a,b,y); input a,b; output y; reg y; always @(a,b) y=a | b; endmodule

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Test Bench for OR gate module or_gate_tst(); reg a,b; wire y; or_gate a1(a,b,y); initial begin a=1'b0; b=1'b0; #100; a=1'b0; b=1'b1; #100; a=1'b1; b=1'b0; #100; a=1'b1; b=1'b1; #100; $stop; end endmodule

Functional Simulation of OR gate:

Inference:

From the above analysis for OR gate functional verification is performed.

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RTL Code for XOR gate: Data Flow Modeling module xorgate(a,b,y); input a,b; output y; wire y; assign y= a ^ b; endmodule Structural Modeling:
module xorgate(a,b,y); input a,b; output y; wire y; xor(y,a,b); endmodule

Behavioral Modeling: module xorgate(a,b,y); input a,b; output y; reg y; always @(a,b) y=a ^ b; endmodule
Test Bench for XOR gate module xorgate_tst(); reg a,b; wire y; xorgate a1(a,b,y);

initial begin a=1'b0; b=1'b0; #100; a=1'b0; b=1'b1; #100; a=1'b1; b=1'b0; #100; a=1'b1;
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b=1'b1; #100 $stop; end endmodule

Functional Simulation of XOR gate:

Inference:

From the above analysis for XOR gate functional verification is performed

RTL Code for NAND gate: Data Flow Modeling module nandgate(a,b,y); input a,b; output y; wire y; assign y=~(a&b); endmodule Structural Modeling:
module nandgate(a,b,y); input a,b; output y; wire y; nand(y,a,b); endmodule

Behavioral Modeling: module nandgate(a,b,y); input a,b; output y;

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reg y; always @(a,b) y=~(a&b); endmodule Test Bench for NAND gate module nandtest(); reg a,b; wire y; nandgate a1(a,b,y); initial begin a=1'b0; b=1'b0; #100; a=1'b0; b=1'b1; #100; a=1'b1; b=1'b0; #100; a=1'b1; b=1'b1; #100 $stop; end endmodule

Functional Simulation of NAND gate:

Inference:

From the above analysis for NAND gate functional verification is performed

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RTL Code for NOR gate:

Data Flow Modeling: module norgate(a,b,y); input a,b; output y; wire y; assign y= ~(a|b); endmodule Structural Modeling:
module norgate(a,b,y); input a,b; output y; wire y; nor(y,a,b); endmodule

Behavioral Modeling: module norgate(a,b,y); input a,b; output y; reg y; always @(a,b) y=~(a|b); endmodule Test Bench for NOR gate module nortest(); reg a,b; wire y; norgate a1(a,b,y); initial begin a=1'b0; b=1'b0; #100; a=1'b0; b=1'b1; #100; a=1'b1;b=1'b0; #100; a=1'b1; b=1'b1;

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#100 $stop; end endmodule

Functional Simulation of NOR gate:

Inference:

From the above analysis for NOR gate functional verification is performed

RTL Code for XNOR gate: Data Flow Modeling module xnorgate(a,b,y); input a,b; output y; wire y; assign y= ~(a^b); endmodule Structural Modeling: module xnorgate(a,b,y); input a,b; output y; wire y; xnor(y,a,b);
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Behavioral Modeling: module xnorgate(a,b,y); input a,b; output y; reg y; always @(a,b) y=~(a^b); endmodule Test Bench for XNOR gate module xnortest(); reg a,b; wire y; xnorgate a1(a,b,y); initial begin a=1'b0;b=1'b0; #100;a=1'b0;b=1'b1; #100;a=1'b1; b=1'b0; #100;a=1'b1;b=1'b1; #100 $stop; end endmodule

Functional Simulation of XNOR gate:

Inference:

From the above analysis for XNOR gate functional verification is performed

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b. Half-Adder and Full-Adder using structural and Dataflow Modeling

RTL Code for Half Adder : Structural modeling:
module halfadder(a,b,s,c); input a,b; output s,c; wire s,c; xor (s,a,b); and (c,a,b); endmodule Dataflow modeling: module halfadder(a,b,s,c); input a,b; output s,c; assign s= a^b; assign c=a&b; endmodule

Test Bench for Half Adder : module halfadder_test(); reg a,b; wire s,c; halfadder a1(a,b,s,c); initial begin a=1'b0;b=1'b0; #100; a=1'b0;b=1'b1; #100;a=1'b1;b=1'b0; #100;a=1'b1;b=1'b1; #100 $stop;
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end endmodule

Functional Simulation of Half Adder:

Inference:

From the above analysis for Half adder functional verification is performed

RTL Code for Full Adder: dataflow Modeling: module fuladder (a,b,c,s,cin); input a,b,c; output s,cin; wire w1,w2,w3,s,cin; assign s= a ^ b ^ c; assign w1= a & b; assign w2= b & c; assign w3= c & a; assign cin= w1 | w2 | w3; endmodule structural modeling: module fuladder (a,b,c,s,cin); input a,b,c; output s,cin; wire w1,w2,w3,s,cin;
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xor(w1,a,b); xor(s,w1,c); and(w2,w1,c); and(w3,a,b); or(c,w2,w3); endmodule Test Bench for Full Adder : module fuladder_tst(); reg a,b,c; wire w1,w2,w3; wire s,cin; fuladder a1(a,b,c,s,cin); initial begin a=1'b0;b=1'b0;c=1'b0; #100; a=1'b0;b=1'b0;c=1'b1; #100; a=1'b0;b=1'b1;c=1'b0; #100; a=1'b0;b=1'b1;c=1'b1; #100; a=1'b1;b=1'b0;c=1'b0; #100; a=1'b1;b=1'b0;c=1'b1; #100; a=1'b1;b=1'b1;c=1'b0; #100; a=1'b1;b=1'b1;c=1'b1; #100 $stop; end endmodule

Functional Simulation of Full Adder:

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Inference:

From the above analysis for full adder functional verification is performed

c. Half-Subtractor and Full-Subtractor using Structural and dataflow modeling

RTL Code for Half Subtractor: Dataflow Modeling: module halfsub(a,b,d,bo); input a,b; output d,bo; wire d,bo; assign d=a^b; assign bo=(~a)&b; endmodule Structural Modeling: module halfsub(a,b,d,bo); input a,b; output d,bo; wire w1,d,bo; xor(d,a,b); not(w1,a);

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and(bo,w1,b); endmodule Test Bench for Half Subtractor: module halfsub_test(); reg a,b; wire d,bo; halfsub m1(a,b,d,b0); initial begin
a=1'b0; b=1'b0; #100; a=1'b0;b=1'b1; #100; a=1'b1;b=1'b0; #100; a=1'b1;b=1'b1; #100 $stop; end endmodule

Functional Simulation of Half subtractor:

Inference:

From the above analysis for Half subtractor functional verification is performed

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RTL Code for Full Subtractor : Dataflow Modeling: module fullsub (a,b,c,d,ca); input a,b,c; output d,ca; wire w1,w2,w3,d,ca; assign d= a ^ b ^ c; assign w1= ~a & b; assign w2= b & c; assign w3= c & ~a; assign ca= w1 | w2 | w3; endmodule Structural Modeling: module fullsub (a,b,c,d,ca); input a,b,c; output d,ca; wire w1,w2,w3,w4,w5,d,ca; xor(w5,a,b); xor(d,w5,c); not(w4,a); and(w1,w4,b); and(w2,b,c); and(w3,c,w4); or(ca,w1,w2,w3); endmodule Test Bench for Full Subtractor: module fullsub_tst(); reg a,b,c; wire w1,w2,w3; wire d,ca; fullsub a1(a,b,c,d,ca); initial begin a=1'b0;b=1'b0;c=1'b0; #100; a=1'b0;b=1'b0;c=1'b1; #100; a=1'b0;b=1'b1;c=1'b0; #100; a=1'b0;b=1'b1;c=1'b1; #100; a=1'b1;b=1'b0;c=1'b0;

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#100; a=1'b1;b=1'b0;c=1'b1; #100; a=1'b1;b=1'b1;c=1'b0; #100; a=1'b1;b=1'b1;c=1'b1; #100 $stop; end endmodule

Functional Simulation of Full subtractor:

Inference:

From the above analysis for Full subtractor functional verification is performed

d. Decoder and Encoder using structural and dataflow modeling.

RTL Code for DECODER : Structural: module decoder2to4(a,b,en); input [1:0]a; input en; output [3:0]b; wire w1,w2; wire [3:0]b;
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not(w1,a[0]); not(w2,a[1]); and(b[0],w1,w2); and(b[1],w2,a[0]); and(b[2],a[1],w1); and(b[3],a[0],a[1]); endmodule Dtaflow: module decoder2to4(a,b,en); input [1:0]a; input en; output [3:0]b; wire w1,w2; wire [3:0]b; assign b[0]=w1&w2; assign b[1]=a[0]&w2; assign b[2]=a[1]&w1; assign b[3]=a[1]&a[0]; endmodule

Test Bench for DECODER: module decoder2to4_test(); reg [1:0]a; wire[3:0]b; reg en; decoder2to4 d1(a,b,en); initial begin en=1'b0;a[0]=1'b0;a[1]=1'b0; #100 en=1'b1;a[0]=1'b0;a[1]=1'b0; #100 en=1'b1;a[0]=1'b1;a[1]=1'b0; #100 en=1'b1;a[0]=1'b0;a[1]=1'b1; #100 en=1'b1;a[0]=1'b1;a[1]=1'b1; #100 $stop; end endmodule

Functional Simulation of Decoder:

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Inference:

From the above analysis for 2 to 4 decoder functional verification is performed

RTL Code for ENCODER :

Structural modeling: module encoder(i,d);

input [7:0]i; output [2:0]d; wire [2:0]d; or(d[0],i[1],i[3],i[5],i[7]); or(d[1],i[2],i[3],i[6],i[7]); or(d[2],i[4],i[5],i[6],i[7]); endmodule

Dataflow modeling : module encoder(i,d); input [7:0]i; output [2:0]d; wire [2:0]d; assign d[0]=(i[1]|i[3]|i[5]|i[7]); assign d[1]=(i[2]|i[3]|i[6]|i[7]); assign d[2]=(i[4]|i[5]|i[6]|i[7]); endmodule

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Test Bench for ENCODER: module encoder_test(); reg [7:0]i; wire [2:0]d; encoder e1(i,d); initial begin i=8'b00000001; #100 i=8'b00000010; #100 i=8'b00000100; #100 i=8'b00001000; #100 i=8'b00010000; #100 i=8'b00100000; #100 i=8'b01000000; #100 i=8'b10000000; #100 $stop; end endmodule

Functional Simulation of Encoder:

Inference:

From the above analysis for 8 to 3 encoder functional verification is performed FPGA Lab

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e. Code Convertor & parity generators using structural and dataflow modeling

RTL Code binary to gray converter : Dataflow modeling: module binatogray(g0,g1,g2,g3,b0,b1,b2,b3); input b0,b1,b2,b3; output g0,g1,g2,g3; wire g0,g1,g2,g3; assign g3=b3; assign g2=b3^b2; assign g1=b2^b1; assign g0=b1^b0; endmodule Structural modeling: module binatogray(g0,g1,g2,g3,b0,b1,b2,b3); input b0,b1,b2,b3; output g0,g1,g2,g3; wire g0,g1,g2,g3; buf(g3,b3); xor(g2,b3,b2); xor(g1,b2,b1); xor(g0,b1,b0); endmodule Test Bench for binary to gray converter module binatogray_tst() reg b0,b1,b2,b3;

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wire g0,g1,g2,g3; binatogray e1(g0,g1,g2,g3,b0,b1,b2,b3); initial begin b3=1'b0; b2=1'b0; b1=1'b0;b0=1'b0; #100; b3=1'b0; b2=1'b0; b1=1'b0;b0=1'b1; #100; b3=1'b0; b2=1'b0; b1=1'b1;b0=1'b0; #100; b3=1'b0; b2=1'b0; b1=1'b1;b0=1'b1; #100; b3=1'b0; b2=1'b1; b1=1'b0;b0=1'b0; #100; b3=1'b0; b2=1'b1; b1=1'b0;b0=1'b1; #100; b3=1'b0; b2=1'b1; b1=1'b1;b0=1'b0; #100; b3=1'b0; b2=1'b1; b1=1'b1;b0=1'b1; #100; b3=1'b1; b2=1'b0; b1=1'b0;b0=1'b0;

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#100; b3=1'b1; b2=1'b0; b1=1'b0;b0=1'b1; #100; b3=1'b1; b2=1'b0; b1=1'b1;b0=1'b0; #100; b3=1'b1; b2=1'b0; b1=1'b1;b0=1'b1; #100; b3=1'b1; b2=1'b1; b1=1'b0;b0=1'b0; #100; b3=1'b1; b2=1'b1; b1=1'b0;b0=1'b1; #100; b3=1'b1; b2=1'b1; b1=1'b1;b0=1'b0; #100; b3=1'b1; b2=1'b1; b1=1'b1;b0=1'b1; #100; end endmodule Functional simulation of binary to grey converter:

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Inference:
performed

From the above analysis for 4 bit binary to gray code converter functional verification is

RTL code parity generator : Structural modeling: module parigen(x,y,z,p); input x,y,z; output p; wire p,w1,w2; xor(w1,x,y); xor(w2,w1,z); not (p,w2); endmodule Dataflow modeling: module pgen(x,y,z,p); input x,y,z; output p; wire p,w1,w2; assign w1=x^y; assign w2=w1^z;
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assign p=~w2; endmodule Test Bench of parity generator : module parigen_test(); reg x,y,z; wire p; parigen p1(x,y,z,p); initial begin x=1'b0;y=1'b0;z=1'b0; #100 x=1'b0;y=1'b0;z=1'b1; #100 x=1'b0;y=1'b1;z=1'b0; #100 x=1'b0;y=1'b1;z=1'b1; #100 x=1'b1;y=1'b0;z=1'b0; #100 x=1'b1;y=1'b0;z=1'b1; #100 x=1'b1;y=1'b1;z=1'b0; #100 x=1'b1;y=1'b1;z=1'b1; #100 $stop; end endmodule Functional simulation:

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Inference:

From the above analysis for odd parity generator functional verification is performed

f. Multiplexer and De-multiplexer using structural, dataflow and behavioral modeling

RTL code for Multiplexer : Structural modeling: module mux4to1(in,se,y); input[3:0]in; input [1:0]se; output y; wire y,w1,w2,w3,w4,w5,w6; not (w1,se[0]); not (w2,se[1]); and(w3,in[0],w1,w2); and(w4,in[1],se[0],w2); and(w5,in[2],w1,se[1]);

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and(w6,in[3],se[0],se[1]); or (y,w3,w4,w5,w6); endmodule Dataflowmodelling: module mux4to1(in,se,y); input[3:0]in; input [1:0]se; output y; wire y,w1,w2,w3,w4; assign w1=(in[0]&(~se[0])&(~se[1])); assign w2=(in[1]&(~se[0])&(se[1])); assign w3=(in[2]&(se[0])&(~se[1])); assign w4=(in[3]&(se[0])&(se[1])); assign y=(w1|w2|w3|w4); endmodule Behavioral modeling: module mux4to1(in,se,y); input[3:0]in; input [1:0]se; output y; reg y; always@(se or y) begin if(se==2'b00) y=in[0]; else if(se==2'b01) y=in[1]; else if(se==2'b10)

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y=in[2]; else if(se==2'b11) y=in[3]; end endmodule Test bench Code for 4:1 Multiplexer: module mux4to1_tst(); reg [3:0]in; reg [1:0]se; wire y; mux4to1 g1(in,se,y); initial begin in=4'b0000;se=2'b00; #100; in=4'b1111; se=2'b01; #100; in=4'b0101; se=2'b10; #100 in=4'b1111;se=2'b11; #100

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$stop; end endmodule

Functional Simulation of Multiplexer:

Inference:

From the above analysis for 4 to 1 multiplexer functional verification is performed

RTL Code for 1:4 Demultiplexer : structural modeling: module demux(i,s,y); input i; input [1:0]s; output [3:0]y; wire w1,w0; not(w0,s[0]); not(w1,s[1]);

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and(y[0],i,w1,w0); and(y[1],i,w1,s[0]); and(y[2],i,s[1],w0); and(y[3],i,s[1],s[0]); endmodule Dataflow modeling: module demux(i,s,y); input i; input [1:0]s; output [3:0]y; wire w1,w0; assign w0=~s[0]; assign w1=~s[1]; assign y[0]=i&w1&w0; assigny[1]=i&w1&s[0]; assigny[2]=i&w0&s[1]; assigny[3]=i&s[1]&s[0]; endmodule Behavioral modeling: module demux(i,s,y); input i;

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input [1:0]s; output [3:0]y; reg[3:0]y; always@(s or y) begin if(s==2'b00) begin y[0]=i;y[1]=1'b0;y[2]=1'b0;y[3]=1'b0; end else if(s==2'b01) begin y[0]=1'b0;y[1]=i;y[2]=1'b0;y[3]=1'b0; end else if(s==2'b10) begin y[0]=1'b0;y[1]=1'b0;y[2]=i;y[3]=1'b0; end else if(s==2'b11) begin y[0]=1'b0;y[1]=1'b0;y[2]=1'b0;y[3]=i; end end endmodule Test Bench for 1:4 Demultiplexer: module demux_tst(); reg i; reg [1:0]s; wire [3:0]y; demux r1(i,s,y);

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initial begin s=2'b00;i=1'b1; #100 s=2'b01;i=1'b1; #100 s=2'b10;i=1'b1; #100 s=2'b11;i=1'b1; #100 $stop; end endmodule

Functional Simulation of De-multiplexer:

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Inference:

From the above analysis for 1 to 4 demultiplexer functional verification is performed

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