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C Computer t E Eng 1
HOANG Trang hoangtrang@hcmut edu vn, TA: Bui Minh Thanh. 203 B3
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Main references
M.Morris M Morris and Charles R R.Kime, Kime Logic Logic and computer design fundamentals. ISBN: 0-13-1911651 0 13 1911651 Pearson Prentice Hall, Pearson Education Inc >600 pages

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Course Goals
To design and analyze combinational and sequential logic networks. To understand the principles of computer organization. organization To develop the skills required to solve engineering problems. To develop critical thinking skills to analyze ethical dilemmas. To know how computers execute instructions. To be able to design the hardware of a computer.

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Major Topics
Representation of information, two's complement arithmetic. Combinational logic: switching algebra, algebra canonical forms, Karnaugh maps, combinational network analysis and design, MSI modules. Sequential logic: latch, latch flip-flop, flip-flop state diagram, diagram sequential network analysis and synthesis, register, counter, memory organization. Computer organization: register-transfer register transfer language language, arithmetic-logic unit, fetch-execute microsequences, loop, subroutine, interrupt, microprogrammed control unit. Computer ethics.

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Specific Instructional Objectives? (1/4)


obtained !!!???

1. Representation of information
Convert between decimal, binary, octal, and hexadecimal representations of integers Determine the number of errors that a code can detect or correct Understand two's complement representation of integers and determine whether overflow occurs in arithmetic operations Distinguish between a variety of decimal and alphanumeric codes

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Specific Instructional Objectives? (2/4)

2. Design and analysis of combinational networks
Understand the operation of discrete logic gates Analyze a combinational network using Boolean expressions Convert a verbal specification into a Boolean expression Understand basic properties of Boolean algebra: duality, complements, standard forms Apply Boolean algebra to prove identities and simplify expressions Use Karnaugh maps to find minimal sum-of-products and productsof-sums f expressions i Design combinational networks that use NAND, NOR, and XOR gates Design with MSI components such as encoders, decoders, multiplexers, adders, arithmetic-logic units, ROMs, and programmable logic arrays Calculate delays in ripple carry adders and combinational arrays

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Specific Instructional Objectives? (3/4)

3. Design and analysis of sequential networks
Understand the operation of latches; clocked, clocked master-slave, master slave and edge-triggered flip-flops; shift registers; and counters Plot and interpret timing diagrams Determine the functionality y of sequential q circuits from state diagrams and timing diagrams Translate sequential circuit specifications into state diagrams Design sequential circuit components (latches, flip-flops, registers synchronous counters) using logic gates registers, Synthesize general sequential circuits Understand tradeoffs in register and counter design

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Specific Instructional Objectives? (4/4)

4. Computer p organization g
Understand the operation of tri-state buffers and their uses in multiplexing outputs and enabling bi-directional signaling Understand the operation of random access memories S th i a large Synthesize l memory from f smaller ll memories i and d decoders d d Design datapath components, including register files, buses, and functional units Design a hardwired control unit to implement an instruction set Design a microprogrammed control unit Understand tradeoffs between hardwired and microprogrammed control Understand instruction formats and addressing modes Understand the operation of stack instructions, control flow, and interrupts Specify new instructions and addressing modes in register transfer language Translate register transfer language statements into microcode y the effects of individual instructions and machine-level Analyze programs Write short machine-level programs!!!
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1. 1 2. 3. 4. 5. Attendance at class class, Quiz: 10% Homework: 20% Project: j 10% Midterm exam: 20% Final term: 40%

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