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22.8 A [10C ; 70C] 640480 17m Pixel Pitch TEC-Less IR Bolometer Imager with Below 50mK and Below 4V Power Supply
The CTIAs gain can be set between 5 and 70V/A. At 30C, such a high gain allows for an output NETD that is only 2% higher than the intrinsic sensitive bolometers NETD. To compensate for the remaining FPN, offset pre-correction (OPC) is implemented: thermalized bolometers provide currents {Ioff, Ioff/2, Ioff/4, Ioff/8} that are combined according to the 4b values stored in each pixel. These pixel registers are read just before the pixels of the active row start their integration. By reducing mismatch impact before integration, OPC prevents the CTIA from saturating under thermal drift, especially at high gain. By being less sensitive to thermal drift, a low gain would enable a larger TEC-less range, but the read-out chain would intolerably degrade the output NETD. Conversely for a given TEC-less range, the OPC enables a reduction in the constraints on bolometer mismatches. This constitutes a key factor when low-cost microbolometer imagers are targeted. These properties are demonstrated by Fig. 22.8.3, which shows the output voltage of a classic architecture and our mirror architecture. It also shows the impact of 1% bolometer current mismatch on operability. The other benefit of the 4b OPC is to allow centering and tightening the raw image histogram. An optimal conversion gain with respect to output NETD can be applied even for high mismatch chips, as shown Fig. 22.8.4, or to correct sun blooming. The readout chain is about 95% of the 170mW total power consumption. Achieving low power consumption implies reducing power supply. The NETD is improved by increasing dissipated power into bolometers. Therefore, considering a constant NETD target, RI must remain constant when power supply, i.e. RI, is lowered. Since biasing current and thus self-heating are increased, achieving TEC-less abilities is harder with a 4V power supply than with a 5V or higher power supply. Designed in 0.18m CMOS technology, the presented ROIC allows a TEC-less capability with a low 4V power supply without using off-chip compensation tables. To the best of our knowledge, this micro-bolometer imager is the only 17m pixel pitch one that features a NETD less than 50mK over a [10C ; 70C] operating range (see Fig. 22.8.5), thanks to its enhanced differential architecture. The differential architecture is naturally TEC-less, regardless of bolometer resistance values. The digital OPC reduces the impact of FPN and contributes to extend the TEC-less range. Finally, the enhanced differential architecture also rejects supply noise by a factor of 50, and so makes the circuit fully compliant with harsh environments. Acknowledgment: The authors would like to acknowledge the French MOD (DGA) for funding this research program. References: [1] A. Durand, C. Minassian, J.L Tissot, et al., Uncooled Amorphous Silicon TEC-less VGA IRFPA with 25m Pixel-Pitch for High Volume Applications. Proc. SPIE, vol. 6940, Infrared Technology and Applications XXXIV 69401V, Apr. 2008. [2] C. Li, C.J. Han, G.D. Skidmore, and C. Hess DRS Uncooled VOx Infrared Detector Development and Production Status, Proc. SPIE, vol. 7660, Infrared Technology and Applications XXXVI 76600V, Apr. 2010. [3] U. Mizrahi, A. Fraenkel, L. Bykov, et al., Uncooled Detector Development Program at SCDU. Mizrahi, A. Fraenkel, L. Bykov, A. Giladi, A. Adin, E. Ilan, N. Shiloah, E. Malkinson, Y. Zabar, D. Seter, R. Nakash, Z. Kopolovich Semi Conductor Devices (Israel), Proc. SPIE, vol. 5783, Infrared Technology and Applications XXXI 551, May 2005. [4] A. Durand, J.L. Tissot, P. Robert, et al., VGA 17m Development for Compact, Low-Power Systems, Proc SPIE, vol. 8012, Infrared Technology and Applications XXXVII 80121C, Apr. 2011. [5] B. Dupont, A. Dupret, E. Belhaire, and P. Villard, FPN Sources in Bolometetric Infrared detectors, IEEE Sensors Journal, vol. 9, no. 8, pp. 944952, Aug. 2009.

Bertrand Dupont, Antoine Dupret, Sebastien Becker, Antoine Hamelin, Fabrice Guellec, Pierre Imperinetti, Wilfried Rabaud
CEA-LETI-MINATEC, Grenoble, France Used in low-cost thermal imaging, 8-to-12m infrared micro-bolometer hybrid detectors are very demanding in terms of offset skimming and technological fluctuation compensation: typical offset values are about 100 times larger than the signal, while the fixed-pattern noise (FPN) is about 10 times larger. State-ofthe-art image sensors feature noise-equivalent temperature difference (NETD), i.e. thermal resolutions, of about 50mK. To reach such an NETD, and considering the dependency of both offset and FPN to the temperature of the focal plane, a thermo-electrical cooler (TEC) is used to prevent the temperature of the focal plane from varying either spatially and temporally. This paper presents a 640480 17m-pitch TEC-less IR bolometer imager that features an NETD below 50mK over a 60C range, while keeping a low 4V power supply. It also features a figure of merit of only 400mK/ms, which reflects its ability to deliver 50mK NETD lag-free images at 60fps. Getting rid of the TEC is a key issue to spread the use of microbolomoter imagers to cost-sensitive markets (e.g. automotive) or to extend the battery life of portable devices (e.g. gun sight). Few works to achieve TEC-less capabilities have been reported to date [1-4]. This circuit is based on an enhanced differential pixel read-out (Fig. 22.8.1), which differs from the classical bolometer read-out architectures [1,2]. As with all microbolometer imagers, this circuit is based on sensitive thermistor arrays (i.e. the bolometers), processed on top of a CMOS read-out circuit (ROIC). A bolometers resistance varies according to its temperature, which is linked to biasing, self-heating, focal-plane temperature, and scene temperature. The differences between the sensitive bolometers and a blind, i.e. shielded or a thermalized, reference bolometer gives an image of the scene temperature. This difference is less accurate when the characteristics of the reference bolometer differ from the sensitive bolometer (i.e. polarization, duty cycle, and physical design). The read-out circuit also impacts the accuracy of the difference and its sensitivity to temperature [5]. To sum up the TEC-less characteristic implies to keep output NETD over a large thermal range, without tuning either the supplies or polarizations of the circuit. So it depends on conversion gain, mismatch, and the offset level drift. This work is an improvement on [1], for which thermal drift of NMOS and PMOS differs, except for a specific polarization point. Finding such a polarization point for each imager design makes this architecture suffer from a lack of flexibility. The presented circuit is also an improvement over [2] and [3], for which the TEC-less ability is obtained by using a temperature probe and correction tables in order to modify polarization conditions. Such an approach implies costly calibration steps and power-consuming off-chip processing. In the presented circuit, the reference is provided by a shielded bolometer with the same characteristics as the sensitive bolometer. A shielded bolometer is located at the end of each row of the pixel array. Therefore, since the pixel array is read in a rolling-shutter way, the shielded bolometer has the same thermal cycle as the sensitive bolometers of the sensitive pixel array. For both the reference and the sensitive branch, PMOS voltage followers with identical gate voltage force identical voltages across both bolometers. On the reference branch, the Buffered Direct Injection (BDI) forces Vref on the drain of the PMOS. It prevents Early effect and allows a more accurate copy of the current. To keep the reference branch noise below the sensitive branch, dominated by 1/f noise, large NMOS are designed. As a result, the BDI has a load about 800pF, and rejects the 1/f noise by a factor of 50 in the [1Hz ; 5KHz] bandwidth (Fig. 22.8.2).


2013 IEEE International Solid-State Circuits Conference

978-1-4673-4516-3/13/$31.00 2013 IEEE

ISSCC 2013 / February 20, 2013 / 11:30 AM

Figure 22.8.1: Circuit architecture.

Figure 22.8.2: Noise rejection for classic and mirror architecture.

Figure 22.8.3: DC level vs. temperature for classical and mirror mode, and impact of 1% mismatch on output voltage.

Figure 22.8.4: Offset Pre-Correction impact on histogram, and image of a blackbody.


Figure 22.8.5: NETD performances without TEC.

Figure 22.8.6: Performance summary.




Figure 22.8.7: Picture of our 17x14mm circuit glued on ceramic.

2013 IEEE International Solid-State Circuits Conference

978-1-4673-4516-3/13/$31.00 2013 IEEE