Lic Manual

5124-SARASWATHI VELU COLLEGE OF ENGINEERING
ELECTRONICS AND COMMUNICATION ENGINEERING

ANNA UNIVERSITY -CHENNAI
REGULATION 2008
II YEAR/IV SEMESTER

EC 2258
LINEAR INTEGRATED CIRCUITS LABORATORY
LAB MANUAL

PREPARED BY
P.MEENA- AP/ECE,

LINEAR INTEGRATED CIRCUITS LAB MANUAL II YEAR

2
SL.NO
EXPERIMENTS NAME
PAGE
NO
1
Inverting, Non inverting and Differential amplifiers.
21
2 Integrator and Differentiator. 27
3 Active Filter LPF, BPF,HPF 33
4 Square wave generator- Astable multivibrator 41
5
Monostable multivibrator
44
6
IC 555 Timer-Monostable Operation Circuit

47
7
IC 555 Timer-Astable Operation Circuit
51
8
Schmitt Trigger Circuits- using IC 741 & IC 555
56
9
RC phase shift oscillator
61
10
Wein bridge oscillator
65
11
Frequency multiplier using PLL

68
12
Voltage Regulator using IC723

71
13
Simulation Using ORCAD
76
References 90


3
LIST OF EXPERIMENTS

Design and testing of
1. Inverting, Non inverting and Differential amplifiers.
2. Integrator and Differentiator.
3. Instrumentation amplifier
4. Active lowpass, Highpass and bandpass filters.
5. Astable & Monostable multivibrators and Schmitt Trigger using op-amp.
6. Phase shift and Wien bridge oscillators using op-amp.
7. Astable and monostable multivibrators using NE555 Timer.
8. PLL characteristics and its use as Frequency Multiplier.
9. DC power supply using LM317 and LM723.
10. Study of SMPS.
11. Simulation of Experiments 3, 4, 5, 6 and 7 using PSpice netlists.

Note: Op-Amps uA741, LM 301, LM311, LM 324 & AD 633 may be used


4
LIST OF EQUIPMENTS AND COMPONENTS

1. Dual ,(0-30V) variable Power Supply
2. CRO 30MHz
3. Digital Multimeter
4. Function Generator 1 MHz
5. IC Tester (Analog)
6. Bread board
7. Computer (PSPICE installed)

Consumables (Minimum of 25 Nos. each)

1. IC 741
2. IC NE555
3. LED
4. LM317
5. LM723
6. ICSG3524 / SG3525
7. Transistor 2N3391
8. Diodes, IN4001,BY126
9. Zener diodes
10. Potentiometer
11. Step-down transformer 230V/12-0-12V
12. Capacitor
13. Resistors 1/4 Watt Assorted
14. Single Strand Wire


5

DESIGN OF INVERTING, NON INVERTING AND DIFFERENTIAL AMPLIFIERS

EX.NO: 1
DATE:

AIM:
To design and construct a inverting, non- inverting and differential amplifiers.

APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY

1.
2.
3.
4.
5.
6.
7.

Resistor
Op-amp
Dual RPS
AFO
CRO
Bread board
Connecting wires

10k
IC741
(0-30)v
-
-
-
-

5
1
1
2
1
1
As
required
THEORY:
INVERTING AMPLIFIER:
This is the most widely used op-amp. Here, the output voltage Vo is feedback to the
inverting input terminal through the Rf R1 network. The negative sign in gain indicates the
phase shift of 180
.
NON - INVERTING AMPLIFIER:
If signal is applied to the non-inverting input terminal of op-amp without inverting the
input signal such a circuit is called non-inverting amplifier. Here the output is feedback to the
inverting input terminal. The phase shift of input signal does not occur in non-inverting terminal.
DIFFERENTIAL AMPLIFIER

6
A circuit that amplifies that amplifies the difference between two input signals is called
as differential amplifier. It is useful in instrumentation amplifier. If the two input signals are the
same, the output should be zero.
DESIGN:
Inverting amplifier:
A = -Rf/R1
Take A = 1
Rf = R1
Choose Rf = 10k, R1=10k

Non inverting amplifier:
A = 1+ Rf/R1
Take A = 2
Rf = R1
Choose Rf = 10k, R1=10k

Differential amplifier
a) In common mode
V
1
= V
2
= V
V
c
=
=V
A
c
=

V
d
= V
1
-V
2
=V-V =0
b) In difference mode
V
1
= -V
2
= V
V
d
= V
1
-V
2

A
d
=

V
c
=

CIRCUIT DIAGRAM:
INVERTING AMPLIFIER

7
R
1
V
in
R
f
2
3
+
_
741
+V
cc
7
4
-V
cc
6 V
0

NON-INVERTING AMPLIFIER
R
1
V
in
R
f
2
3
+
_
741
+V
cc
7
4
-V
cc
6 V
0



8

MODEL GRAPH:
Inverting Amplifier

Non inverting Amplifier:


9

TABULATION:
INVERTING AMPLIFIER:

S.NO Vin
Vo = Vin(-Rf/R1)
Gain = Vo/Vin
Theoretical practical

NON- INVERTING AMPLIFIER:

S.NO Vin
Vo = Vin(1+Rf/R1)
Gain = Vo/Vin
Theoretical practical

Mode of operation V
in
Vout Gain CMRR

PROCEDURE:

Inverting and Non-inverting amplifier:
1. Connections are made as per the circuit diagram.
2. Apply the input voltage using AFO or RPS.
3. The output is noted and plots the graph.
4. Then calculate the gain value.


10
Differential amplifier
1. Connections are made as per the circuit diagram
2. For the common mode operation of the differential amplifier, apply the same input
voltage to the both the input terminals.
3. Note down the output voltage
4. For the differential mode operation of the differential amplifier, apply the same input
voltage to the opposite voltages the input terminals.
5. Measure the output voltage
6. Calculate the difference mode gain
7. Calculate the CMRR


11

INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
EX.NO: 2
DATE:
AIM:

To design and test the performance of integrator and differentiator circuits using
Op-amp.

APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1.
2.
3.
4.
5.
6.
7.
8.

Signal generator
CRO
Resistors
Capacitor
Op-amp
Breadboard
Dual power supply
Connecting wires

1KO, 10KO
0.1F
IC741
1
1
1
1
1
1
1
AS REQURIED

THEORY:

Integrator: In an integrator circuit, the output voltage is integral of the input signal. The output
voltage of an integrator is given by V
o
= -1/R
1
C
f
Vidt
t
o
}

At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open
circuit. The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with
capacitor.
Differentiator: In the differentiator circuit the output voltage is the differentiation of the input
voltage. The output voltage of a differentiator is given by V
o
= -RfC
1

dt
dV
i
.The input impedance of this
circuit decreases with increase in frequency, thereby making the circuit sensitive to high frequency noise.
At high frequencies circuit may become unstable.


12
DESIGN:

INTEGRATOR:
Given :
R1= 10 KO ; f= 4 kHz
C
f
= 1/ (2Rf)
R
f
= 10 R
= 10 * 10 KO = 100 KO
C
f
= 1/ (2 * 10
3
*10*4*10
3
)
= 0.039 f

DIFFERENTIATOR:

Given:
C
1
= 1 f ; f
1
= 150 kHz
R
f
= 1/ (2C
1
f
1
)
= 1/ (2*3.14*1*10
-6
*150)
R
f
= 1.06 KO
C
f
= R
1
C
1
/R
f

= 1.06*10
-3
*0.1*10
-6

10.6 * 10
3

C
f
= 0.01 f
R
f
= 100KO

INTEGRATOR

C
f
= 0.03F

10KO +Vcc=12V

2 7
-
R
1

3 IC741
+
+
V
in
4

- -Vee=-12V
R
10kO

CRO

13
DIFFERENTIATOR
R
f
= 1.06KO

0.01 F
1.06 K O 0.1 F
2 7
-

3 IC741

+
4

-Vee=-12V

1kO

MODEL GRAPH:
DIFFERENTIATOR
Vi

INPUT SIGNAL

t (msec)

Vo

t(msec)

CRO
AFO
O

14

INTEGRATOR

Vi

INPUT SIGNAL

t (msec)

Vo

OUTPUT SIGNAL

t(msec)

TABULATION:

INTEGRATOR:

PARAMETER THEORITICAL PRACTICAL
1. Frequency
2. I/P time period
3. O/P time period
4. I/P Amplitude
5. O/P Amplitude


15
DIFFERENIATOR:

PARAMETER THEORITICAL PRACTICAL
1. Frequency
2. I/P time period
3. O/P time period
4. I/P Amplitude
5. O/P Amplitude

PROCEDURE:

Integrator:
2. Apply the square or sine input signal at high frequency using AFO.
3. Note the corresponding output waveforms and plot the graph.

Differentiator:
2. Apply the square or sine input signal at low frequency using AFO.
3. Note the corresponding output waveforms and plot the graph.


16
Active Filter LPF, HPF,BPF
EX.NO: 3
DATE:
AIM:
To design and obtain the frequency response of
i) First order Low Pass Filter (LPF)
ii) First order High Pass Filter (HPF)
iii) Band pass filter
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 IC 741 1
2 Resistors
Variable Resistor
10k ohm

20k pot
3
1
3 Capacitors 0.01f 1
4 Cathode Ray Oscilloscope (0 20MHz) 1
5 Regulated Power supply (0 30V),1A 1
6 Function Generator (1Hz 1MHz) 1

THEORY:
a) LPF:
A LPF allows frequencies from 0 to higher cut of frequency, f
H
. At f
H
the gain is 0.707
A
max
, and after f
H
gain decreases at a constant rate with an increase in frequency. The gain
decreases 20dB each time the frequency is increased by 10. Hence the rate at which the gain
rolls off after f
H
is 20dB/decade or 6 dB/ octave, where octave signifies a two fold increase in
frequency. The frequency f=f
H
is called the cut off frequency because the gain of the filter at this

17
frequency is down by 3 dB from 0 Hz. Other equivalent terms for cut-off frequency are -3dB
frequency, break frequency, or corner frequency.
b) HPF:
The frequency at which the magnitude of the gain is 0.707 times the maximum value of
gain is called low cut off frequency. Obviously, all frequencies higher than f
L
are pass band
frequencies with the highest frequency determined by the closed loop band width all of the op-
amp.
c) BAND PASS FILTER:
A band pass filter has a pass band between two cutoff frequencies f
H
and f
L
such that f
H
>
f
L
. Any input frequency outside this pass band is attenuated. There are two types of band-pass
filters. Wide band pass and Narrow band pass filters. We can define a filter as wide band pass if
its quality factor Q <10. If Q>10, then we call the filter a narrow band pass filter. A wide band
pass filter can be formed by simply cascading high-pass and low-pass sections. The order of
band pass filter depends on the order of high pass and low pass sections.
CIRCUIT DIAGRAM:

Fig 1: Low pass filter

18

Fig 2: High pass filter

Fig 3:Wide band pass filter
DESIGN:
First Order LPF: To design a Low Pass Filter for higher cut off frequency f
H
= 4 KHz and pass
band gain of 2
f
H
= 1/( 2RC )
Assuming C=0.01 F, the value of R is found from
R= 1/(2f
H
C) =3.97K

19
The pass band gain of LPF is given by A
F
= 1+ (R
F
/R
1
)= 2
Assuming R
1
=10 K, the value of R
F
is found from
R
F
=( A
F
-1) R
1
=10K
First Order HPF: To design a High Pass Filter for lower cut off frequency f
L
= 4 KHz and
pass band gain of 2
f
L
= 1/( 2RC )
Assuming C=0.01 F,the value of R is found from
R= 1/(2f
L
C) =3.97K
The pass band gain of HPF is given by A
F
= 1+ (R
F
/R
1
)= 2
Assuming R
1
=10 K, the value of R
F
is found from
R
F
=( A
F
-1) R
1
=10K
Band pass filter: To design a band pass filter having f
H
= 4KHz and f
L
= 400Hz and pass
band gain of 2.
As shown in Fig ,the first section consisting of Op Amp,R
F
,R
1
,R and C is the high pass filter and
second consisting of low pass filter. The design of low pass and high pass filters.
Low Pass Filter Design:
Assuming C=0.01f, the value of R is found from
R = 1/(2f
H
C) =3.97K
The pass band gain of LPF is given by A
LPF
= 1+ (R
F
/ R
1
)=2
Assuming R
1
=5.6 K, the value of R
F
is found from R
F
=( A
F
-1) R
1
=5.6K


20
High Pass Filter Design:
Assuming C=0.01f, the value of R is found from
R = 1/(2f
L
C) =39.7K
The pass band gain of HPF is given by A
HPF
= 1+ (R
F
/ R
1
)=2
Assuming R
1
=5.6 K, the value of R
F
is found from
R
F
= ( A
F
-1) R
1
=5.6K
Model graphs :

Frequency response characteristics of LPF Frequency response characteristics of HPF

Band pass filter
TABULAR FORM :

21
a)LPF
Input voltage V
in
= 0.5V

b)HPF

Frequency O/P Voltage(V) Voltage
Gain Vo/Vi
Gain indB

Frequency O/P Voltage(V) Voltage
Gain Vo/Vi
Gain indB


22

C)Bandpass filter

PROCEDURE:
First Order LPF
1. Connections are made as per the circuit diagram
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into
saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown in Table
4. Plot the frequency response
First Order HPF
1. Connections are made as per the circuit diagrams
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into
saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown in Table

Frequeny O/P Voltage Vo(V) Gain Vo/Vi Gain indB


23

Band pass filter:
1. Connect the circuit as per the circuit diagram shown in Fig
2. Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go into
saturation (depending on gain).
3. Vary the input frequency from 100 Hz to 100 KHz and note down the output amplitude at
each step as shown in Table.

Viva questions and answers:
1. What is the relation between f
C
& f
H
, f
L
?

L H C
f f f =

2. How do you increase the gain of the wideband pass filter?
By increasing the gain of either LPF or HPF
3. What is the difference between active and passive filters?
Active filters use Op Amp as active element, and resistors and capacitors as the passive
elements.
4. What is the effect of order of the filter on frequency response characteristics?
Each increase in order will produce -20 dB/decade additional increases in roll off rate.
5 .What modifications in circuit diagrams require to change the order of the filter?
Order of the filter is changed by RC network.


24

SQUARE WAVE GENERATOR-ASTABLE MULTIVIBRATOR
EX.NO: 4
DATE:
AIM:
To design a square wave generator circuit for the frequency of Oscillations of 1KHZ
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 OP-AMP IC741 1
2 Resistor 4.7KO,
1KO
1.16KO

1
1
1
3 Capacitor 0.1F 1
4 CRO - 1
5 RPS DUAL(0-30) V 1

THEORY:
A simple op-Amp square wave generator is also called as free running oscillator, the
principle of generation of square wave output is to force an op-amp to operate in the saturation
region . A fraction |=R2/(R1+R2) of the output is fed back to the (+) input terminal. The output
is also fed to the (-) terminal after integrating by means of a low pass Rc combination in astable
multivibrator both the states are quasistables. The frequency is determined by the time taken by
the capacitor to charge from- |Vsat to+|Vsat.
DESIGN:

25
F=1KHZ =T=1ms
R2=1KO,C=0.1F
R1=1.16R2=1.16KO~1KO+100O
T=2RC
R=T/2C =5KO
~4.7KO
CIRCUIT DIAGRAM:

MODEL GRAPH
+ Vcc
+Vsat
|Vsat

- |Vsat
-Vsat
- Vee

26
PROCEDURE:
1. The connection is given as per the circuit diagram
2. Connect the CRO in the output and trace the square waveform.
3. Calculate the practical frequency and compare with the theoretical Frequency.
4. Plot the waveform obtained and mark the frequency and time period.


27

MONOSTABLE MULTIVIBRATOR USING IC 741
EX.NO: 5
DATE:
AIM:
To construct monostable mutivibrator using IC741
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 Regulated variable Power Supply

(0-30)V 2
2 Function generator

1MHz 1
3 CRO

30MHz 1
4 Resistors

15K,10K Each two
5 Capacitor

0.1F 2
6 Op-amp

IC 741 1
7 Diode

BY 127 2
8 Bread board

- 1
9 Connecting wires

- As required

DESIGN CALCULATION
V
cc
= 10V,V
sat
= 10V,pulse width T= 1ms
1. To find R
1
and R
2

= 0.86 choose R
1
= 10K
=


28
Assume R
1
= R
2
, = 0.5
2. To find charging period of capacitor
T = R * C (
)
We know that
V
t
= V
sat
*
where V
sat
= 12V and substitute V
t
in T , we get
T = R * C (
) take R
2
= R
1

T = 0.69 R * C
Choose T = 1 ms,C = 0.1F
Find out the value of R

THEORY
It is also known as one shot multivibrator. It generates a single pulse of specified duration
in response to each external trigger signal. A monostable multivibrator exits only one stable
state. Application of a trigger causes a change to the quasistable state. The circuit remains in a
quasistable state for a fixed interval of time and then reverts to its original stable state. An
internal trigger signal is generated which produces the transition to the stable state. Usually, the
charging and discharging of a capacitor provides this internal trigger signal.

29
CIRCUIT DIAGRAM

PROCEDURE
1. Connect the circuit as per the circuit diagram
2. Switch on the power supply and apply trigger pulse at the second pin of op-amp
3. Measure the output waveform in the CRO
4. Measure the voltage across the capacitor, an exponentially rising and falling wave
between 5V and 10V is noted.

0
0
0
0
0
R4
3.3k
R3
10k
R2
12k
R1
1k
C2
0.1u
C1
0.1u
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
V2
12v
V1
12v
C
L
K
DSTM1
D3
D1N4007
D2
D1N4007
D1
D1N4007
R5
10k

30
IC 555 TIMER-MONOSTABLE OPERATION CIRCUIT
EX.NO: 6
DATE:
AIM:
To generate a pulse using Monostable Multivibrator by using IC555
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 555 IC 1
2 Capacitors 0.1f,0.01f Each one
3 Resistor 10k 1
5 Function Generator (1HZ 1MHz) 1
6 Cathode ray oscilloscope (0 20MHz) 1

THEORY:
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating
circuit in which the duration of the pulse is determined by the RC network connected externally
to the 555 timer. In a stable or stand by mode the output of the circuit is approximately Zero or
at logic-low level. When an external trigger pulse is obtained, the output is forced to go high ( ~
V
CC
). The time for which the output remains high is determined by the external RC network
connected to the timer. At the end of the timing interval, the output automatically reverts back to
its logic-low stable state. The output stays low until the trigger pulse is again applied. Then the
cycle repeats. The Monostable circuit has only one stable state (output low), hence the name
monostable. Normally the output of the Monostable Multivibrator is low.

31
CIRCUIT DIAGRAM:

Fig 1: Monostable Circuit using IC555
DESIGN:
Consider V
CC
= 5V, for given t
p

Output pulse width t
p
= 1.1 R
A
C
Assume C in the order of microfarads & Find R
A
Typical values:
If C=0.1 F , R
A
= 10k

then

t
p
= 1.1 mSec

Trigger Voltage =4 V


32
WAVEFORMS:

Fig (a): Trigger signal
(b): Output Voltage
(c): Capacitor Voltage
Sample Readings:

Trigger Output wave Capacitor output


33

PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
3. Observe the output waveform and measure the pulse duration.
4. Theoretically calculate the pulse duration as T
high
=1.1. R
A
C


34

IC 555 TIMER - ASTABLE OPERATION CIRCUIT
EX.NO: 7
DATE:
AIM:
To generate unsymmetrical square and symmetrical square waveforms using
IC555.
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 IC 555 1
2 Resistors 3.6k,7.2K Each one
3 Capacitors 0.1f,0.01f Each one
4 Diode OA79 1

THEORY:
When the power supply V
CC
is connected, the external timing capacitor C charges
towards V
CC
with a time constant (R
A
+R
B
) C. During this time, pin 3 is high (V
CC
) as Reset
R=0, Set S=1 and this combination makes Q =0 which has unclamped the timing capacitor C.
When the capacitor voltage equals 2/3 V
CC
, the upper comparator triggers the control flip
flop on that Q =1. It makes Q1 ON and capacitor C starts discharging towards ground through

35
R
B
and transistor Q1 with a time constant R
B
C. Current also flows into Q1 through R
A
.
Resistors R
A
and R
B
must be large enough to limit this current and prevent damage to the
discharge transistor Q1. The minimum value of R
A
is approximately equal to V
CC
/0.2 where
0.2A is the maximum current through the ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches V
CC
/3, the lower comparator
is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0 unclamps the external
timing capacitor C. The capacitor C is thus periodically charged and discharged between 2/3
V
CC
and 1/3 V
CC
respectively. The length of time that the output remains HIGH is the time for
the capacitor to charge from 1/3 V
CC
to 2/3 V
CC
.
The capacitor voltage for a low pass RC circuit subjected to a step input of V
CC
volts is
given by V
C
= V
CC
[1- exp (-t/RC)]
Total time period T = 0.69 (R
A
+ 2 R
B
) C
f= 1/T = 1.44/ (R
A
+ 2R
B
) C
CIRCUIT DIAGRAM:

Fig. 555 Astable Circuit
DESIGN:
Formulae: f= 1/T = 1.44/ (R
A
+2R
B
) C

36
Duty cycle (D) = t
c
/T = R
A
+ R
B
/(R
A
+2R
B
)

MODEL CALCULATIONS:
Given f=1 KHz. Assuming c=0.1F and D=0.25
1 KHz = 1.44/ (RA+2R
B
) x 0.1x10
-6
and 0.25 =( R
A
+R
B
)/ (R
A
+2R
B
)
Solving both the above equations, we obtain R
A
& R
B
as
R
A
= 7.2K
R
B
= 3.6K
WAVEFORMS:

Fig (a): Unsymmetrical square wave output
(b): Capacitor voltage of Unsymmetrical square wave output
(c): Symmetrical square wave output


37
TABULATION
Parameter Unsymmetrical Symmetrical
Voltage V
PP

Time period T
Duty cycle

PROCEDURE:
I) Unsymmetrical Square wave
1. Connect the circuit as per the circuit diagram shown without connecting the diode OA
79.
2. Observe and note down the waveform at pin 6 and across timing capacitor.
3. Measure the frequency of oscillations and duty cycle and then compare with the given
values.
4. Sketch both the waveforms to the same time scale.
II) Symmetrical square waveform generator:
1. Connect the diode OA79 as shown in Figure to get D=0.5 or 50%.
2. Choose R
a
=R
b
= 10K and C=0.1f
3. Observe the output waveform, measure frequency of oscillations and the duty cycle and
then sketch the o/p waveform.


38
SCHMITT TRIGGER CIRCUITS- USING IC 741 & IC 555
EX.NO: 8
DATE:
AIM:
To design the Schmitt trigger circuit using IC 741 and IC 555
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 IC 741 1
2 555IC 1
4 Multimeter 1
5 Resistors 100
56 K
2
1
6 Capacitors 0.1 f, 0.01 f Each one
7 Regulated power supply (0 -30V),1A 1

THEORY:
The circuit shows an inverting comparator with positive feed back. This circuit converts
orbitrary wave forms to a square wave or pulse. The circuit is known as the Schmitt trigger (or)
squaring circuit. The input voltage V
in
changes the state of the output V
o
every time it exceeds
certain voltage levels called the upper threshold voltage V
ut
and lower threshold voltage V
lt
.

39
When V
o
= - V
sat
, the voltage across R
1
is referred to as lower threshold voltage, V
lt
.
When V
o
=+V
sat
, the voltage across R
1
is referred to as upper threshold voltage V
ut
.The
comparator with positive feed back is said to exhibit hysterisis, a dead band condition.
CIRCUIT DIAGRAM:

Fig 1: Schmitt trigger circuit using IC 741

Fig 2: Schmitt trigger circuit using IC 555


40
DESIGN:
V
utp
= [R
1
/(R
1
+R
2
)](+V
sat
)
V
ltp
= [R
1
/(R
1
+R
2
)](-V
sat
)
V
hy
= V
utp
V
ltp

=[R
1
/(R
1
+R
2
)] [+V
sat
(-V
sat
)]
WAVE FORMS:

Fig1 : (a) Schmitt trigger input wave form
(b) Schmitt trigger output wave form


41
TABULATION:
Table 1:
Parameter Input Output
741 555 741 555
Voltage( V
p-p
)
Time period(ms)

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Apply an orbitrary waveform (sine/triangular) of peak voltage greater than UTP to the input of a
Schmitt trigger.
3. Observe the output at pin6 of the IC 741 and at pin3 of IC 555 Schmitt trigger circuit by varying
the input and note down the readings as shown in Table
4. Find the upper and lower threshold voltages (V
utp
, V
Ltp
) from the output wave form.


42
RC PHASE SHIFT OSCILLATOR
EX.NO: 9
DATE:
AIM:
To construct a RC phase shift oscillator to generate sine wave using op-amp.
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 OP-AMP IC-741 1
2 Resistor 16KO, 32KO,
1.59KO,
1
2
3 Capacitor 0.1f

2

4 CRO - 1

THEORY:
Basically,positive feedback of a fraction of output voltage of a amplifier fed to the input
in the same phase, generate sine wave.The op-amp provides a phase shift of 180 degree as it is
used in the inverting mode.An additional phase shift of 180 degree is provided by the feedback
Rc network.The frequency of the oscillator f
o
is given by
f
o
= 1 / \ 6 (2 t R C )
Also the gain of the inverting op-amp ahould be atleast 29,or R
f
> 29 R
1


43

RC PHASE SHIFT OSCILLATOR

DESIGN:
f
o
= 1 / \ 6 (2 t R C )
R
f
> 29 R
1
C = 0.01F, fo = 500 Hz.
R

= 1 / \ 6 (2 t f C ) = 13 k
Therefore, Choose R = 15k
To prevent loading,
R1 > 10 R
R1 =10 R = 150 k.
CRO
R1=150k
Rf =470k
741
R = 1.5 k
C =0.01F
2
3

44
R
f
= 4.35 M
MODEL GRAPH:

Observations:

Time period =
Frequency =
Amplitude =
PROCEDURE:
1. Connect the circuit as shown in fig. With the design values.
2. Observe the output waveforms using a CRO.For obtaining sine wave adjust Rf.
3. Measure the output wave frequency and amplitude.

t
T

45

WEIN BRIDGE OSCILLATOR
EX.NO: 10
DATE:
AIM:
To construct a wein bridge oscillator for fo = 1KHz and study its operation
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 OP-AMP IC-741 1
2 Resistor 16KO, 32KO,
1.59KO,
1
2
3 Capacitor 0.1f

2

4 CRO - 1

THEORY:
In wein bridge oscillator, wein bridge circuit is connected between the amplifier input
terminals and output terminals. The bridge has a series rc network in one arm and parallel
network in the adjoining arm. In the remaining 2 arms of the bridge resistors R1and Rf are
connected. To maintain oscillations total phase shift around the circuit must be zero and loop
gain unity. First condition occurs only when the bridge is p balanced. Assuming that the resistors
and capacitors are equal in value, the resonant frequency of balanced bridge is given by
Fo = 0.159 / RC
DESIGN:
At the frequency the gain required for sustained oscillations is given by
1+Rf /R1 = 3 or Rf = 2R1

46
Fo = 0.65/RC and Rf = 2R1
CALCULATION:
Theoretical
Fr = 1/(2*3.14*R*C)
Practical:
F = 1/T
CIRCUIT DIAGRAM
PROCEDURE:
1. Connections are made as per the diagram.
2. R,C,R
1
,R
f
are calculated for the given value of f
o
using the design .
3. Output waveform is traced in the CRO.


47

FREQUENCY MULTIPLIER USING PLL
EX.NO: 11
DATE:
AIM:
To construct and study the operation of frequency multiplier using IC 565.
APPARATUS REQUIRED:

S.NO

DESCRIPTION

RANGE

QUANTITY
1 IC 565,IC 7490,2N2222 - 1
2 Resistors 20 KO, 2kO, 4.7kO,10kO 1
3 Capacitors 0.001 F
10 F
1 each
4 Function Generator (Digital) 1 Hz 2 MHz 1
5 C.R.O - 1
6 Dual Power Supply 0- 30 V 1

THEORY
In a frequency multiplier using PLL 565, a divided by N network is inserted between the
VCO output and the phase comparator input. Since the output of the comparator is locked to
the input frequency f
in
the VCO is running at a multiple of the input frequency. Therefore in
the locked state the VCO output frequency is given by,
f
0
= Nf
in


48

CIRCUIT DIAGRAM:

PROCEDURE:
1. The connections are given as per the circuit diagram.
2. The circuit uses a 4- bit binary counter 7490 used as a divide-by-5 circuit.
3. Measure the free running frequency of VCO at pin 4, with the input signal V
i
set equal to
zero. Compare it with the calculated value = 0.25 / (R
T
C
T
).
4. Now apply the input signal of 1 V
PP
square wave at 500 Hz to pin 2.
5. Vary the VCO frequency by adjusting the 20kO potentiometer till the PLL is
locked.Measure the output frequency.It should be 5 times the input frequency.
6. Repeat steps 4, 5 for input frequency of 1 kHz and 1.5 kHz.

Viva questions and answers
1. Mention the applications of PLL
Frequency multiplier
Frequency synthesizer
Frequency translation
Clock and data recovery
2. What is a voltage controlled oscillator?

1
2
3
1 9
5
4
7
8 10
2
3
2kohm
20kohm
+6v
10Mf
+6v
11
2 3 6 7 10
1
1
2N2222
10kohm
4.7kohm
-6v
0.01Mf
vin
VCO Output
Fo=5fin
565
7490
(%5)
RT
RT
RT
C1
0.001Mf
C

49
Voltage controlled oscillator is a free running multivibrator operating at a set frequency
called the free running frequency. This frequency can be shifted to either side by applying a dc
control voltage and the frequency deviation is proportional to the dc control voltage.
3. What are the applications of VCO?
VCO is used in FM, FSK, and tone generators, where the frequency needs to be
controlled by means of an input voltage called control voltage.
4. What is PLL?
PLL is a control system that generates an output signal whose phase is related to the
phase of input Reference signal.


50

VOLTAGE REGULATOR USING IC723
EX.NO: 12
DATE:
AIM:
To design a low voltage variable regulator of 2 to 7V using IC 723.
APPARATUS REQUIRED:
S.No Equipment/Component name Specifications/Value Quantity
1 IC 723

1
2 Resistors 3.3K,4.7K,
100
Each one
3 Variable Resistors 1K, 5.6K Each one
4 Regulated Power supply 0 -30 V,1A 1
5 Multimeter 3

digit display 1

THEORY:
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in
load current and input voltage variations. Using IC 723, we can design both low voltage and
high voltage regulators with adjustable voltages.
For a low voltage regulator, the output V
O
can be varied in the range of voltages V
o
<
V
ref
, where as for high voltage regulator, it is V
O
> V
ref
. The voltage V
ref
is generally about 7.5V.

51
Although voltage regulators can be designed using Op-amps, it is quicker and easier to use IC
voltage Regulators.
IC 723 is a general purpose regulator and is a 14-pin IC with internal short circuit current
limiting, thermal shutdown, current/voltage boosting etc. Furthermore it is an adjustable voltage
regulator which can be varied over both positive and negative voltage ranges. By simply varying
the connections made externally, we can operate the IC in the required mode of operation.
Typical performance parameters are line and load regulations which determine the precise
characteristics of a regulator. The pin configuration and specifications are described earlier
LM317 series is the most commonly used three terminal adjustable voltage regulators.
The power rating of such regulator by a factor of 10V more because of improved overload
protection greater load current can be drawn over the given operating temperature range.
CIRCUIT DIAGRAM:

Fig1: Voltage Regulator


52

DESIGN OF LOW VOLTAGE REGULATOR:
Assume I
o
= 1mA,V
R
=7.5V
R
B
= 3.3 K
For given V
o

R
1
= ( V
R
V
O
) / I
o

R
2
= V
O
/ I
o

PROCEDURE:
a) Line Regulation:
1. Connect the circuit as shown in Fig 1.
2. Obtain R
1
and R
2
for V
o
=5V

3. By varying V
n
from 2 to 10V, measure the output voltage V
o
.
4. Draw the graph between V
n
and V
o
as shown in model graph (a)
5. Repeat the above steps for V
o
=3V

b) Load Regulation: For V
o
=5V

1. Set V
i
such that V
O
= 5 V
2. By varying R
L
, measure I
L
and V
o

3. Plot the graph between I
L
and V
o
as shown in model graph (b)

53
4. Repeat above steps 1 to 3 for V
O
=3V.

TABULATION
S.NO INPUT VOLTAGE OUTPUT VOLTAGE

Model graphs:
a) Line Regulation: b) Load Regulation:

Viva Questions & Answers:

54
1. What is the effect of R
1
on the output voltage?
R
1
decreases for an increase in the output voltage.
2. What are the applications of voltage regulators?
Voltage regulators are used as control circuits in PWM, series type switch mode
supplies, regulated power supplies, voltage stabilizers.

3. What is the effect of V
i
on output?
Output varies linearly with input voltage up to some value (o/p voltage+dropout
voltage) and remains constant.
4. What is a linear voltage regulator?

Series or linear regulator uses a power transistor connected in series between the
Unregulated dc input and the load and it conducts in the linear region .The output voltage
is controlled by the continous voltage drop taking place across the series pass transistor.

5. What is a switching regulator?
Switching regulators are those which operate the power transistor as a
high frequency on/off switch, so that the power transistor does not conduct current
continously.This gives improved efficiency over series regulators.

6. What is the input voltage of LM 317, LM 723?
40 V
7. What is the output voltage of LM317, LM 723?
1.2V to 54V
2V to 57V

SIMULATION USING ORCAD

55
EX. NO: 13
DATE
AIM:
To simulate the circuit and analyse its characteristics
APPARATUS REQUIRED:

1.Personal computer with windows os.
2.PCB layout software such as ORCAD.
THEORY:
General rules for designing PCBs:
The PCB designer follows few rules of thumb that can be used when laying out PCBs.
Here they are,
1.PLACING COMPONENTS:
Generally, it is best to place parts only on the topside of the board. Firstly place all the
components in specific locations. This includes connectors, switches, LED mounting holes, heat
sinks or any other item that mounts to an external location.
Give careful thought when placing components to minimize trace lengths. Doing a good
job here will make laying the traces much easier.
Arrange ICs in only one or two orientations (up and down or right and left). Align each
IC so that pin 1 is in the same place for each orientation, usually on the top or left sides. Position
polarized parts with the positive leads, all having the same orientation. Also use a square pad to
mark the positive leads of these components.
Frequently, the beginners run out of room when routing traces. Leave 0.35 to 0.5 between
ICs. For large ICs allow even more space.
Parts not found in the component library can be made by placing a series of individual
pads and then group them together. Place one pad for each lead of the component. It is very
important to measure the pin spacing and pin diameters as accurately as possible.
After placing all the components, print out a copy of the layout. Place each component on
the top of the layout. Check to insure that you have allowed enough space for every part to rest
without touching each other.

56
2. PLACING POWER AND GROUND TRACES:
After the components are placed, the next step is to lay the power and ground traces.A
power rail is run along the front edge of the board and a ground rail along the rear edge.From
these rails attach traces that run in between the ICs. The ground rail should be very wide, 0.100
and all the supply lines should be 0.50. When using this configuration the remaining of the
bottom layer is then reserved for the vertical signal traces.
3. PLACING SIGNAL TRACES:
When placing traces, it is always a good practice to make them as short and direct as
possible. Use vias to move signals from one layer to the other. A via is a pad-through hole.
Generally the best strategy is to lay out a board with vertical trace on one side and horizontal
traces on the opposite side. A good trace width for low current digital and analog signals is
0.010.
Traces that carry significant current should be wider than signal traces. The table below gives
rough guidelines of how wide should a trace be for a given amount of current.

When routing traces, it is best to have the snap to grid turned on. Setting the snap grid spacing to
0.050 works well. Changing to a value of 0.025 can be helpful when trying to work as densely
as possible. Turning off the snap feature may be necessary when connecting to parts that have
unusual pin spacing.
It is a commo0n practice to restrict the direction that traces run to horizontal, vertical or
at 45 degrees angles.
When placing narrow traces, use 0.015 or less. Avoid sharp right angle turns. The
problem here is that , in the board manufacturing process the outside corner can be etched a little
more narrow. The solution is to use two 45-degree bends with a short leg in between.
0.010 0.3 Amps
0.015 0.4 Amps
0.020 0.7 Amps
0.025 1 Amps
0.050 2 Amps
0.100 4 Amps
-0.150 6 Amps

57
It is a good idea to place text on the top layer of the board, such as the product or
company name.
4.CHECKING YOUR WORK:
After all the traces are placed, it is best to double-check the routing of every signal to
verify that nothing is missing or incorrectly wired. Do this by running through the schematic, one
wire at a time. Carefully follow the path of each trace. After each trace is confirmed, mark the
signal on the schematic with a yellow highlighter.

CIRCUIT DIAGRAM:

Vin

Inspect the layout, both top and bottom to ensure that the gap between every item is 0.007 or
greater. Use the pad information tool to determine the diameters of pads that make up a
component.
Check for missing vias. The CAD software will automatically insert a via when changing
layers as a series of traces are placed. The user often forget that vias are not automatically
inserted otherwise. For example, when beginning a new trace, a via is to first print a top layer ,
then print the bottom. Visually inspect each side for traces that doesnt connect to anything.
When a missing via is found, insert one. Do this by clicking on the pad in the side tool bar from
the down list box and click on the layout.

58
Check for the traces that cross each other. Inspecting a printout of each layer easily does
this.
Metal components such as heat sinks, crystals, switches, batteries and connectors can
cause shorts, if they are placed over traces on the top layer. Inspect for these shorts by placing all
the metal components on a printout of the top layer. Then look for traces that run below the
metal components.
PROCEDURE FOR SIMULATION:
- Start---program---ORCAD RELEASE 9---CAPTURE CIS
- New---project---title create
- Drag the element as per the circuit requirement.
- Make connections as per circuit using right icon.
- Create the new simulation.
- Set the output level settings.
- Place the voltage marker in output node.
- Run the circuit diagram.
- Print the output waveform

CIRCUIT DIAGRAM:

59

ANALYSIS TYPE: TIME DOMAIN (TRANSIENT)
RUN TO TIME: 40ms
MODEL GRAPH

SIMULATION OUTPUT:
0 0
0
0
0
0
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
R1
92.8k
R2
3.2k
R3
326
R4
326
R5
326
R6
4k
C1
0.1u
C2
0.1u
C3
0.1u
V1
12v
V2
12v

60

ASTABLE MULTIVIBRATOR USING TIMER

SIMULATION RESULT
0
0
0
0
U1
555B
1
2
3 4
5
6
7
8
GND
TRIGGER
OUTPUT RESET
CONTROL
THRESHOLD
DISCHARGE
VCC
C1
0.01u
C2
0.01u
R1
14.41k
R2
43.41k
R3
1k
V1
5v

61

MONOSTABLE MULTIVIBRATOR USING TIMER

SIMULATION RESULT
0
0
0
0
0
V4
8V
V3
U2
555B
1
2
3 4
5
6
7
8
GND
TRIGGER
OUTPUT RESET
CONTROL
THRESHOLD
DISCHARGE
VCC
R5
1k
R4
50K
C3
0.1u
C2
0.01u

62

ASTABLE MULTIVIBRATOR USING OP-AMP

SIMULATION RESULT

63

MONOSTABLE MULTIVIBRATOR USING OP-AMP

SIMULATION RESULT
0
0
0
0
0
R4
3.3k
R3
10k
R2
12k
R1
1k
C2
0.1u
C1
0.1u
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
V2
12v
V1
12v
C
L
K
DSTM1
D3
D1N4007
D2
D1N4007
D1
D1N4007
R5
10k

64

WEIN BRIDGE OSCILLATOR

0
0
0
0
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
V1
12v
V2
12v
R2
1k
R3
1k
C1
0.01u
C2
0.01u
R4
1k
R5
1k

65
SIMULATION OUTPUT

INSTRUMENTATION AMPLIFIER

0
0
0
0
0
0
0
0
0
U2
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
V4
12V
V3
12V
V2
5v
V1
2v
U3
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
V5
12V
R4
10k
R3
10k
R1
10k
V8
12V
V7
12V
V6
12V
R7
10k
R6
10k
R5
10k
R8
500k

66
SIMULATION OUTPUT

ACTIVE LOW PASS FILTER

SIMULATION OUTPUT
0 0
0
0
0
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
V1
12v
V2
12v
R1
2k
R2
4k
R3
1k
R4
1k
C1
0.1u
C2
0.1u
V3

67

BANDPASS FILTER

SIMULATION OUTPUT
0 0
0
0
0
U1
AD741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
C1
0.01u
C2
0.01u
R1
11.9k
R2
4.7k
R3
11.9k
R4
95.5k
V1
V2
12V
V3
12v

68

REFERENCES

69
1. D.Roy Choudhury and Shail B.Jain, Linear Integrated Circuits, 2
nd
edition, New Age
International.
2. James M. Fiore, Operational Amplifiers and Linear Integrated Circuits: Theory and
Application, WEST.
3. Malvino, Electronic Principles, 6
th
edition, TMH
4. Ramakant A. Gayakwad, Operational and Linear Integrated Circuits,4
th
edition, PHI.
5. Roy Mancini, OPAMPs for Everyone, 2
nd
edition, Newnes.
6. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3
rd

edition, TMH.
7. William D. Stanley, Operational Amplifiers with Linear Integrated Circuits, 4
th
edition,
Pearson.

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5124-SARASWATHI VELU COLLEGE OF ENGINEERING

ELECTRONICS AND COMMUNICATION ENGINEERING

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