PROCEDURE TO CODE A DESIGN AND VERIFY THE RESULT USING XILINX ISE SIMULATOR WITH SPARTAN3 FPGA/COLD Implement

t!"n#

Step$%
F!le New Project Enter the Project Name Top level Source type: HDL Click Next

Step&%
Ne' P(")e*t W!+ (, - P(")e*t P("pe(t!e. window open Select the De/!*e and the De.!0n 1l"' !or the Project: P(",2*t C te0"(3 F m!l3 De/!*e P *4 0e Spee, S3nt5e.!. T""l S!m2l t"( Click Next Ne' P(")e*t W!+ (, 2C(e te Ne' S"2(*e 3indow open Click on New Source Select VHDL M",2le and enter the !ile name4 ee that "dd to Project i elected4 Click Next New Source 3i5ard 2 De i/n module window open Enter the port name and elect the direction appropriately Click Next F!n!.5 Ne6t Ne6t F!n!.57 % % % % % % % "ll Spartan# $C#S%&& 'T%() *+ $ST ,-HDL.-erilo/0 1SE Simulator ,-HDL.-erilo/0

Step3%
To enter the lo/ic in the pro/ram6 click the mou e at the place where the lo/ic need to 7e entered4 8o to E,!t L n02 0e Templ te. U.e !n F!le S3nt5e.!. C"n.t(2*t. C",!n0 E6 mple. 88 Select the de i/n you are codin/4 "!ter election click E,!t Save the Pro/ram4

Step9% T" .3nt5e.!+e t5e De.!0n

Dou7le click C5e*4 S3nt 6 in S3nt5e.!+e - XST in Proce e window "!ter checkin/ yntax dou7le click S3nt5e.!+e - XST Dou7le click V!e' Te*5n"l"03 S*5em t!* to view the Schematic dia/ram o! the de i/n4

Step:% T" Implement t5e De.!0n

Dou7le click Implement De.!0n in Proce e window4

Step;% T" /!e' t5e ' /e 1"(m.7

Cl!*4 P(")e*t Ne' S"2(*e Ne' S"2(*e W!+ (, - Sele*t S"2(*e Type window open 4 Select Te.t <en*5 W /e1"(m and type the ource !ile name with =t>' at the end4 See that A,, t" p(")e*t ha 7een elected4 Click Ne6t Ne6t F!n!.57 In!t! l T!m!n0 n, Cl"*4 W!+ (, - In!t! l!+e T!m!n0 window open Set the timin/ a re9uired i! any clock i needed in the de i/n otherwi e no need o! any ettin/ 4 Click F!n!.57 Set the wave!orm a re9uired4 S /e and Cl".e the wave!orm window4 Select <e5 /!"( l .!m2l t!"n a S"2(*e. 1"( in ource window and click on the 7t>' !ile in ource window4 Now dou7le click S!m2l te <e5 /!"( l M",el in X!l!n6 ISE S!m2l t"( in proce e window to view the output wave!orm o! the de i/n4

Step?% T" ..!0n t5e p *4 0e p!n.%

Dou7le click A..!0n P *4 0e P!n. in : er Con traint in proce e window4 P(")e*t N /!0 t"( window open 4 Click Ye.7 X!l!n6 PACE window open 4 Select P *4 0e V!e'7 Select appropriate pin and enter them in the L"* !n ,e.!0n ">)e*t l!. -I/O p!n.7 Save the W!n,"' <2. Del!m!te( window open 4 Select XST ,e1 2lt6 click O@ and *l".e it4 1mplement the de i/n a/ain 7y dou7le clickin/ Implement De.!0n in Proce e window4

StepA%
Select P".tBR"2te S!m2l t!"n a S"2(*e. 1"( in ource window4 Select 7t>' !ile in ource window4 Dou7le click S!m2l te P".tBPl *e n, R"2te M",el in proce e window4 ISE .!m2l t"( window open 4 Click Ye.7

3ave!orm with delay appear on the window4

StepC% T" ,2mp t5e *",e "nt" t5e Sp (t n3 4!t%

Dou7le click Gene( te P("0( mm!n0 F!le in proce e window4 Dou7le click C"n1!02(e De/!*e D!MPACTE !MPACT window open 4 Select C"n1!02(e ,e/!*e 2.!n0 >"2n, (3B.* n DFTAGE and click F!n!.57 A..!0n ne' *"n1!02( t!"n 1!le window open 4 Select 7>!t !ile and click open4 'or the next ..!0n ne' *"n1!02( t!"n window click >3p ..7 ;i/ht click the XC3S&GG FPGA and click p("0( m7 P("0( mm!n0 p("pe(t!e. window open 4 Click O@7

P("0( m .2**ee,e,
"ppear on the creen and the lead on the partan# kit /low indicatin/ the ucce o! the de i/n4 Step$G% -eri!y the re ult 7y connectin/ the di/ital trainer kit to the pin elected4

EXPERIMENTB$ VHDL CODE COD FOR AND GATE AIM% To implement "ND /ate u in/ -HDL4 THEORY% The "ND /ate per!orm lo/ical multiplication6 more commonly known a "ND !unction4 "nd /ate can have any num7er o! input /reater than one4 The operation o! "ND /ate i uch that output i H18H only when all o! the input are H18H4 3hen any o! the input are L<3 the output i L<34 TRUTH TA<LE%

A G G $ $ <OOLEAN EXPRESSION% C="> RTL SCHEMATIC%

< G $ G $

C G G G $

CIRCUIT DIAGRAM%

VHDL CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity and/ate i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end and/ate? architecture >ehavioral o! and/ate i 7e/in cB= a and 7? end >ehavioral? TIMING WAVEFOMRS%

VHDL CODE FOR OR GATE AIM% To implement <; /ate u in/ $ilinx procedure4 THEORY% The <; /ate per!orm lo/ical addition6 more commonly known a <; !unction4 <; /ate can have any num7er o! input /reater than one4 The operation o! <; /ate i H18H only when any one o! the input are H18H4 TRUTH TA<LE% A G G $ $ <OOLEAN EXPRESSION% CHAI< RTL SCHEMATIC% < G $ G $ C G $ $ $ uch that output i

CIRCUIT DIAGRAM%

VHDL CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity or/ate i Port , a : in STD@L<81C? 7 : in STD@L<81C?

c : out STD@L<81C0? end or/ate? architecture >ehavioral o! or/ate i 7e/in c B= a or 7? end >ehavioral? TIMING WAVEFORM%

VHDL CODE COD FOR NAND GATE AIM% To implement N"ND /ate u in/ $ilinx procedure4 THEORY% The term N"ND i a contraction o! N<T*"ND N<T "ND and implie an "ND !unction with a complemented output4 1t i a univer al /ate4 the lo/ical operation o! N"ND /ate i TRUTH TA<LE% A G G $ $ <OOLEAN EXPRESSION% CHAJI>J DA<EJ CHAJI>JH RTL SCHEMATIC% < G $ G $ C $ $ $ G uch that a Low output occur only when all input are H18H4 when any o! the input are L<36 output will 7e H18H4

TECHNOLOGY SCHEMATIC%

VHDL CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity nand/ate i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end nand/ate? architecture >ehavioral o! or/ate i 7e/in c B= a nand 7? end >ehavioral? TIMING WAVEFORM%

VHDL CODE FOR NOR GATE AIM% To implement N<; /ate u in/ $ilinx procedure4 THEORY% The term N<; i a contraction o! N<T*<; and implie an <; !unction with a complemented output4 1t i a univer al /ate4 the lo/ical operation o! N<; /ate i H18H4 TRUTH TA<LE% A & & A A <OOLEAN EXPRESSION% CH DAI<EJHAJ<J RTL SCHEMATIC% < & A & A C A & & & uch that a Low output occur when any o! the input are H18H4 when all o! the input are L<36 output will 7e

TECHNOLOGY SCHEMATIC%

PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity nor/ate i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end nor/ate? architecture >ehavioral o! nor/ate i 7e/in c B= a nor 7? end >ehavioral? TIMING WAVEFORMK

VHDL CODE FOR XOR GATE AIM% To implement $<; /ate u in/ $ilinx procedure4 THEORY% 1t reco/ni5e only the word that have an odd num7er o! one 4 Thi mean that !or odd num7er o! one 6 output o! $<; /ate i H18H4 TRUTH TA<LE% A & & A A <OOLEAN EXPRESSION% CHAJ<IA<J RTL SCHEMATIC% < & A & A C & A A &

TECHNOLOGY SCHEMATIC%

PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity xor/ate i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end xor/ate? architecture >ehavioral o! xor/ate i 7e/in c B= a xor 7? end >ehavioral? TIMING WAVEFORM%

VHDL CODE FOR XNOR GATE AIM% To implement $N<; /ate u in/ $ilinx procedure4 THEORY% 1t reco/ni5e only the word that have an even num7er o! one .5ero 4 Thi mean that !or odd num7er o! one 6 output o! $N<; /ate i L<34 L<3 TRUTH TA<LE% A & & A A <OOLEAN EXPRESSION% CHA CHA<IAJ<J CIRCUIT DIAGRAM% < & A & A C A & & A

TIMING WAVEFORM%

PROGRAM CODE% Li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity xnor/ate i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end xnor/ate? architecture >ehavioral o! xnor/ate i 7e/in c B= a xnor 7? end >ehavioral?

VHDL CODE FOR NOT GATE AIM% To implement N<T /ate u in/ $ilinx procedure4 THEORY% The inverter ,N<T circuit0 per!orm a 7a ic lo/ic !unction called Cinver ionD or CcomplementationD4 The inverter chan/e one lo/ical level to it oppo ite level4 1n term o! 7it 6 it chan/e lo/icA to lo/ic & and lo/ic & to lo/icA4 TRUTH TA<LE% A & A < A &

<OOLEAN EXPRESSION% <HAJ RTL SCHEMATIC%

TECHNOLOGY SCHEMATIC%

PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity not/ate i Port , a : in STD@L<81C? 7 : out STD@L<81C0? end not/ate? architecture >ehavioral o! not/ate i 7e/in 7 B= not a? end >ehavioral? TIMING WAVEFORM%

;ES:LT: Hence reali5ation o! lo/ic /ate are imulated and veri!ied u in/ -HDL4

EXPERIMENTB& VHDL CODE FOR HALF ADDER AIM% To de i/n and imulate hal! adder u in/ -HDL4 TRUTH TA<LE% S2m & A A &

A & & A A

< & A & A

C ((3 & & & A

<OOLEAN EXPRESSION% S2mH ADIE< CIRCUIT DIAGRAM%

TIMING WAVEFORM%

PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity hal!adder i Port , a67 : in STD@L<81C? um6 carry : out STD@L<81C0? end hal!adder? architecture >ehavioral o! hal!adder i 7e/in proce ,a670 7e/in i! aB=E&E and 7B=E&E then umB=E&E? carryB=E&E? el i! aB=EAE and 7B=E&E then umB=EAE? carryB=E&E? el i! aB=E&E and 7B=EAE then umB=EAE? carryB=E&E? el e umB=E&E? carryB=EAE? end i!? end proce ? end >ehavioral? RESULT: Hence the hal! adder internal tructure i veri!ied u in/ -HDL4

EXPERIMENTB3 VHDL CODE FOR &69 DECODER AIM% To de i/n a %x+ decoder and to imulate in -HDL4 THEORY% " decoder i a com7inational circuit with multiple input6 multiple output lo/ic circuit that convert coded input to coded output 6 where the input are le er in num7er than output code 4 The input code i /enerally ha !ewer 7it than the output code6 there i one*to*one mappin/ !rom input code word into output code word 4 in a one*to*one mappin/6 each input code word produce a di!!erent output code word4 The /eneral tructure o! a decoder circuit can 7e hown a !ollow 4 The ena7le input 6 i! pre ent mu t 7e a erted !or the decoder to per!orm it normal mappin/ !unction4 <therwi e the decoder map all the input code word into a in/le di a7led output code word4 The corre pondin/ 1C num7er i F+A#G4 TRUTH TA<LE%

e G $ $ $ $

!G 6 G G $ $

!$ 6 G $ G $

1G G $ G G G

1$ G G $ G G

1& G G G $ G

13 G G G G $

PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity decoder%x+ i Port , x : in STD@L<81C@-ECT<; ,A downto &0? d : out STD@L<81C@-ECT<; ,# downto &00? end decoder%x+? architecture >ehavioral o! decoder%x+ i

7e/in proce ,x0 i 7e/in ca e x i when H&&H=I d B=HA&&&H? when H&AH=I d B=H&A&&H? when HA&H=I d B=H&&A&H? when other =I d B=H&&&AH? end ca e? end proce ? end 7ehavioral? TECHNOLOGY SCHEMATIC DIAGRAM FOR &69 DECODER%

SIMULATION FOR &69 DECODER%

RESULT: 2X4 Decoder internal structure is simulated and verified using VHDL.

EXPERIMENTB9 PROGRAM CODE% li7rary 1EEE?

VHDL CODE FOR DECODER 9X$; USING &X9

AIM% To de i/n a +$A) decoder u in/ %x+ decoder and to imulate in -HDL4

u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity decoder+xA) i Port , a676c6d6e : in STD@L<81C? y : out STD@L<81C@vector,A( downto &00? end decoder+xA)? architecture >ehavioral o! decoder+xA) i i/nal cA6c%6c#6c+: td@lo/ic? component decoderA) i port ,p696e: in td@lo/ic? dA6d%6d#6d+:out td@lo/ic0? end component? 7e/in PA: decoderA) port map,a676e6cA6c%6c#6c+0? P%: decoderA) port map,c6d6cA6y,&06y,A06y,%06y,#00? P#: decoderA) port map,cA6d6c%6y,+06y,(06y,)06y,F00? P+: decoderA) port map,c6d6c#6y,G06y,J06y,A&06y,AA00? P(: decoderA) port map,c6d6c+6y,A%06y,A#06y,A+06y,A(00? end >ehavioral? C"mp"nent ,e*l ( t!"n "1 De*",e($; li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity decoderA) i Port , p696e : in STD@L<81C? dA6d%6d#6d+ : out STD@L<81C0? end decoderA)? architecture >ehavioral o! decoderA) i 7e/in

dAB= ,,not p0 and ,not 90 and e0? d%B= ,,not p0 and ,90 and e0? d#B= ,p and ,not 90 and e0? d+B= ,p and 9 and e0? end >ehavioral? S!m2l t!"n (e.2lt "1 De*",e( 9X$;

TECHNOLOGY SCHEMATIC DIAGRAM FOR 9X$; DECODER%

RESULT: 4X16 MULTIPLEXER internal structure is simulated and verified using VHDL.

EXPERIMENTB: PROGRAM CODE%

VHDL CODE FOR A%$ MULTIPLEXER

AIM% To de i/n a G:A multiplexer and to imulate in -HDL4 li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity muxG i Port , i : in STD@L<81C@-ECT<; ,F downto &0? : in STD@L<81C@-ECT<; ,% downto &0? e : in STD@L<81C? o : out STD@L<81C0? end muxG? architecture >ehavioral o! muxG i 7e/in proce , 6i0 7e/in ca e i when H&&&H =I o B=i,&0? when H&&AH =I o B=i,A0? when H&A&H =I o B=i,%0? when H&AAH =I o B=i,#0? when HA&&H =I o B=i,+0? when HA&AH =I o B=i,(0? when HAA&H =I o B=i,)0? when HAAAH =I o B=i,F0? when other =I o B= i,&0? end ca e? end proce ? end >ehavioral?

SCHEMATIC DIAGRAM OF A%$ MULTIPLEXER%

TIMING DIAGRAM OF A%$ MULTIPLEXER%

RESULT: 8X1 MULTIPLEXER ULTIPLEXER internal structure is simulated and verified using VHDL.

EXPERIMENTB; PROGRAM CODE%

VHDL CODE FOR $;X$ MULTIPLEXER

AIM% To de i/n a A)xA multiplexer and to imulate in -HDL4 li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity muxA) i Port , i : in STD@L<81C@-ECT<; ,A( downto &0? : in STD@L<81C@-ECT<; ,# downto &0? e : in STD@L<81C? o : out STD@L<81C0? end muxA)? architecture >ehavioral o! muxA) i 7e/in proce , 6i0 7e/in i! e=EAE then ca e i when H&&&&H =I o B=i,&0? when H&&&AH =I o B=i,A0? when H&&A&H =I o B=i,%0? when H&&AAH =I o B=i,#0? when H&A&&H =I o B=i,+0? when H&A&AH =I o B=i,(0? when H&AA&H =I o B=i,)0? when H&AAAH =I o B=i,F0? when HA&&&H =I o B=i,G0? when HA&&AH =I o B=i,J0? when HA&A&H =I o B=i,A&0? when HA&AAH =I o B=i,AA0? when HAA&&H =I o B=i,A%0? when HAA&AH =I o B=i,A#0? when HAAA&H =I o B=i,A+0?

when HAAAAH =I o B=i,A(0? when other =I o B= i,&0? end ca e? end i!? end proce ? end >ehavioral? TECHNOLOGY SCHEMATIC FOR $;X$ MULTIPLEXER%

SIMULATION FOR $;X$ MULTIPLEXER%

RESULT: 16X1 MULTIPLEXER internal structure is simulated and verified using VHDL.

EXPERIMENTB? PROGRAM CODE% li7rary 1EEE?

VHDL CODE FOR PRIORITY ENCODER

AIM% To de i/n a priority encoder and to imulate in -HDL4

u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity priorityencoder i port , el : in td@lo/ic@vector ,F downto &0? code :out td@lo/ic@vector ,% downto &00? end priorityencoder? architecture >ehavioral o! priorityencoder i 7e/in code B= H&&&H when el,&0 = EAE el e H&&AH when el,A0 = EAE el e H&A&H when el,%0 = EAE el e H&AAH when el,#0 = EAE el e HA&&H when el,+0 = EAE el e HA&AH when el,(0 = EAE el e HAA&H when el,)0 = EAE el e HAAAH when el,F0 = EAE el e H***H? end >ehavioral?

TECHNOLOGY SCHEMATIC DIAGRAM FOR 9X$; DECODER%

SIMULATOIN RESULTS OF PRIORITY ENCODER%

Re.2lt% Hence priority encoder output i veri!ied u in/ -HDL4

EXPERIMENTBA VHDL CODE FOR DBFLIP FLOP AIM% To implement Cne/ative ed/eD D !ilp !lop u in/ xilinx procedure4 THEORY% <ne way to eliminate the unde ira7le condition o! the indetermined tate in the ;S*!! i to en ure that input SK; are never e9ual to A at the ame time4thi i done in the D*!!4the D*!! ha only two input :D and CLL4the input /oe directly to the S input and it complement to the ; input a lon/ a the CLL input i at &4the input i ampled when CLL=A4i! D i A6the M output /oe to A6placin/ the circuit in the et tate41! D i &6the output M /oe to & and the circuit witche to the clear tate4 The D*!! receive the de i/nation !rom it a7ility to hold data into it internal tora/e4thi type o! !lip!lop i ometime called a /ated d*latch4the CLL input i o!ten /iven the de i/nation /ate to indicate that thi input ena7le the /ated latch to make po i7le data entry into circuit4the 7inary in!ormation pre ent at the data input o! the D*!! i tran !erred to the M output when the CLL input i ena7led4the output !ollow the data input a lon/ a the pul e remain in it A tate4when the pul e /oe to & the 7inary in!ormation that wa pre ent in the data input at the time the pul e tran ition occurred it retained at the M output until the pul e input i ena7led a/ain4 The truth ta7le how that the M,tNA0 o! the !lip !lop i independent o! the pre nt tate ince M,tNA0 i e9ual to input D whether M i e9ual to & or A4 PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity ne/ative d!! i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end ne/ative d!!? architecture >ehavioral o! ne/ative d!! i 7e/in proce ,a0 7e/in i! aEevent and a=E&E then c B= 7? end i!? end proce ?

end >ehavioral? CIRCUIT DIAGRAM%

TIMING WAVEFORM%

AIM% To implement Cpo itive ed/eD D !lip !lop u in/ -HDL4 PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity Po itive d!! i Port , a : in STD@L<81C? 7 : in STD@L<81C? c : out STD@L<81C0? end Po itive d!!? architecture >ehavioral o! Po itive d!! i 7e/in proce ,a0 7e/in i! aEevent and a=EAE then c B= 7? end i!? end proce ? end >ehavioral? CIRCUIT DIAGRAM%

TIMING WAVEFORM%

AIM% To de i/n and implement D !ilp !lop u in/ -HDL4 PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity d!! i Port , clk6d : in STD@L<81C? 9 : out STD@L<81C0? end d!!? architecture >ehavioral o! d!! i 7e/in proce ,clk0 7e/in i! ,clkEevent and clk=EAE0 then 9B=d? end i!? end proce ? end >ehavioral? TECHNOLOGY SCHEMATIC DIAGRAM FOR D FLIP FLOP%

SIMULATION RESULTS OF D FLIP FLOP

EXPERIMENTBC VHDL CODE FOR F@ FLIPBFLOP L TB FLIPBFLOP AIM% To de i/n and implement O*L !ilp !lop u in/ -HDL4 PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity jk!! i Port , clk6re et6j6k : in STD@L<81C? 9 : 7u!!er td@lo/ic0? end jk!!? architecture >ehavioral o! jk!! i 7e/in proce ,clk6 re et0 7e/in i! ,re et = EAE0 then 9B=E&E? el i! ,clkEevent and clk=EAE0 then i! , j=E&E and k=E&E0 then 9B=9? el i! ,j=E&E and k=EAE0 then 9B=E&E? el i! ,j=EAE and k=E&E0 then 9B=EAE? el i! ,j=EAE and kB=EAE0 then 9B= not 9? end i!? end i!? end proce ? end >ehavioral? TECHNOLOGY SCHEMATIC DIAGRAM FOR FB@ FLIP FLOP%

AIM% To de i/n and implement T* !lip !lop u in/ -HDL4 PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity t!! i port ,t: in 7it? clk: in td@lo/ic? 9: 7u!!er 7it0? end t!!? architecture 7ehavioural o! t!! i 7e/in proce ,clk0 7e/in i! ,clkEevent and clk=EAE0 then i! , t=E&E0 then 9B=9? el i! ,t=EAE0 then 9B=,not 90? end i!? end i!? end proce ? end 7ehavioural? TECHNOLOGY SCHEMATIC DIAGRAM FOR TBFLIP FLOP%

RESULT% Hence the output o! OL6D and T 'lip !lop are veri!ied u in/ -HDL

EXPERIMENTB$G VHDL CODE FOR DECADE COUNTER AIM% To de i/n a decade counter and to imulate in -HDL4 THEORY% " ,modulo*A&0 decade counter i one that count num7er !rom & to J4thi can 7e con tructed !rom a modulo*A) counter 7y re ettin/ the counter at the A&th pul e4 1t i hown in 7elow ta7le4we ee that each 7inary num7er i uni9ue and it uni9uene can 7e u ed !or re ettin/ the counter at the de ired level4 thi i illu trated 7elow con ider the M column o! ta7le re ettin/ o! the counter at any de ired level i done 7y takin/ output !rom the !lip!lop terminal noted in the ta7le6 and u e them to drive a uita7le N"ND /ate !or clearin/4 Thu !or the modulo*A& decade counter we connect output terminal D and > to a N"ND /ate and connect the output o! the N"ND /ate to the CL; terminal o! all the T*''P TRUTH TA<LE% CL@ ;ST,A0 A % # + ( ) F G J A& PROGRAM CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity decadecounter i Port , r t : in STD@L<81C? clk : in STD@L<81C? 9out : out STD@L<81C@-ECT<; ,# downto &00? end decadecounter? M &&&& &&&A &&A& &&AA &A&& &A&A &AA& &AAA A&&& A&&A &&&&

architecture >ehavioral o! decadecounter decadeco i i/nal 9: td@lo/ic@vector,# downto &0? 7e/in proce ,clk6 r t0 7e/in i!,r t=EAE or cnt=HA&A&H0then 9B=H&&&&H? el e i!,clk=EAE and clkEevent0then i!,9=DA&&AD0then 9B=D&&&&D? el e 9B=9NA? end i!? end i!? end i!? end proce ? 9outB=9? end >ehavioral? CIRCUIT DIAGRAM%

SIMULATION RESULTS FOR DECADE COUNTER%

RESULT% Decade counter out put i veri!ied and imulated u in/ -HDL4

EXPERIMENTB$$ VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER AIM% To de i/n a erial in erial out hi!t re/i ter imulate in -HDL4 THEORY% Shi!t re/i ter are u ed in di/ital y tem !or temporary in!ormation tora/e and !or data manipulation or tran !er there are two way to hi!t data into re/i ter i4e46 erial or parallel6 and imilarly two way o! hi!t data out o! re/i ter4 1n thi type o! hi!t re/i ter6 data i tored into the re/i ter one 7it at a time, erial0 and taken out erially 4they delay data 7y one clock time !or each ta/e they will tore a 7it o! data !or each re/i ter4 " erial in erial out hi!t re/i ter may 7e A to )+ 7it in len/th6 lon/er i! re/i ter or packa/e are ca caded4 TRUTH TA<LE% .! $ & A & A VHDL CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity hi!tre/i ter i Port , clk : in STD@L<81C? r t : in STD@L<81C? i : in STD@L<81C? p : out STD@L<81C@-ECT<; ,# downto &0? out : out STD@L<81C0? end hi!tre/i ter? architecture i o o! hi!tre/i ter i i/nal 9: td@lo/ic@vector,# downto &0? 7e/in proce ,r t6clk0 7e/in *l4 rt A % # + N &&&& &&&& A&&& &A&& A&A& ."2t $ & & & &

i!,r t=EAE0then 9B=H&&&&H? el e i!,clkEevent and clk=EAE0 then 9,#0B= i? 9,%0B=9,#0? 9,A0B=9,%0? 9,&0B=9,A0? outB=9,&0? end i!? end i!? end proce ? pB=9? end i o? TECHNOLOGY SCHEMATIC%

SIMULATION RESULTS%

VHDL CODE FOR SERIAL IN PARALLEL OUT SHIFT REGISTER AIM% To de i/n a erial in parallel out hi!t re/i ter and to imulate in -HDL and veri!y experimentally in di/ital 1C La74 THEORY% hi!t re/i ter are u ed in di/ital y tem !or temporary in!ormation tora/e and !or data manipulation or tran !er there are two way to hi!t data into re/i ter i4e46 erial or parallel6 and imilarly two way o! hi!t data out o! re/i ter4 1n thi type o! hi!t re/i ter6 data i tored into the re/i ter one 7it at a time, erial0 and taken out in parallel it make all the internal ta/e availa7le a output 4 1! !our 7it are hi!ted in 7y !our clock pul e via a in/le wire 6the data 7ecome availa7le imultaneou ly on !our output 4 TRUTH TA<LE% .! $ & A & A VHDL CODE% li7rary 1EEE? u e 1EEE4STD@L<81C@AA)+4"LL? u e 1EEE4STD@L<81C@";1TH4"LL? u e 1EEE4STD@L<81C@:NS18NED4"LL? entity hi!tre/i ter i Port , clk : in STD@L<81C? r t : in STD@L<81C? i : in STD@L<81C? pout : out STD@L<81C@-ECT<; ,# downto &0? end hi!tre/i ter? architecture i o o! hi!tre/i ter i i/nal 9: td@lo/ic@vector,# downto &0? 7e/in proce ,r t6clk0 7e/in i!,r t=EAE0then 9B=H&&&&H? el e i!,clkEevent and clk=EAE0 then *l4 rt A % # + p"2t &&&& &&&& A&&& &A&& A&A&

9,#0B= i? 9,%0B=9,#0? 9,A0B=9,%0? 9,&0B=9,A0? end i!? end i!? end proce ? poutB=9? end i o?

TECHNOLOGY SCHEMATIC%

SIMULATION RESULTS%

VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER AIM% To de i/n a erial in erial out hi!t re/i ter and to imulate in -HDL4 VHDL CODE% li7rary ieee? u e ieee4 td@lo/ic@AA)+4all? u e ieee4 td@lo/ic@arith4all? entity pi o i /eneric,x : inte/er := G0? port, din: in td@lo/ic@vector,x*A downto &0? clk6ld6r6dir@r6 e: in td@lo/ic? o: out td@lo/ic 0? end pi o? architecture rtl o! pi o i i/nal pre@9 : td@lo/ic@vector,,x*A0 downto &0 := ,other =I ExE0? 7e/in hi!t@re/i ter@proce : proce ,clk6r0 7e/in i! ,r = EAE0 then pre@9 B= ,other =I E&E0? el i! ,clkEevent and ,clk = EAE0 and ,clkEla t@value = E&E00 then i! ,ld = EAE0 then pre@9 B= din? el i! , e = EAE0 and ,dir@r = EAE0 then pre@9,x*A0 B= E&E? pre@9,,x*%0 downto &0 B= pre@9,,x*A0 downto A0? el i! , e = EAE0 and ,dir@r = E&E0 then pre@9,,x*A0 downto A0 B= pre@9,,x*%0 downto &0? pre@9,&0 B= E&E? end i!? end i!? end proce hi!t@re/i ter@proce ? o B= pre@9,&0 when dir@r = EAE el e pre@9,x*A0 when dir@r = E&E el e ExE? end rtl?

TECHNOLOGY OGY SCHEMATIC%

SIMULATION RESULTS%

VHDL CODE FOR SERIAL/PARALLEL IN SERIAL/PARALLEL OUT SHIFT REGISTER

AIM% To de i/n a erial.parallel in erial.parallel out hi!t re/i ter and to imulate in -HDL4 VHDL CODE% li7rary ieee? u e ieee4 td@lo/ic@AA)+4all? u e ieee4 td@lo/ic@arith4all? entity pi po i /eneric,x : inte/er := G0? port, din: in td@lo/ic@vector,,x*A0 downto &0? dout: out td@lo/ic@vector,,x*A0 downto &0? clk6ld6r6dir@r6 e6 i: in td@lo/ic? o: out td@lo/ic 0? end pi po? architecture rtl o! pi po i i/nal pre@9 : td@ulo/ic@vector,,x*A0 downto &0 := ,other =I ExE0? 7e/in hi!t@re/i ter@proce : proce ,clk6r0 7e/in i! ,r = EAE0 then pre@9 B= ,other =I E&E0? el i! ,clkEevent and ,clk = EAE0 and ,clkEla t@value = E&E00 then i! ,ld = EAE0 then pre@9 B= din? el i! , e = EAE0 and ,dir@r = EAE0 then pre@9,,x*A00 B= i? pre@9,,x*%0 downto &0 B= pre@9,,x*A0 downto A0? el i! , e = EAE0 and ,dir@r = E&E0 then pre@9,,x*A0 downto A0 B= pre@9,,x*%0 downto &0? pre@9,&0 B= i? end i!? end i!? end proce hi!t@re/i ter@proce ? dout B= pre@9? o B= pre@9,&0 when dir@r = EAE el e pre@9,,x*A00 when dir@r = E&E el e ExE? end rtl?

TECHNOLOGY SCHEMATIC%

SIMULATION RESULTS%

;ES:LT: -eri!ied the output o! erial.parallel in erial.parallel out hi!t re/i ter u in/ -HDL4

EXPERIMENTB$&

STATE MACHINE WITH MEALY OUTPUT

AIM% To implement the tate machine with melay output u in/ -HDL4 PROGRAM CODE% li7rary ieee? u e ieee4 td@lo/ic@AA)+4all? entity ! m i port,x6clk:in td@lo/ic? y:out td@lo/ic0? end ! m? architecture mealy@ca e o! ! m i type tate@type i ,re et6/otA6/otA&0? i/nal tate: tate@type:=re et? 7e/in proce ,clk0 7e/in i! clk=E&E then ca e tate i when re et =I i! x=E&E then yB=E&E? tateB=re et? el e yB=E&E? tateB=/otA? end i!? when /otA =I i! x=E&E then yB=E&E? tateB=/otA&? el e yB=E&E? tateB=/otA? end i!? when /otA& =I i! x=E&E then yB=E&E? tateB=re et? el e yB=EAE? tateB=/otA? end i!? end ca e? end i!? end proce ? end mealy@ca e? TECHNOLOGY SCHEMATIC%

SIMULATION RESULTS%

RTL S*5em t!*

EXPERIMENTB$3

STATE MACHINE WITH MOORE OUTPUT:

AIM% To implement the tate machine with melay output u in/ -HDL4 PROGRAM CODE% li7rary ieee? u e ieee4 td@lo/ic@AA)+4all? entity ! m i port,x6clk : in td@lo/ic? y : out td@lo/ic0? end ! m? architecture moore@ca e o! ! m i type tate@type i ,re et6 /otA6 /otA&6 /otA&A0? i/nal tate: tate@type:=re et? 7e/in proce ,clk0 7e/in i! ,clk=E&E0 then ca e tate i when re et =I i! x=E&E then tateB=re et? el e tateB=/otA? end i!? when /otA =I i! x=E&E then tateB=/otA&? el e tateB=/otA? end i!? when /otA& =I i! x=E&E then tateB=re et? el e tateB=/otA&A? end i!? when /otA&A =I i! x=E&E then tateB=/otA&? el e tateB=/otA?

end i!? end ca e? end i!? i! tate=/otA&A then yB=EAE? el e yB=E&E? end i!? end proce ? end moore@ca e?

SIMULATION RESULTS%

RESULT : 'inite tate machine melay and moore output are veri!ied u in/ -HDL

EXPERIMENTB$9 ALU AIM% To ,e i/n a "L: per!ormin/ operation 4 PROGRAM CODE% li7rary ieee? u e ieee4 td@lo/ic@AA)+4all? u e ieee4 td@lo/ic@un i/ned4all? u e ieee4 td@lo/ic@arith4all? entity "L: i port , ": >: Sel: ;e : in td@lo/ic@vector,A downto &0? in td@lo/ic@vector,A downto &0? in td@lo/ic@vector,A downto &0? out td@lo/ic@vector,A downto &0 0?

end "L:? architecture 7ehv o! "L: i 7e/in proce ,"6>6Sel0 7e/in ca e Sel i when H&&H =I ;e B= " N >? when H&AH =I ;e B= " N ,not >0 N A? when HA&H =I ;e B= " and >? when HAAH =I ;e B= " or >? when other =I ;e B= H$$H? end ca e? end proce ? end 7ehv?

SIMULATION RESULTS%

TECHNOLOGY SCHEMATIC%

EXPERIMENTB$: RAM D$;69EB?9$AC AIM% To Simulate 1nternal tructure o! A)$+ ;"Q,1C F+AGJ0 u in/ -HDL and -eri!y it operation4 APPARATUS%

S7NO A4 %4

COMPONENT 1C F+AGJ Di/ital Trainer >oard

MUANTITY A A

SOFTWARE USED% $ilinx 1SE Suite A#4% ver ion

$;69 RAM DETAILS% TRUTH TA<LE% INPUT OPERATION CONDITION OF OUTPUT

CSO L

WEO L 3;1TE H18H 1QPEDENCE

;E"D

C<QPLEQENT <' ST<;ED D"T"

1NH1>1T

H18H 1QPENDENCE

INTERNAL DIAGRAM%

RAM OUTPUT EMUATIONS% 3rite = CSR3ER ;E"D = CSR3E 1NH1>1T = CS 3E VHDL CODE% li7rary 1EEE? u e 1EEE4 td@lo/ic@AA)+4all? entity ram i port , c : in STD@L<81C? we: in STD@L<81C? re: in STD@L<81C? mr: out STD@L<81C? mw: out STD@L<81C 0? end ram? architecture ram o! ram i 7e/in proce ,c 6we6re0 7e/in i! ,c =E&Eand we=EAEand re=E&E0then mrB=E&E? mwB=EAE? el i! ,c =E&Eand we=E&Eand re=EAE0then mrB=EAE? mwB=E&E? end i!? end proce ? end ram? PROCEDURE DSOFTWAREE% A0 'ollow 8ettin/ Started Procedure !or the So!tware you are u in/4 %0 DonPt !or/et to in tantiate 1EEE Li7rarie at the tartin/ o! the code4 PROCEDURE DHARDWAREE% A0 Connect the circuit a per the pin dia/ram4 %0 8ive proper -CC volta/e to the 1C4 #0 Supply the input accordin/ to truth ta7le and veri!y output 4 EXPECTED RESULTS DSOFTWAREE% c =E&Eand we =EAEand re =E&E memory read =E&E memory write = EAE c =E&Eand we=E&Eand re=EAE memory read =EAE memory write = E&E RESULTS DSOFTWAREE%

F!0% S!m2l t!"n Re.2lt. "1 RAM D$;69E

RESULT% $;69 RAM internal tructure i imulated and veri!ied u in/ xilinx So!tware4