Technische Universitt Mnchen

Chip Multicore Processors

Tutorial 6

S. Wallentowitz

Institute for Integrated Systems Theresienstr. 90 Building N1 www.lis.ei.tum.de

Technische Universitt Mnchen

Task 6.1: Cache Misses

Explain the 3 Cs of cache misses. How do they relate?

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Technische Universitt Mnchen

3 Cs Model
Compulsory:
Very first access to a data block Cannot be avoided

Capacity:
Restricted size leads to miss after replacement Would not have happened if cache was unlimited

Conflict:
Miss occurs due to prior replacement Would not have happened with full-associative caches

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Example for Contribution of each of the Cs

(c) Rochester Institute of Technology

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Technische Universitt Mnchen

Task 6.2: Multilevel Caches and separated instruction and data caches
In this tutorial we focus on the impact of the cache hierarchy on the performance of the system.

a) You have a simple system with a processor core, no caches and an external memory. The on-chip interconnect between the processor core and the memory requires 3 + x cycles for the transfer of x data words. The memory requires 46 cycles to access data. By using a benchmark you find that on average each fifth instruction accesses data. Your processor has a CPI of 1.8.
What is the CPI of your whole system?

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Simple System
Proc. Core Memory

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b)

You are using a direct-mapped cache of 32 kB and with cache blocks of 4 words (each 32 bit). The cache is accessed in one clock cycle. For your application you measure a miss rate of 5%. How does the CPI change?

Proc. Core

Cache

Memory

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c)
Proc. Core

Impressed by the improvement you add a second instance of this cache. How does the CPI change?

Cache

Cache

Memory

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Local vs. Global Miss Rate

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d)

Alternatively, you can use two other caches, each of total 256 kB. One of the caches is 2-way associative and has an access time of 4 cycles. The other cache is 4-way associative and has an access time of 6 cycles. The global miss rate is 4% for the first cache and 3% for the second cache. Which cache should be chosen?

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Institute for Integrated Systems

Technische Universitt Mnchen

Proc. Core

Cache
32 kB Direct-mapped 5% global miss rate 1 cycle

Cache
256 kB 2-way 4% global miss rate 4 cycles

Memory

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Institute for Integrated Systems

Technische Universitt Mnchen

Proc. Core

Cache
32 kB Direct-mapped 5% global miss rate 1 cycle

Cache
256 kB 4-way 3% global miss rate 6 cycles

Memory

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Institute for Integrated Systems

Technische Universitt Mnchen

e)

Explain the meaning of spatial and temporal locality in the context of instructions and data.

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Locality of data

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Locality of instructions

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f)

Based on your previous findings, exchange the level one cache with separate caches for instructions and data. The miss rate for instructions is 3% and for data 8%. Use the level 2 cache from d) and calculate the CPI value.

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