Notes

Microprocessor
Unit 1: 8086 CPU Architecture:
It is a 16-bit Microprocessor. It contains 29,000 transistors. Fabricated using HMOS technology (High density Metal Oxide Semiconductor). Number of address pins it has is 20. Hence the addressing capacity is 220 = 1Megabyte. It has multiprogramming features and hence can be used with 8087 Numeric data processor. Number of pins on the 8086 IC is 40. GND 2, Vcc 1, CLK 1, Address/Data/Control 20, Control 16. Voltage supply is +5V. Clock has a frequency of +5MHz. Internal configuration:

All the registers are 16-bit wide.

Data registers:
They can be used to store both operands and results. The upper and lower bits can be accessed separately. They are used in arithmetic operations. BX is used as a base register for address calculation. CX is used as a counter. DX is used to hold I/O address.

Pointers:
- The pointers used are SP, BP, SI, DI, and IP. - IP and SP are Program counter and Stack Pointers. - BP is used as a base register to access the stack. - SI and DI are used for indexing. There is an Instruction Queue which has 6 bytes for storing instructions. There are four Segment Registers used for flexible addressing. A data address is formed by adding BX or BP contents with SI or DI and a displacement. The address thus obtained is called Effective Address (EA) or Offset. The total Physical address is 20 bits and hence the address is formed by adding the EA with Segment register times 1610. A segment always starts with a multiple of 16.

Advantages of Segment Registers:

1. 2. 3. 4. 5. Memory is safely divided into different segments. Addressing capability of 8086 is increased to 20 bits. Multiple areas can be used for the same segment. The segment can be easily shifted. Overlapping of segments can take place to conserve space. It contains 16 bits. 7 are not used. Each bit is called a flag. There are two kinds of flags: Conditional and Control. Conditional flags reflect the result of the previous operation in the ALU. Control flags control the operations.

PSW:
-

1. 2. 3. 4. 5. 6. 7. 8. 9.

Carry: Set if there is carry out of MSB. Parity: Set if low order 8 bits contain an even number of 1s. Auxiliary Carry: Carry from 4th bit. Zero: Result is zero. Sign: MSB. Trap: Trap is executed after each instruction. Interrupt: Interrupts are recognized. Direction: String is processed from high addressed. Overflow: There is a carry into the MSB.

Internal Operation:
1. Fetching: The next instruction is fetched from address indicated by the PC. 2. Decoding: The fetched instruction is decoded after putting it in the instruction register. The PC is incremented to point to the next instruction.

3. Execution: The instruction once decoded is executed. The above steps are repeated. The address of the next instruction is calculated by adding (IP) and (CS) x 1610. The instruction register is 6 byte and is filled continuously when the system bus is not required. It is a First in/First out queue. This saves time because most of the times the next instruction is already in the queue before the fetching request. Increases the speed. Two bytes are fetched for an even address and one byte is fetched for an odd address.